;/*!
; * @file       APM32F00x_OPT.s
; *
; * @brief      modify the option byte area by OPT download algorithm
; *
; * @version    V1.0.0
; *
; * @date       2023-03-31
; *
; * @attention
; *
; *  Copyright (C) 2023 Geehy Semiconductor
; *
; *  You may not use this file except in compliance with the
; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
; *
; *  The program is only for reference, which is distributed in the hope
; *  that it will be useful and instructional for customers to develop
; *  their software. Unless required by applicable law or agreed to in
; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
; *  and limitations under the License.
; */
;/* <<< Use Configuration Wizard in Context Menu >>>                          */

;// <e> Flash Option Bytes
OB_Program      EQU     1

;//   <o0> Flash Read Protection
;//          <0xA5=> Disable <0xFF=> Enable
RDP             EQU     0xA5
nRDP            EQU     RDP:EOR:0xFF
;// <h> Flash Write Protection
;//   <o0.0> Page 0
;//   <o0.1> Page 1
;//   <o0.2> Page 2
;//   <o0.3> Page 3
;//   <o0.4> Page 4
;//   <o0.5> Page 5
;//   <o0.6> Page 6
;//   <o0.7> Page 7
;//   <o1.0> Page 8
;//   <o1.1> Page 9
;//   <o1.2> Page 10
;//   <o1.3> Page 11
;//   <o1.4> Page 12
;//   <o1.5> Page 13
;//   <o1.6> Page 14
;//   <o1.7> Page 15
;//   <o2.0> Page 16
;//   <o2.1> Page 17
;//   <o2.2> Page 18
;//   <o2.3> Page 19
;//   <o2.4> Page 20
;//   <o2.5> Page 21
;//   <o2.6> Page 22
;//   <o2.7> Page 23
;//   <o3.0> Page 24
;//   <o3.1> Page 25
;//   <o3.2> Page 26
;//   <o3.3> Page 27
;//   <o3.4> Page 28
;//   <o3.5> Page 29
;//   <o3.6> Page 30
;//   <o3.7> Page 31
;// </h>
nWRP0           EQU     0x00
nWRP1           EQU     0x00
nWRP2           EQU     0x00
nWRP3           EQU     0x00
WRP0            EQU     nWRP0:EOR:0xFF
WRP1            EQU     nWRP1:EOR:0xFF
WRP2            EQU     nWRP2:EOR:0xFF
WRP3            EQU     nWRP3:EOR:0xFF

;// <h> User Configuration
;//   <o0.0> WWDT_SW     
;//          <0=> HW Watchdog <1=> SW Watchdog
;//   <o0.1> WWDTRST  <i> Whether to reset in HALT mode when window watchdog is valid
;//          <0=> Enabled <1=> Disabled
;//   <o0.2> IWDTSW <i> Generate Reset when entering Standby Mode
;//          <0=> Enabled <1=> Disabled
;//   <o0.3> LIPCEN <i> LIRC Clock as CPU Clock Source
;//          <0=> Enabled <1=> Disabled
;//   <o0.4> HIRCTRIM <i> HIRCTRIM Register adjustment value set
;//          <0=> 4 bit <1=> 3 bit
;// </h>
USER            EQU     0xFF
nUSER           EQU     USER:EOR:0xFF

;// <h> User Data
;//   <o0> Data 0 <0x00-0xFF>
;//   <o1> Data 1 <0x00-0xFF>
;// </h>
DATA0           EQU     0x22
DATA1           EQU     0x16
nDATA0          EQU     DATA0:EOR:0xFF
nDATA1          EQU     DATA1:EOR:0xFF

;// <h> Reset mapping 
;//   <o0.0> AFP0 <i> PC5 as TMR2_CH1,PC6 as TMR1_CH1,PC7 as TMR1_CH2
;//          <0=> Enable <1=> Disable
;//   <o0.1> AFR1 <i> PA3 as SPI_NSS,PD2 as TMR2_CH3
;//          <0=> Enable <1=> Disable
;//   <o0.3> AFR3 <i> PC3 as TLI
;//          <0=> Enable <1=> Disable
;//   <o0.4> AFR4 <i> PB4 as ADC_ETR,PB5 as TMR1_BKIN
;//          <0=> Enable <1=> Disable
;//   <o0.5> AFR5 <i> PD5 as TMR1A_CH1N,PD6 as TMR1A_CH2N
;//          <0=> Enable <1=> Disable
;//   <o0.7> AFR7 <i> PC3 as TMR1_CH1N,PC6 as TMR1_CH1,PC4 as TMR2_CH2N
;//          <0=> Enable <1=> Disable
;// </h>
AFR            EQU     0xFF
nAFR           EQU     AFR:EOR:0xFF
RES            EQU     0xFF
nRES           EQU     RES:EOR:0xFF

;// <h> HXT Count 
;//   <o0> HXTCNT <i> set the HXT period
;//          <0x1E=> 0.5HXT <0x2D=> 8HXT <0x4B=> 128HXT <0xFF=> 2048HXT
;// </h>
HXTCNT         EQU     0xFF
nHXTCNT        EQU     HXTCNT:EOR:0xFF

;// <h> Clock Cnfiguration 
;//   <o0.0..1> WUPTDIV <i> Set the range of the pre_divider
;//          <0x00=> 4MHZ~128KHZ <0x01=> 8MHZ~128KHZ <0x03=> 16MHZ~128KHZ
;//   <o0.2> WUPTLIRC <i> Select the divider for clock source
;//          <0=> HXT <1=> LSI
;//   <o0.3> EXTCLK <i> Select the external clock source
;//          <0=> External clock sign in OSCIN
;//          <1=> External crystal conect in OSCIN/OSCOUT
;// </h>
COPT           EQU     0xFF
nCOPT          EQU     COPT:EOR:0xFF

;// </e>


               IF      OB_Program == 1
               AREA    |.ARM.__AT_0x00020400|, CODE, READONLY
               DCB     RDP,   nRDP,   USER,  nUSER
               DCB     DATA0, nDATA0, DATA1, nDATA1
               DCB     WRP0,  nWRP0,  WRP1,  nWRP1
               DCB     WRP2,  nWRP2,  WRP3,  nWRP3
               DCB     AFR,   nAFR,   RES,   nRES
               DCB     HXTCNT,nHXTCNT,COPT,  nCOPT
               ENDIF


               END
