/*!
 * @file        apm32f00x_int.h
 *
 * @brief       This file contains the headers of the interrupt handlers
 *
 * @version     V1.0.1
 *
 * @date        2023-03-31
 *
 * @attention
 *
 *  Copyright (C) 2023 Geehy Semiconductor
 *
 *  You may not use this file except in compliance with the
 *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 *
 *  The program is only for reference, which is distributed in the hope
 *  that it will be useful and instructional for customers to develop
 *  their software. Unless required by applicable law or agreed to in
 *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
 *  and limitations under the License.
 */

/* Define to prevent recursive inclusion */
#ifndef __APM32F00X_INT_H
#define __APM32F00X_INT_H

/* Includes */
#include "apm32f00x.h"
#include "main.h"
#include "bsp_flash.h"

/** @addtogroup Examples
  @{
*/

/** @addtogroup BootLoader
  @{
*/

/** @defgroup BootLoader_INT_Macros INT_Macros
  @{
*/

/* application 1 interrupt vector address */
#define     APP1_NonMaskableInt_IRQn_APP_ADDR          (uint32_t) (USER_APP1_ADDRESS+0x08)    /*!< 2 Non Maskable Interrupt                                */
#define     APP1_HardFault_IRQn_APP_ADDR               (uint32_t) (USER_APP1_ADDRESS+0x0C)    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
#define     APP1_SVC_IRQn_APP_ADDR                     (uint32_t) (USER_APP1_ADDRESS+0x2C)    /*!< 11 Cortex-M0 SV Call Interrupt                          */
#define     APP1_PendSV_IRQn_APP_ADDR                  (uint32_t) (USER_APP1_ADDRESS+0x38)    /*!< 14 Cortex-M0 Pend SV Interrupt                          */
#define     APP1_SysTick_IRQn_APP_ADDR                 (uint32_t) (USER_APP1_ADDRESS+0x3C)    /*!< 15 Cortex-M0 System Tick Interrupt                      */

#define     APP1_WUPT_IRQn_APP_ADDR                    (uint32_t) (USER_APP1_ADDRESS+0x44)    /*!< Wakeup timer                                            */
#define     APP1_RCM_IRQn_APP_ADDR                     (uint32_t) (USER_APP1_ADDRESS+0x48)    /*!< Clock controller interrupt                              */
#define     APP1_EINTA_IRQn_APP_ADDR                   (uint32_t) (USER_APP1_ADDRESS+0x4C)    /*!< Port A external interrupts                              */
#define     APP1_EINTB_IRQn_APP_ADDR                   (uint32_t) (USER_APP1_ADDRESS+0x50)    /*!< Port B external interrupts                              */
#define     APP1_EINTC_IRQn_APP_ADDR                   (uint32_t) (USER_APP1_ADDRESS+0x54)    /*!< Port C external interrupts                              */
#define     APP1_EINTD_IRQn_APP_ADDR                   (uint32_t) (USER_APP1_ADDRESS+0x58)    /*!< Port D external interrupts                              */

#define     APP1_SPI_IRQn_APP_ADDR                     (uint32_t) (USER_APP1_ADDRESS+0x68)    /*!< SPI Interrupt                                           */
#define     APP1_TMR1_UT_IRQn_APP_ADDR                 (uint32_t) (USER_APP1_ADDRESS+0x6C)    /*!< TIMER1 update/overflow/underflow/trigger/break interrupt  */
#define     APP1_TMR1_CC_IRQn_APP_ADDR                 (uint32_t) (USER_APP1_ADDRESS+0x70)    /*!< TIMER1 capture/compare interrupt                          */
#define     APP1_TMR2_UO_IRQn_APP_ADDR                 (uint32_t) (USER_APP1_ADDRESS+0x74)    /*!< TIMER2 update /overflow interrupt                         */
#define     APP1_TMR2_CC_IRQn_APP_ADDR                 (uint32_t) (USER_APP1_ADDRESS+0x78)    /*!< TIMER2 capture/compare interrupt                          */
#define     APP1_USART1_TX_IRQn_APP_ADDR               (uint32_t) (USER_APP1_ADDRESS+0x84)    /*!< USART1 TX interrupt                                      */
#define     APP1_USART1_RX_IRQn_APP_ADDR               (uint32_t) (USER_APP1_ADDRESS+0x88)    /*!< USART1 RX interrupt                                      */
#define     APP1_IIC_IRQn_APP_ADDR                     (uint32_t) (USER_APP1_ADDRESS+0x8C)    /*!< I2C Interrupt                                           */
#define     APP1_ADC_IRQn_APP_ADDR                     (uint32_t) (USER_APP1_ADDRESS+0x98)    /*!< ADC interrupt                                          */
#define     APP1_TMR4_IRQn_APP_ADDR                    (uint32_t) (USER_APP1_ADDRESS+0x9C)    /*!< TIMER4 update /overflow interrupt                         */
#define     APP1_FLASH_IRQn_APP_ADDR                   (uint32_t) (USER_APP1_ADDRESS+0xA0)    /*!< Flash interrupt                                         */
#define     APP1_USART2_TX_IRQn_APP_ADDR               (uint32_t) (USER_APP1_ADDRESS+0xAC)    /*!< USART2 TX interrupt                                      */
#define     APP1_USART2_RX_IRQn_APP_ADDR               (uint32_t) (USER_APP1_ADDRESS+0xB0)    /*!< USART2 RX interrupt                                      */
#define     APP1_TMR1A_UT_IRQn_APP_ADDR                (uint32_t) (USER_APP1_ADDRESS+0xB4)    /*!< TIMER1A update/overflow/underflow/trigger/break interrupt */
#define     APP1_TMR1A_CC_IRQn_APP_ADDR                (uint32_t) (USER_APP1_ADDRESS+0xB8)    /*!< TIMER1A capture/compare interrupt                         */

/* application 2 interrupt vector address */
#define     APP2_NonMaskableInt_IRQn_APP_ADDR          (uint32_t) (USER_APP2_ADDRESS+0x08)    /*!< 2 Non Maskable Interrupt                                */
#define     APP2_HardFault_IRQn_APP_ADDR               (uint32_t) (USER_APP2_ADDRESS+0x0C)    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
#define     APP2_SVC_IRQn_APP_ADDR                     (uint32_t) (USER_APP2_ADDRESS+0x2C)    /*!< 11 Cortex-M0 SV Call Interrupt                          */
#define     APP2_PendSV_IRQn_APP_ADDR                  (uint32_t) (USER_APP2_ADDRESS+0x38)    /*!< 14 Cortex-M0 Pend SV Interrupt                          */
#define     APP2_SysTick_IRQn_APP_ADDR                 (uint32_t) (USER_APP2_ADDRESS+0x3C)    /*!< 15 Cortex-M0 System Tick Interrupt                      */

#define     APP2_WUPT_IRQn_APP_ADDR                    (uint32_t) (USER_APP2_ADDRESS+0x44)    /*!< Wakeup timer                                            */
#define     APP2_RCM_IRQn_APP_ADDR                     (uint32_t) (USER_APP2_ADDRESS+0x48)    /*!< Clock controller interrupt                              */
#define     APP2_EINTA_IRQn_APP_ADDR                   (uint32_t) (USER_APP2_ADDRESS+0x4C)    /*!< Port A external interrupts                              */
#define     APP2_EINTB_IRQn_APP_ADDR                   (uint32_t) (USER_APP2_ADDRESS+0x50)    /*!< Port B external interrupts                              */
#define     APP2_EINTC_IRQn_APP_ADDR                   (uint32_t) (USER_APP2_ADDRESS+0x54)    /*!< Port C external interrupts                              */
#define     APP2_EINTD_IRQn_APP_ADDR                   (uint32_t) (USER_APP2_ADDRESS+0x58)    /*!< Port D external interrupts                              */

#define     APP2_SPI_IRQn_APP_ADDR                     (uint32_t) (USER_APP2_ADDRESS+0x68)    /*!< SPI Interrupt                                           */
#define     APP2_TMR1_UT_IRQn_APP_ADDR                 (uint32_t) (USER_APP2_ADDRESS+0x6C)    /*!< TIMER1 update/overflow/underflow/trigger/break interrupt  */
#define     APP2_TMR1_CC_IRQn_APP_ADDR                 (uint32_t) (USER_APP2_ADDRESS+0x70)    /*!< TIMER1 capture/compare interrupt                          */
#define     APP2_TMR2_UO_IRQn_APP_ADDR                 (uint32_t) (USER_APP2_ADDRESS+0x74)    /*!< TIMER2 update /overflow interrupt                         */
#define     APP2_TMR2_CC_IRQn_APP_ADDR                 (uint32_t) (USER_APP2_ADDRESS+0x78)    /*!< TIMER2 capture/compare interrupt                          */
#define     APP2_USART1_TX_IRQn_APP_ADDR               (uint32_t) (USER_APP2_ADDRESS+0x84)    /*!< USART1 TX interrupt                                      */
#define     APP2_USART1_RX_IRQn_APP_ADDR               (uint32_t) (USER_APP2_ADDRESS+0x88)    /*!< USART1 RX interrupt                                      */
#define     APP2_IIC_IRQn_APP_ADDR                     (uint32_t) (USER_APP2_ADDRESS+0x8C)    /*!< I2C Interrupt                                           */
#define     APP2_ADC_IRQn_APP_ADDR                     (uint32_t) (USER_APP2_ADDRESS+0x98)    /*!< ADC interrupt                                          */
#define     APP2_TMR4_IRQn_APP_ADDR                    (uint32_t) (USER_APP2_ADDRESS+0x9C)    /*!< TIMER4 update /overflow interrupt                         */
#define     APP2_FLASH_IRQn_APP_ADDR                   (uint32_t) (USER_APP2_ADDRESS+0xA0)    /*!< Flash interrupt                                         */
#define     APP2_USART2_TX_IRQn_APP_ADDR               (uint32_t) (USER_APP2_ADDRESS+0xAC)    /*!< USART2 TX interrupt                                      */
#define     APP2_USART2_RX_IRQn_APP_ADDR               (uint32_t) (USER_APP2_ADDRESS+0xB0)    /*!< USART2 RX interrupt                                      */
#define     APP2_TMR1A_UT_IRQn_APP_ADDR                (uint32_t) (USER_APP2_ADDRESS+0xB4)    /*!< TIMER1A update/overflow/underflow/trigger/break interrupt */
#define     APP2_TMR1A_CC_IRQn_APP_ADDR                (uint32_t) (USER_APP2_ADDRESS+0xB8)    /*!< TIMER1A capture/compare interrupt                         */

/**@} end of group BootLoader_INT_Macros */

/** @defgroup BootLoader_INT_Enumeration INT_Enumeration
  @{
*/

/**
 * @brief   INTERRUPT_VECTOR_STATE_T
 */
typedef enum
{
    IAP_INTERRUPT_VECTOR    = ((uint8_t)0), //!< IAP interrupt vector
    APP1_INTERRUPT_VECTOR   = ((uint8_t)1), //!< APP1 interrupt vector
    APP2_INTERRUPT_VECTOR   = ((uint8_t)2), //!< APP2 interrupt vector
} INTERRUPT_VECTOR_STATE_T;

/**@} end of group BootLoader_INT_Enumeration */

/** @defgroup BootLoader_INT_Variables INT_Variables
  @{
*/

extern uint32_t FLASH_interrupt_vector;

/**@} end of group BootLoader_INT_Variables */

/** @defgroup BootLoader_INT_Functions INT_Functions
  @{
*/

void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);

void WUPT_IRQHandler(void);
void RCM_IRQHandler(void);
void EINTA_IRQHandler(void);
void EINTB_IRQHandler(void);
void EINTC_IRQHandler(void);
void EINTD_IRQHandler(void);

void SPI_IRQHandler(void);
void TMR1_UT_IRQHandler(void);
void TMR1_CC_IRQHandler(void);
void TMR2_UO_IRQHandler(void);
void TMR2_CC_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void IIC_IRQHandler(void);
void ADC_IRQHandler(void);
void TMR4_IRQHandler(void);
void FLASH_IRQHandler(void);
void USART2_TX_IRQHandler(void);
void USART2_RX_IRQHandler(void);
void TMR1A_UT_IRQHandler(void);
void TMR1A_CC_IRQHandler(void);

/**@} end of group BootLoader_INT_Functions */
/**@} end of group BootLoader */
/**@} end of group Examples */

#endif
