/*!
 * @file        apm32f446.h
 *
 * @brief       CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
 *
 * @details     This file contains all the peripheral register's definitions, bits definitions and memory mapping
 *
 * @version     V1.0.0
 *
 * @date        2026-01-31
 *
 * @attention
 *
 *  Copyright (C) 2026 Geehy Semiconductor
 *
 *  You may not use this file except in compliance with the
 *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 *
 *  The program is only for reference, which is distributed in the hope
 *  that it will be useful and instructional for customers to develop
 *  their software. Unless required by applicable law or agreed to in
 *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
 *  and limitations under the License.
 */


/** @addtogroup APM32F445_446
  * @{
  */


#ifndef APM32F445_446_H
#define APM32F445_446_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Enum_IRQn_Type
  * @{
  */

/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */
typedef enum {
  NotAvail_IRQn             = -128,             /* Not available device specific interrupt */
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ====================================== */
  Reset_IRQn                = -15,              /* -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /* -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /* -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /* -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                            */
  BusFault_IRQn             = -11,              /* -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                           */
  UsageFault_IRQn           = -10,              /* -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /* -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /* -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /* -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /* -1 System Tick Timer                                                      */
/* =========================================  APM32F446 Specific Interrupt Numbers  =========================================== */
  DMA0_IRQn                 =   0U,              /* 0  DMA0                                                                   */
  DMA1_IRQn                 =   1U,              /* 1  DMA1                                                                   */
  DMA2_IRQn                 =   2U,              /* 2  DMA2                                                                   */
  DMA3_IRQn                 =   3U,              /* 3  DMA3                                                                   */
  DMA4_IRQn                 =   4U,              /* 4  DMA4                                                                   */
  DMA5_IRQn                 =   5U,              /* 5  DMA5                                                                   */
  DMA6_IRQn                 =   6U,              /* 6  DMA6                                                                   */
  DMA7_IRQn                 =   7U,              /* 7  DMA7                                                                   */
  DMA8_IRQn                 =   8U,              /* 8  DMA8                                                                   */
  DMA9_IRQn                 =   9U,              /* 9  DMA9                                                                   */
  DMA10_IRQn                =  10U,              /* 10 DMA10                                                                  */
  DMA11_IRQn                =  11U,              /* 11 DMA11                                                                  */
  DMA12_IRQn                =  12U,              /* 12 DMA12                                                                  */
  DMA13_IRQn                =  13U,              /* 13 DMA13                                                                  */
  DMA14_IRQn                =  14U,              /* 14 DMA14                                                                  */
  DMA15_IRQn                =  15U,              /* 15 DMA15                                                                  */
  DMA_Error_IRQn            =  16U,              /* 16 DMA_Error                                                              */
  MC_IRQn                   =  17U,              /* 17 MC                                                                     */
  FLASH_IRQn                =  18U,              /* 18 FLASH                                                                  */
  Read_Collision_IRQn       =  19U,              /* 19 Read_Collision                                                         */
  LVD_LVW_IRQn              =  20U,              /* 20 LVD_LVW                                                                */
  FLASH_Fault_IRQn          =  21U,              /* 21 FLASH_Fault                                                            */
  WDT_EWDT_IRQn             =  22U,              /* 22 WDT_EWDT                                                               */
  RMU_IRQn                  =  23U,              /* 23 RMU                                                                    */
  LPI2C_Master_IRQn         =  24U,              /* 24 LPI2C_Master                                                           */
  LPI2C_Slave_IRQn          =  25U,              /* 25 LPI2C_Slave                                                            */
  LPSPI0_IRQn               =  26U,              /* 26 LPSPI0                                                                 */
  LPSPI1_IRQn               =  27U,              /* 27 LPSPI1                                                                 */
  LPSPI2_IRQn               =  28U,              /* 28 LPSPI2                                                                 */
  LPUART0_RxTx_IRQn         =  31U,              /* 31 LPUART0_RxTx                                                           */
  LPUART1_RxTx_IRQn         =  33U,              /* 33 LPUART1_RxTx                                                           */
  LPUART2_RxTx_IRQn         =  35U,              /* 35 LPUART2_RxTx                                                           */
  ADC0_IRQn                 =  39U,              /* 39 ADC0                                                                   */
  ADC1_IRQn                 =  40U,              /* 40 ADC1                                                                   */
  COMP_IRQn                 =  41U,              /* 41 COMP                                                                   */
  EREP_single_fault_IRQn    =  44U,              /* 44 EREP_single_fault                                                      */
  EREP_double_fault_IRQn    =  45U,              /* 45 EREP_double_fault                                                      */
  RTC_IRQn                  =  46U,              /* 46 RTC                                                                    */
  RTC_Seconds_IRQn          =  47U,              /* 47 RTC_Seconds                                                            */
  LPITMR_Ch0_IRQn           =  48U,              /* 48 LPITMR_Ch0                                                             */
  LPITMR_Ch1_IRQn           =  49U,              /* 49 LPITMR_Ch1                                                             */
  LPITMR_Ch2_IRQn           =  50U,              /* 50 LPITMR_Ch2                                                             */
  LPITMR_Ch3_IRQn           =  51U,              /* 51 LPITMR_Ch3                                                             */
  PDU0_IRQn                 =  52U,              /* 52 PDU0                                                                   */
  SCG_IRQn                  =  57U,              /* 57 SCG                                                                    */
  LPTMR_IRQn                =  58U,              /* 58 LPTMR                                                                  */
  PMA_IRQn                  =  59U,              /* 59 PMA                                                                    */
  PMB_IRQn                  =  60U,              /* 60 PMB                                                                    */
  PMC_IRQn                  =  61U,              /* 61 PMC                                                                    */
  PMD_IRQn                  =  62U,              /* 62 PMD                                                                    */
  PME_IRQn                  =  63U,              /* 63 PME                                                                    */
  SWI_IRQn                  =  64U,              /* 64 SWI                                                                    */
  PDU1_IRQn                 =  68U,              /* 68 PDU1                                                                   */
  CFGIO_IRQn                =  69U,         /* 69 CFGIO                                                                 */
  CAN0_ORed_IRQn            =  78U,         /* 78 CAN0_ORed                                                           */
  CAN0_Error_IRQn           =  79U,         /* 79 CAN0_Error                                                          */
  CAN0_Wake_Up_IRQn         =  80U,         /* 80 CAN0_Wake_Up                                                        */
  CAN0_ORed_0_15_MB_IRQn    =  81U,         /* 81 CAN0_ORed_0_15_MB                                                   */
  CAN0_ORed_16_31_MB_IRQn   =  82U,         /* 82 CAN0_ORed_16_31_MB                                                  */
  CAN1_ORed_IRQn            =  85U,         /* 85 CAN1_ORed                                                           */
  CAN1_Error_IRQn           =  86U,         /* 86 CAN1_Error                                                          */
  CAN1_ORed_0_15_MB_IRQn    =  88U,         /* 88 CAN1_ORed_0_15_MB                                                   */
  CAN1_ORed_16_31_MB_IRQn   =  89U,         /* 88 CAN1_ORed_16_31_MB                                                   */
  CAN2_ORed_IRQn            =  92U,         /* 92 CAN2_ORed                                                           */
  CAN2_Error_IRQn           =  93U,         /* 93 CAN2_Error                                                          */
  CAN2_ORed_0_15_MB_IRQn    =  95U,         /* 95 CAN2_ORed_0_15_MB                                                   */
  CFGTMR0_Ch0_Ch1_IRQn        =  99U,             /* 99 CFGTMR0_Ch0_Ch1                                                           */
  CFGTMR0_Ch2_Ch3_IRQn        = 100U,             /* 100  CFGTMR0_Ch2_Ch3                                                         */
  CFGTMR0_Ch4_Ch5_IRQn        = 101U,             /* 101  CFGTMR0_Ch4_Ch5                                                         */
  CFGTMR0_Ch6_Ch7_IRQn        = 102U,             /* 102  CFGTMR0_Ch6_Ch7                                                         */
  CFGTMR0_Fault_IRQn          = 103U,             /* 103  CFGTMR0_Fault                                                           */
  CFGTMR0_Ovf_Reload_IRQn     = 104U,             /* 104  CFGTMR0_Ovf_Reload                                                      */
  CFGTMR1_Ch0_Ch1_IRQn        = 105U,             /* 105  CFGTMR1_Ch0_Ch1                                                         */
  CFGTMR1_Ch2_Ch3_IRQn        = 106U,             /* 106  CFGTMR1_Ch2_Ch3                                                         */
  CFGTMR1_Ch4_Ch5_IRQn        = 107U,             /* 107  CFGTMR1_Ch4_Ch5                                                         */
  CFGTMR1_Ch6_Ch7_IRQn        = 108U,             /* 108  CFGTMR1_Ch6_Ch7                                                         */
  CFGTMR1_Fault_IRQn          = 109U,             /* 109  CFGTMR1_Fault                                                           */
  CFGTMR1_Ovf_Reload_IRQn     = 110U,             /* 110  CFGTMR1_Ovf_Reload                                                      */
  CFGTMR2_Ch0_Ch1_IRQn        = 111U,             /* 111  CFGTMR2_Ch0_Ch1                                                         */
  CFGTMR2_Ch2_Ch3_IRQn        = 112U,             /* 112  CFGTMR2_Ch2_Ch3                                                         */
  CFGTMR2_Ch4_Ch5_IRQn        = 113U,             /* 113  CFGTMR2_Ch4_Ch5                                                         */
  CFGTMR2_Ch6_Ch7_IRQn        = 114U,             /* 114  CFGTMR2_Ch6_Ch7                                                         */
  CFGTMR2_Fault_IRQn          = 115U,             /* 115  CFGTMR2_Fault                                                           */
  CFGTMR2_Ovf_Reload_IRQn     = 116U,             /* 116  CFGTMR2_Ovf_Reload                                                      */
  CFGTMR3_Ch0_Ch1_IRQn        = 117U,             /* 117  CFGTMR3_Ch0_Ch1                                                         */
  CFGTMR3_Ch2_Ch3_IRQn        = 118U,             /* 118  CFGTMR3_Ch2_Ch3                                                         */
  CFGTMR3_Ch4_Ch5_IRQn        = 119U,             /* 119  CFGTMR3_Ch4_Ch5                                                         */
  CFGTMR3_Ch6_Ch7_IRQn        = 120U,             /* 120  CFGTMR3_Ch6_Ch7                                                         */
  CFGTMR3_Fault_IRQn          = 121U,             /* 121  CFGTMR3_Fault                                                           */
  CFGTMR3_Ovf_Reload_IRQn     = 122U,             /* 122  CFGTMR3_Ovf_Reload                                                      */
  CFGTMR4_Ch0_Ch1_IRQn        = 123u,             /**< CFGTMR4 Channel 0 and 1 interrupt                                          */
  CFGTMR4_Ch2_Ch3_IRQn        = 124u,             /**< CFGTMR4 Channel 2 and 3 interrupt                                          */
  CFGTMR4_Ch4_Ch5_IRQn        = 125u,             /**< CFGTMR4 Channel 4 and 5 interrupt                                          */
  CFGTMR4_Ch6_Ch7_IRQn        = 126u,             /**< CFGTMR4 Channel 6 and 7 interrupt                                          */
  CFGTMR4_Fault_IRQn          = 127u,             /**< CFGTMR4 Fault interrupt                                                    */
  CFGTMR4_Ovf_Reload_IRQn     = 128u,             /**< CFGTMR4 Counter overflow and Reload interrupt                              */
  CFGTMR5_Ch0_Ch1_IRQn        = 129u,             /**< CFGTMR5 Channel 0 and 1 interrupt                                          */
  CFGTMR5_Ch2_Ch3_IRQn        = 130u,             /**< CFGTMR5 Channel 2 and 3 interrupt                                          */
  CFGTMR5_Ch4_Ch5_IRQn        = 131u,             /**< CFGTMR5 Channel 4 and 5 interrupt                                          */
  CFGTMR5_Ch6_Ch7_IRQn        = 132u,             /**< CFGTMR5 Channel 6 and 7 interrupt                                          */
  CFGTMR5_Fault_IRQn          = 133u,             /**< CFGTMR5 Fault interrupt                                                    */
  CFGTMR5_Ovf_Reload_IRQn     = 134u              /**< CFGTMR5 Counter overflow and Reload interrupt                              */
} IRQn_Type;

/** @} */ /* End of group Enum_IRQn_Type */

/** @addtogroup Configuration_of_CMSIS
  * @{
  */
/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                      1U        /* CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               4U        /* Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0U        /* Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  0U        /* MPU present                                                               */
#define __FPU_PRESENT                  1U        /* FPU present                                                               */

/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /* ARM Cortex-M4 processor and core peripherals                               */
#include "apm_core_cm4.h"
#include "system_apm32f445_446.h"                     /* APM32F445_446 System                                                            */

/** @addtogroup Exported_Types
  * @{
  */

#ifndef __IM
#define __IM   __I
#endif
#ifndef __OM
#define __OM   __O
#endif
#ifndef __IOM
#define __IOM  __IO
#endif
/** @} */ /* End of group Exported_Types */

/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
  * @{
  */
/* =========================================================================================================================== */
/* ================                                         CSE_PRAM                                          ================ */
/* =========================================================================================================================== */

/**
  * @brief CSE_PRAM (CSE_PRAM)
  */

/** CSE_PRAM - Size of Registers Arrays */
#define CSE_PRAM_RAMn_COUNT                      32U

/** CSE_PRAM - Register Layout Typedef */
typedef struct {
  union {                                  /* offset: 0x0, array step: 0x4                                                      */
    __IO uint32_t DATA_32;                 /* CSE PRAM 0 Register..CSE PRAM 31 Register, array offset: 0x0, array step: 0x4     */
    struct {                               /* offset: 0x0, array step: 0x4                                                      */
      __IO uint8_t DATA_8LL;               /* CSE PRAM0LL register...CSE PRAM31LL register., array offset: 0x0, array step: 0x4 */
      __IO uint8_t DATA_8LU;               /* CSE PRAM0LU register...CSE PRAM31LU register., array offset: 0x1, array step: 0x4 */
      __IO uint8_t DATA_8HL;               /* CSE PRAM0HL register...CSE PRAM31HL register., array offset: 0x2, array step: 0x4 */
      __IO uint8_t DATA_8HU;               /* CSE PRAM0HU register...CSE PRAM31HU register., array offset: 0x3, array step: 0x4 */
    } ACCESS8BIT;
  } RAMn[CSE_PRAM_RAMn_COUNT];
} CSE_PRAM_T;


/* =========================================================================================================================== */
/* ================                                            AC                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Access Controller (AC)
  */

typedef struct {                                /* (@ 0x40000000) AC Structure                                               */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Master Privilege Register A                                */

    struct {
      __IM  uint32_t RESERVED0  : 16;
      __IOM uint32_t MPLCFG3    : 1;            /* [16..16] Master 3 Privilege Level Configure                               */
      __IOM uint32_t MTWA3      : 1;            /* [17..17] Master 3 Trusted For Writes                                      */
      __IOM uint32_t MTRA3      : 1;            /* [18..18] Master 3 Trusted For Read                                        */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t MPLCFG2    : 1;            /* [20..20] Master 2 Privilege Level Configure                               */
      __IOM uint32_t MTWA2      : 1;            /* [21..21] Master 2 Trusted For Writes                                      */
      __IOM uint32_t MTRA2      : 1;            /* [22..22] Master 2 Trusted For Read                                        */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t MPLCFG1    : 1;            /* [24..24] Master 1 Privilege Level Configure                               */
      __IOM uint32_t MTWA1      : 1;            /* [25..25] Master 1 Trusted for Writes                                      */
      __IOM uint32_t MTRA1      : 1;            /* [26..26] Master 1 Trusted for Read                                        */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t MPLCFG0    : 1;            /* [28..28] Master 0 Privilege Level Configure                               */
      __IOM uint32_t MTWA0      : 1;            /* [29..29] Master 0 Trusted For Writes                                      */
      __IOM uint32_t MTRA0      : 1;            /* [30..30] Master 0 Trusted For Read                                        */
      __IM  uint32_t RESERVED4  : 1;
    } bit;
  } MPRIA;
  __IM  uint32_t  RESERVED[7];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Peripheral Access Control Register A                       */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
    } bit;
  } PACCTRLA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) Peripheral Access Control Register B                       */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 13;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
    } bit;
  } PACCTRLB;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000002C) Peripheral Access Control Register D                       */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
    } bit;
  } PACCTRLD;
  __IM  uint32_t  RESERVED2[4];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Off-Platform Peripheral Access Control Register A          */

    struct {
      __IOM uint32_t TPCFG7     : 1;            /* [0..0] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG7     : 1;            /* [1..1] Write Protect Configure                                            */
      __IOM uint32_t SPCFG7     : 1;            /* [2..2] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 9;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED5  : 1;
    } bit;
  } OPACCTRLA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000044) Off-Platform Peripheral Access Control Register B          */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 13;
    } bit;
  } OPACCTRLB;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000048) Off-Platform Peripheral Access Control Register C          */

    struct {
      __IOM uint32_t TPCFG7     : 1;            /* [0..0] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG7     : 1;            /* [1..1] Write Protect Configure                                            */
      __IOM uint32_t SPCFG7     : 1;            /* [2..2] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 13;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 5;
    } bit;
  } OPACCTRLC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000004C) Off-Platform Peripheral Access Control Register D          */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED5  : 1;
    } bit;
  } OPACCTRLD;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000050) Off-Platform Peripheral Access Control Register E          */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 21;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
    } bit;
  } OPACCTRLE;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000054) Off-Platform Peripheral Access Control Register F         */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 1;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED5  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED6  : 1;
    } bit;
  } OPACCTRLF;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000058) Off-Platform Peripheral Access Control Register G         */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 5;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 9;
    } bit;
  } OPACCTRLG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000005C) Off-Platform Peripheral Access Control Register H          */

    struct {
      __IM  uint32_t RESERVED4  : 20;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED5  : 9;
    } bit;
  } OPACCTRLH;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000060) Off-Platform Peripheral Access Control Register I          */

    struct {
      __IOM uint32_t TPCFG7    : 1;            /* [0..0] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG7     : 1;            /* [1..1] Write Protect Configure                                            */
      __IOM uint32_t SPCFG7     : 1;            /* [2..2] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 5;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED5  : 5;
    } bit;
  } OPACCTRLI;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000064) Off-Platform Peripheral Access Control Register J          */

    struct {
      __IOM uint32_t TPCFG7     : 1;            /* [0..0] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG7     : 1;            /* [1..1] Write Protect Configure                                            */
      __IOM uint32_t SPCFG7     : 1;            /* [2..2] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t TPCFG4     : 1;            /* [12..12] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG4     : 1;            /* [13..13] Write Protect Configure                                          */
      __IOM uint32_t SPCFG4     : 1;            /* [14..14] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG2     : 1;            /* [20..20] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG2     : 1;            /* [21..21] Write Protect Configure                                          */
      __IOM uint32_t SPCFG2     : 1;            /* [22..22] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 9;
    } bit;
  } OPACCTRLJ;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000068) Off-Platform Peripheral Access Control Register K          */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 9;
      __IOM uint32_t TPCFG3     : 1;            /* [16..16] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG3     : 1;            /* [17..17] Write Protect Configure                                          */
      __IOM uint32_t SPCFG3     : 1;            /* [18..18] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 5;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TPCFG0     : 1;            /* [28..28] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG0     : 1;            /* [29..29] Write Protect Configure                                          */
      __IOM uint32_t SPCFG0     : 1;            /* [30..30] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED4  : 1;
    } bit;
  } OPACCTRLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000006C) Off-Platform Peripheral Access Control Register L          */

    struct {
      __IOM uint32_t TPCFG7     : 1;            /* [0..0] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG7     : 1;            /* [1..1] Write Protect Configure                                            */
      __IOM uint32_t SPCFG7     : 1;            /* [2..2] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TPCFG6     : 1;            /* [4..4] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG6     : 1;            /* [5..5] Write Protect Configure                                            */
      __IOM uint32_t SPCFG6     : 1;            /* [6..6] Supervisor Protect Configure                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TPCFG5     : 1;            /* [8..8] Trusted Protect Configure                                          */
      __IOM uint32_t WPCFG5     : 1;            /* [9..9] Write Protect Configure                                            */
      __IOM uint32_t SPCFG5     : 1;            /* [10..10] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED2  : 13;
      __IOM uint32_t TPCFG1     : 1;            /* [24..24] Trusted Protect Configure                                        */
      __IOM uint32_t WPCFG1     : 1;            /* [25..25] Write Protect Configure                                          */
      __IOM uint32_t SPCFG1     : 1;            /* [26..26] Supervisor Protect Configure                                     */
      __IM  uint32_t RESERVED3  : 5;
    } bit;
  } OPACCTRLL;
} AC_T;                                      /* Size = 112 (0x70)                                                            */



/* =========================================================================================================================== */
/* ================                                            MSC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Miscellaneous System Control (MSC)
  */

typedef struct {                                /* (@ 0x40001000) MSC Structure                                              */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Processor X Type Register                                  */

    struct {
      __IM  uint32_t CPUxREV    : 8;            /* [7..0] CPUx Processor Revision                                            */
      __IM  uint32_t CPUxSEQ    : 24;           /* [31..8] CPUx Processor Specific Sequence                                  */
    } bit;
  } PCxTYPE;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) CPUx Logical Processor Number Register                     */

    struct {
      __IM  uint32_t CPUxLPNUM  : 1;            /* [0..0] CPUx Logical Processor Number                                      */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } CPUxLPNUM;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000008) CPUx Physical Bus Master Number Register                   */

    struct {
      __IM  uint32_t CPUxPBMNUM : 6;            /* [5..0] CPUx Physical Bus Master Number                                    */
      __IM  uint32_t RESERVED0  : 26;
    } bit;
  } CPUxPBMNUM;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000000C) CPUx Count Register                                        */

    struct {
      __IM  uint32_t PCNT       : 2;            /* [1..0] Processor Count                                                    */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } CPUxCNT;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000010) Processor X Information Register 0                         */

    struct {
      __IM  uint32_t DCWNUML1   : 8;            /* [7..0] Number of Level 1 Data Cache Way                                   */
      __IM  uint32_t DCSIZEL1   : 8;            /* [15..8] Level 1 Data Cache Size                                           */
      __IM  uint32_t ICWNUML1   : 8;            /* [23..16] Number of Level 1 Instruction Cache Way                          */
      __IM  uint32_t ICSIZEL1   : 8;            /* [31..24] Level 1 Instruction Cache Size                                   */
    } bit;
  } PCxINF0;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000014) Processor X Information Register 1                         */

    struct {
      __IM  uint32_t RESERVED0  : 16;
      __IM  uint32_t ICWNUML2   : 8;            /* [23..16] Number of Level 2 Instruction Cache Way                          */
      __IM  uint32_t ICSIZEL2   : 8;            /* [31..24] Level 2 Instruction Cache Size                                   */
    } bit;
  } PCxINF1;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000018) Processor X Information Register 2                         */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IM  uint32_t TCMHSIZE   : 8;            /* [15..8] Tightly-Coupled Memory Higher Size                                */
      __IM  uint32_t RESERVED1  : 8;
      __IM  uint32_t TCMLSIZE   : 8;            /* [31..24] Tightly-Coupled Memory Lower Size                                */
    } bit;
  } PCxINF2;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000001C) Processor X Information Register 3                         */

    struct {
      __IM  uint32_t FPUFLG     : 1;            /* [0..0] Support Floating Point Unit Flag                                   */
      __IM  uint32_t ISEFLG     : 1;            /* [1..1] Support Instruction Set Extension                                  */
      __IM  uint32_t JHWFLG     : 1;            /* [2..2] Support Jazelle Hardware Flag                                      */
      __IM  uint32_t MMFLG      : 1;            /* [3..3] Support Memory Management Unit Flag                                */
      __IM  uint32_t TZFFLG     : 1;            /* [4..4] Support Trust Zone Function Flag                                   */
      __IM  uint32_t CMPHWFLG   : 1;            /* [5..5] Support Core Memory Protection Hardware Flag                       */
      __IM  uint32_t BBFLG      : 1;            /* [6..6] Support Bit Banding Flag                                           */
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t SYSBPNUM   : 2;            /* [9..8] Number of System Bus Ports                                         */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } PCxINF3;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000020) Processor 0 Type Register                                  */

    struct {
      __IM  uint32_t CPU0REV    : 8;            /* [7..0] CPU0 Processor Revision                                            */
      __IM  uint32_t CPU0SEQ    : 24;           /* [31..8] CPU0 Processor Specific Sequence                                  */
    } bit;
  } PC0TYPE;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000024) CPU0 Logical Processor Number Register                     */

    struct {
      __IM  uint32_t CPU0LPNUM  : 1;            /* [0..0] Processor 0 Number                                                 */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } CPU0LPNUM;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000028) CPU0 Physical Bus Master Number Register                   */

    struct {
      __IM  uint32_t CPU0PBMNUM : 6;            /* [5..0] CPU0 Physical Bus Master Number                                    */
      __IM  uint32_t RESERVED0  : 26;
    } bit;
  } CPU0PBNUM;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000002C) CPU0 Count Register                                        */

    struct {
      __IM  uint32_t PCNT       : 2;            /* [1..0] Processor Count                                                    */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } CPU0CNT;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000030) Processor 0 Information Register 0                         */

    struct {
      __IM  uint32_t DCWNUML1   : 8;            /* [7..0] Number of Level 1 Data Cache Way                                   */
      __IM  uint32_t DCSIZEL1   : 8;            /* [15..8] Level 1 Data Cache Size                                           */
      __IM  uint32_t ICWNUML1   : 8;            /* [23..16] Number of Level 1 Instruction Cache Way                          */
      __IM  uint32_t ICSIZEL1   : 8;            /* [31..24] Level 1 Instruction Cache Size                                   */
    } bit;
  } PC0INF0;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000034) Processor 0 Information Register 1                         */

    struct {
      __IM  uint32_t RESERVED0  : 16;
      __IM  uint32_t ICWNUML2   : 8;            /* [23..16] Number of Level 2 Instruction Cache Way                          */
      __IM  uint32_t ICSIZEL2   : 8;            /* [31..24] Level 2 Instruction Cache Size                                   */
    } bit;
  } PC0INF1;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000038) Processor 0 Information Register 2                         */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IM  uint32_t TCMHSIZE   : 8;            /* [15..8] Tightly-Coupled Memory Higher Size                                */
      __IM  uint32_t RESERVED1  : 8;
      __IM  uint32_t TCMLSIZE   : 8;            /* [31..24] Tightly-Coupled Memory Lower Size                                */
    } bit;
  } PC0INF2;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000003C) Processor 0 Information Register 3                         */

    struct {
      __IM  uint32_t FPUFLG     : 1;            /* [0..0] Support Floating Point Unit Flag                                   */
      __IM  uint32_t ISEFLG     : 1;            /* [1..1] Support Instruction Set Extension                                  */
      __IM  uint32_t JHWFLG     : 1;            /* [2..2] Support Jazelle Hardware Flag                                      */
      __IM  uint32_t MMFLG      : 1;            /* [3..3] Support Memory Management Unit Flag                                */
      __IM  uint32_t TZFFLG     : 1;            /* [4..4] Support Trust Zone Function Flag                                   */
      __IM  uint32_t CMPHWFLG   : 1;            /* [5..5] Support Core Memory Protection Hardware Flag                       */
      __IM  uint32_t BBFLG      : 1;            /* [6..6] Support Bit Banding Flag                                           */
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t SYSBPNUM   : 2;            /* [9..8] Number of System Bus Ports                                         */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } PC0INF3;
  __IM  uint32_t  RESERVED[240];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000400) On-Chip Memory Descriptor Register 0                       */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t OCMCTRLF1  : 2;            /* [5..4] On-Chip Memory Control Field 1                                     */
      __IM  uint32_t RESERVED1  : 6;
      __IM  uint32_t OCMMPU     : 1;            /* [12..12] On-Chip Memory Memory Protect Unit                               */
      __IM  uint32_t OCMTYPE    : 3;            /* [15..13] On-Chip Memory Type                                              */
      __IOM uint32_t RONLY      : 1;            /* [16..16] Read-Only                                                        */
      __IM  uint32_t OCMDPWID   : 3;            /* [19..17] On-Chip Memory Datapath Width                                    */
      __IM  uint32_t RESERVED2  : 4;
      __IM  uint32_t OCMSIZE    : 4;            /* [27..24] On-Chip Memory Size                                              */
      __IM  uint32_t IFOCM      : 1;            /* [28..28] Incompletely Filled On-Chip Memory                               */
      __IM  uint32_t RESERVED3  : 2;
      __IM  uint32_t OCMVLDFLG  : 1;            /* [31..31] On-Chip Memory Valid Flag                                        */
    } bit;
  } OCMD0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000404) On-Chip Memory Descriptor Register 1                       */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t OCMCTRLF1  : 2;            /* [5..4] On-Chip Memory Control Field 1                                     */
      __IM  uint32_t RESERVED1  : 6;
      __IM  uint32_t OCMMPU     : 1;            /* [12..12] On-Chip Memory Memory Protect Unit                               */
      __IM  uint32_t OCMTYPE    : 3;            /* [15..13] On-Chip Memory Type                                              */
      __IOM uint32_t RONLY      : 1;            /* [16..16] Read-Only                                                        */
      __IM  uint32_t OCMDPWID   : 3;            /* [19..17] On-Chip Memory Datapath Width                                    */
      __IM  uint32_t RESERVED2  : 4;
      __IM  uint32_t OCMSIZE    : 4;            /* [27..24] On-Chip Memory Size                                              */
      __IM  uint32_t IFOCM      : 1;            /* [28..28] Incompletely Filled On-Chip Memory                               */
      __IM  uint32_t RESERVED3  : 2;
      __IM  uint32_t OCMVLDFLG  : 1;            /* [31..31] On-Chip Memory Valid Flag                                        */
    } bit;
  } OCMD1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000408) On-Chip Memory Descriptor Register2                        */

    struct {
      __IM  uint32_t RESERVED0  : 12;
      __IM  uint32_t OCMMPU     : 1;            /* [12..12] On-Chip Memory Memory Protect Unit                               */
      __IM  uint32_t OCMTYPE    : 3;            /* [15..13] On-Chip Memory Type                                              */
      __IOM uint32_t RONLY      : 1;            /* [16..16] Read-Only                                                        */
      __IM  uint32_t OCMDPWID   : 3;            /* [19..17] On-Chip Memory Datapath Width                                    */
      __IM  uint32_t RESERVED1  : 4;
      __IM  uint32_t OCMSIZE    : 4;            /* [27..24] On-Chip Memory Size                                              */
      __IM  uint32_t IFOCM      : 1;            /* [28..28] Incompletely Filled On-Chip Memory                               */
      __IM  uint32_t RESERVED2  : 2;
      __IM  uint32_t OCMVLDFLG  : 1;            /* [31..31] On-Chip Memory Valid Flag                                        */
    } bit;
  } OCMD2;
} MSC_T;                                     /* Size = 1036 (0x40c)                                                         */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Direct Memory Access (DMA)
  */

typedef struct {                                /* (@ 0x40008000) DMA Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control Register                                           */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t DBGEN      : 1;            /* [1..1] Debug Enable                                                       */
      __IOM uint32_t CHASEL     : 1;            /* [2..2] Channel Arbitration Mode Select                                    */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t HALTEFLG   : 1;            /* [4..4] HALT Error Flag                                                    */
      __IOM uint32_t HALT       : 1;            /* [5..5] DMA Operations Halt                                                */
      __IOM uint32_t CLMEN      : 1;            /* [6..6] Continuous Link Mode Enable                                        */
      __IOM uint32_t MINLMEN    : 1;            /* [7..7] Minor Loop Mapping Enable                                          */
      __IM  uint32_t RESERVED2  : 8;
      __IOM uint32_t TXCNLERR   : 1;            /* [16..16] Data Transfer Cancel Error                                       */
      __IOM uint32_t TXCNL      : 1;            /* [17..17] Data Transfer Cancel                                             */
      __IM  uint32_t RESERVED3  : 13;
      __IM  uint32_t ACTFLG     : 1;            /* [31..31] DMA Active Flag                                                  */
    } bit;
  } CTRL;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Error Status Register                                      */

    struct {
      __IM  uint32_t DBEFLG     : 1;            /* [0..0] Destination Bus Error Flag                                         */
      __IM  uint32_t SBEFLG     : 1;            /* [1..1] Source Bus Error Flag                                              */
      __IM  uint32_t SGCFGEFLG  : 1;            /* [2..2] Scatter/Gather Configure Error Flag                                */
      __IM  uint32_t MCCFGEFLG  : 1;            /* [3..3] MINBTCNT/CMAJICNT Configure Error Flag                             */
      __IM  uint32_t DOFCFGEFLG : 1;            /* [4..4] Destination Offset Configure Error Flag                            */
      __IM  uint32_t DADDRCFGEFLG : 1;          /* [5..5] Destination Address Configure Error Flag                           */
      __IM  uint32_t SOFCFGEFLG : 1;            /* [6..6] Source Offset Configure Error Flag                                 */
      __IM  uint32_t SADDRCFGEFLG : 1;          /* [7..7] Source Address Configure Error Flag                                */
      __IM  uint32_t ERRCHNUM   : 4;            /* [11..8] Error Channel Number                                              */
      __IM  uint32_t RESERVED0  : 2;
      __IM  uint32_t CPCFGEFLG  : 1;            /* [14..14] Channel Priority Configure Error Flag                            */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t TCFLG      : 1;            /* [16..16] Transfer Canceled Flag                                           */
      __IM  uint32_t RESERVED2  : 14;
      __IM  uint32_t EEFLG      : 1;            /* [31..31] Error Exist Flag                                                 */
    } bit;
  } ESTS;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Request Enable Register                                    */

    struct {
      __IOM uint32_t REQEN0     : 1;            /* [0..0] Channel 0 DMA Request Enable                                       */
      __IOM uint32_t REQEN1     : 1;            /* [1..1] Channel 1 DMA Request Enable                                       */
      __IOM uint32_t REQEN2     : 1;            /* [2..2] Channel 2 DMA Request Enable                                       */
      __IOM uint32_t REQEN3     : 1;            /* [3..3] Channel 3 DMA Request Enable                                       */
      __IOM uint32_t REQEN4     : 1;            /* [4..4] Channel 4 DMA Request Enable                                       */
      __IOM uint32_t REQEN5     : 1;            /* [5..5] Channel 5 DMA Request Enable                                       */
      __IOM uint32_t REQEN6     : 1;            /* [6..6] Channel 6 DMA Request Enable                                       */
      __IOM uint32_t REQEN7     : 1;            /* [7..7] Channel 7 DMA Request Enable                                       */
      __IOM uint32_t REQEN8     : 1;            /* [8..8] Channel 8 DMA Request Enable                                       */
      __IOM uint32_t REQEN9     : 1;            /* [9..9] Channel 9 DMA Request Enable                                       */
      __IOM uint32_t REQEN10    : 1;            /* [10..10] Channel 10 DMA Request Enable                                    */
      __IOM uint32_t REQEN11    : 1;            /* [11..11] Channel 11 DMA Request Enable                                    */
      __IOM uint32_t REQEN12    : 1;            /* [12..12] Channel 12 DMA Request Enable                                    */
      __IOM uint32_t REQEN13    : 1;            /* [13..13] Channel 13 DMA Request Enable                                    */
      __IOM uint32_t REQEN14    : 1;            /* [14..14] Channel 14 DMA Request Enable                                    */
      __IOM uint32_t REQEN15    : 1;            /* [15..15] Channel 15 DMA Request Enable                                    */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } REQEN;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Error Interrupt Enable Register                            */

    struct {
      __IOM uint32_t EIEN0      : 1;            /* [0..0] Error Interrupt Channel 0 Enable                                   */
      __IOM uint32_t EIEN1      : 1;            /* [1..1] Error Interrupt Channel 1 Enable                                   */
      __IOM uint32_t EIEN2      : 1;            /* [2..2] Channel 2 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN3      : 1;            /* [3..3] Channel 3 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN4      : 1;            /* [4..4] Channel 4 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN5      : 1;            /* [5..5] Channel 5 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN6      : 1;            /* [6..6] Channel 6 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN7      : 1;            /* [7..7] Channel 7 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN8      : 1;            /* [8..8] Channel 8 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN9      : 1;            /* [9..9] Channel 9 Error Interrupt Enable                                   */
      __IOM uint32_t EIEN10     : 1;            /* [10..10] Channel 10 Error Interrupt Enable                                */
      __IOM uint32_t EIEN11     : 1;            /* [11..11] Channel 11 Error Interrupt Enable                                */
      __IOM uint32_t EIEN12     : 1;            /* [12..12] Channel 12 Error Interrupt Enable                                */
      __IOM uint32_t EIEN13     : 1;            /* [13..13] Channel 13 Error Interrupt Enable                                */
      __IOM uint32_t EIEN14     : 1;            /* [14..14] Channel 14 Error Interrupt Enable                                */
      __IOM uint32_t EIEN15     : 1;            /* [15..15] Channel 15 Error Interrupt Enable                                */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } EIEN;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000018) Error Interrupt Enable Clear Register                      */

    struct {
      __OM  uint8_t EIENCLR     : 4;            /* [3..0] Channel Error Interrupt Enable Bit Clear                           */
            uint8_t             : 2;
      __OM  uint8_t AEIENCLR    : 1;            /* [6..6] All Channel Error Interrupt Bits Clear                             */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } EIENCLR;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000019) Error Interrupt Enable Set Register                        */

    struct {
      __OM  uint8_t EIENSET     : 4;            /* [3..0] Channel Error Interrupt Enable Bit Set                             */
            uint8_t             : 2;
      __OM  uint8_t AEIENSET    : 1;            /* [6..6] All Channel Error Interrupt Bits Set                               */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } EIENSET;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001A) Request Enable Clear Register                              */

    struct {
      __OM  uint8_t REQENCLR    : 4;            /* [3..0] DMA Request Enable Clear                                           */
            uint8_t             : 2;
      __OM  uint8_t AREQENCLR   : 1;            /* [6..6] All DMA Requests Enable Clear                                      */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } REQENCLR;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001B) Request Enable Set Register                                */

    struct {
      __OM  uint8_t REQENSET    : 4;            /* [3..0] DMA Request Enable Setup                                           */
            uint8_t             : 2;
      __OM  uint8_t AREQENSET   : 1;            /* [6..6] ALL DMA Requests Enable Set                                        */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } REQENSET;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001C) DONE Status Clear Register                                 */

    struct {
      __OM  uint8_t DNECLR      : 4;            /* [3..0] DONE Field Clear                                                   */
            uint8_t             : 2;
      __OM  uint8_t ADNECLR     : 1;            /* [6..6] All DONE Field Clear                                               */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } DNESTSCLR;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001D) START Set Register                                         */

    struct {
      __OM  uint8_t STATSET     : 4;            /* [3..0] START Field Set                                                    */
            uint8_t             : 2;
      __OM  uint8_t ASTATSET    : 1;            /* [6..6] All START Field Setup                                              */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } STATSET;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001E) Error Status Clear Register                                */

    struct {
      __OM  uint8_t EFLGCLR     : 4;            /* [3..0] Error Flag Clear                                                   */
            uint8_t             : 2;
      __OM  uint8_t AEFLGCLR    : 1;            /* [6..6] All Error Flag Clear                                               */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } ESTSCLR;

  union {
    __OM  uint8_t reg;                          /* (@ 0x0000001F) Interrupt Request Clear Register                           */

    struct {
      __OM  uint8_t INTREQCLR   : 4;            /* [3..0] Interrupt Request Clear                                            */
            uint8_t             : 2;
      __OM  uint8_t AINTREQCLR  : 1;            /* [6..6] All Interrupt Request Clear                                        */
      __OM  uint8_t NOOP        : 1;            /* [7..7] No Operation                                                       */
    } bit;
  } INTREQCLR;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) Interrupt Request Register                                 */

    struct {
      __IOM uint32_t INTREQSTS0 : 1;            /* [0..0] Interrupt Request 0 Status                                         */
      __IOM uint32_t INTREQSTS1 : 1;            /* [1..1] Interrupt Request 1 Status                                         */
      __IOM uint32_t INTREQSTS2 : 1;            /* [2..2] Interrupt Request 2 Status                                         */
      __IOM uint32_t INTREQSTS3 : 1;            /* [3..3] Interrupt Request 3 Status                                         */
      __IOM uint32_t INTREQSTS4 : 1;            /* [4..4] Interrupt Request 4 Status                                         */
      __IOM uint32_t INTREQSTS5 : 1;            /* [5..5] Interrupt Request 5 Status                                         */
      __IOM uint32_t INTREQSTS6 : 1;            /* [6..6] Interrupt Request 6 Status                                         */
      __IOM uint32_t INTREQSTS7 : 1;            /* [7..7] Interrupt Request 7 Status                                         */
      __IOM uint32_t INTREQSTS8 : 1;            /* [8..8] Interrupt Request 8 Status                                         */
      __IOM uint32_t INTREQSTS9 : 1;            /* [9..9] Interrupt Request 9 Status                                         */
      __IOM uint32_t INTREQSTS10 : 1;           /* [10..10] Interrupt Request 10 Status                                      */
      __IOM uint32_t INTREQSTS11 : 1;           /* [11..11] Interrupt Request 11 Status                                      */
      __IOM uint32_t INTREQSTS12 : 1;           /* [12..12] Interrupt Request 12 Status                                      */
      __IOM uint32_t INTREQSTS13 : 1;           /* [13..13] Interrupt Request 13 Status                                      */
      __IOM uint32_t INTREQSTS14 : 1;           /* [14..14] Interrupt Request 14 Status                                      */
      __IOM uint32_t INTREQSTS15 : 1;           /* [15..15] Interrupt Request 15 Status                                      */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } INTREQ;
  __IM  uint32_t  RESERVED3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000002C) Channel Error Status Register                              */

    struct {
      __IOM uint32_t EFLG0      : 1;            /* [0..0] Error In Channel 0 Flag                                            */
      __IOM uint32_t EFLG1      : 1;            /* [1..1] Error In Channel 1 Flag                                            */
      __IOM uint32_t EFLG2      : 1;            /* [2..2] Error In Channel 2 Flag                                            */
      __IOM uint32_t EFLG3      : 1;            /* [3..3] Error In Channel 3 Flag                                            */
      __IOM uint32_t EFLG4      : 1;            /* [4..4] Error In Channel 4 Flag                                            */
      __IOM uint32_t EFLG5      : 1;            /* [5..5] Error In Channel 5 Flag                                            */
      __IOM uint32_t EFLG6      : 1;            /* [6..6] Error In Channel 6 Flag                                            */
      __IOM uint32_t EFLG7      : 1;            /* [7..7] Error In Channel 7 Flag                                            */
      __IOM uint32_t EFLG8      : 1;            /* [8..8] Error In Channel 8 Flag                                            */
      __IOM uint32_t EFLG9      : 1;            /* [9..9] Error In Channel 9 Flag                                            */
      __IOM uint32_t EFLG10     : 1;            /* [10..10] Error In Channel 10 Flag                                         */
      __IOM uint32_t EFLG11     : 1;            /* [11..11] Error In Channel 11 Flag                                         */
      __IOM uint32_t EFLG12     : 1;            /* [12..12] Error In Channel 12 Flag                                         */
      __IOM uint32_t EFLG13     : 1;            /* [13..13] Error In Channel 13 Flag                                         */
      __IOM uint32_t EFLG14     : 1;            /* [14..14] Error In Channel 14 Flag                                         */
      __IOM uint32_t EFLG15     : 1;            /* [15..15] Error In Channel 15 Flag                                         */
      __IM  uint32_t RESERVED1  : 16;
    } bit;
  } CHESTS;
  __IM  uint32_t  RESERVED4;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000034) Hardware Request Status Register                           */

    struct {
      __IM  uint32_t HREQSTS0   : 1;            /* [0..0] Hardware Request Channel 0 Status                                  */
      __IM  uint32_t HREQSTS1   : 1;            /* [1..1] Hardware Request Channel 1 Status                                  */
      __IM  uint32_t HREQSTS2   : 1;            /* [2..2] Hardware Request Channel 2 Status                                  */
      __IM  uint32_t HREQSTS3   : 1;            /* [3..3] Hardware Request Channel 3 Status                                  */
      __IM  uint32_t HREQSTS4   : 1;            /* [4..4] Hardware Request Channel 4 Status                                  */
      __IM  uint32_t HREQSTS5   : 1;            /* [5..5] Hardware Request Channel 5 Status                                  */
      __IM  uint32_t HREQSTS6   : 1;            /* [6..6] Hardware Request Channel 6 Status                                  */
      __IM  uint32_t HREQSTS7   : 1;            /* [7..7] Hardware Request Channel 7 Status                                  */
      __IM  uint32_t HREQSTS8   : 1;            /* [8..8] Hardware Request Channel 8 Status                                  */
      __IM  uint32_t HREQSTS9   : 1;            /* [9..9] Hardware Request Channel 9 Status                                  */
      __IM  uint32_t HREQSTS10  : 1;            /* [10..10] Hardware Request Channel 10 Status                               */
      __IM  uint32_t HREQSTS11  : 1;            /* [11..11] Hardware Request Channel 11 Status                               */
      __IM  uint32_t HREQSTS12  : 1;            /* [12..12] Hardware Request Channel 12 Status                               */
      __IM  uint32_t HREQSTS13  : 1;            /* [13..13] Hardware Request Channel 13 Status                               */
      __IM  uint32_t HREQSTS14  : 1;            /* [14..14] Hardware Request Channel 14 Status                               */
      __IM  uint32_t HREQSTS15  : 1;            /* [15..15] Hardware Request Channel 15 Status                               */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } HWREQSTS;
  __IM  uint32_t  RESERVED5[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000044) Asynchronous Request in Stop Enable Register               */

    struct {
      __IOM uint32_t AREQSEN0   : 1;            /* [0..0] Asynchronous DMA Request Channel 0 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN1   : 1;            /* [1..1] Asynchronous DMA Request Channel 1 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN2   : 1;            /* [2..2] Asynchronous DMA Request Channel 2 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN3   : 1;            /* [3..3] Asynchronous DMA Request Channel 3 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN4   : 1;            /* [4..4] Asynchronous DMA Request Channel 4 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN5   : 1;            /* [5..5] Asynchronous DMA Request Channel 5 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN6   : 1;            /* [6..6] Asynchronous DMA Request Channel 6 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN7   : 1;            /* [7..7] Asynchronous DMA Request Channel 7 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN8   : 1;            /* [8..8] Asynchronous DMA Request Channel 8 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN9   : 1;            /* [9..9] Asynchronous DMA Request Channel 9 in Stop Mode Enable             */
      __IOM uint32_t AREQSEN10  : 1;            /* [10..10] Asynchronous DMA Request Channel 10 in Stop Mode Enable          */
      __IOM uint32_t AREQSEN11  : 1;            /* [11..11] Asynchronous DMA Request Channel 11 in Stop Mode Enable          */
      __IOM uint32_t AREQSEN12  : 1;            /* [12..12] Asynchronous DMA Request Channel 12 in Stop Mode Enable          */
      __IOM uint32_t AREQSEN13  : 1;            /* [13..13] Asynchronous DMA Request Channel 13 in Stop Mode Enable          */
      __IOM uint32_t AREQSEN14  : 1;            /* [14..14] Asynchronous DMA Request Channel 14 in Stop Mode Enable          */
      __IOM uint32_t AREQSEN15 : 1;            /* [15..15] Asynchronous DMA Request Channel 15 in Stop Mode Enable          */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } AREQSEN;
  __IM  uint32_t  RESERVED6[46];

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000100) Channel 3 Priority Register                                */

    struct {
      __IOM uint8_t CHPRIA      : 4;            /* [3..0] Channel n Priority Arbitration                                     */
            uint8_t             : 2;
      __IOM uint8_t PLPRICHD    : 1;            /* [6..6] Preemption of Other Lower Priority Channel Disable                 */
      __IOM uint8_t BPHPRICHEN  : 1;            /* [7..7] being Preempted by Other Higher Channel Enable                     */
    } bit;
  } CHPRI[16];
  __IM  uint32_t  RESERVED7[956];

  struct {
    union {
      __IOM uint32_t reg;                         /* (@ 0x00001000) TCD Source Address                                       */

      struct {
        __IOM uint32_t SADDR      : 32;           /* [31..0] Source Data Address                                             */
      } bit;
    } SADDR;

    union {
      __IOM uint16_t reg;                         /* (@ 0x00001004) TCD Signed Source Address Offset                          */

      struct {
        __IOM uint16_t SADDROF    : 16;           /* [15..0] Source Address Signed Offset                                     */
      } bit;
    } SADDROF;

    union {
      __IOM uint16_t reg;                         /* (@ 0x00001006) TCD Transfer Attributes                                   */

      struct {
        __IOM uint16_t DTSIZE     : 3;            /* [2..0] Destination Data Transfer Size                                     */
        __IOM uint16_t DADDRMV    : 5;            /* [7..3] Destination Address Modulo Value                                   */
        __IOM uint16_t STSIZE     : 3;            /* [10..8] Source Data Transfer Size                                         */
        __IOM uint16_t SADDRMV    : 5;            /* [15..11] Source Address Modulo Value                                      */
      } bit;
    } TATT;

    union {
      union {
        __IOM uint32_t reg;                       /* (@ 0x00001008) TCD Minor Byte Transfer Count (Minor Loop Mapping
                                                                      Disabled) Register                                       */

        struct {
          __IOM uint32_t MINBTCNT : 32;           /* [31..0] Minor Byte Number Transfer Count                                  */
        } bit;
      } MINBCNT_MINLMD;

      union {
        __IOM uint32_t reg;                       /* (@ 0x00001008) TCD Signed Minor Loop Offset (Minor Loop Mapping
                                                                      Enabled and Offset Disabled) Register                    */

        struct {
          __IOM uint32_t MINBTCNT : 30;           /* [29..0] Minor Byte Number Transfer Count                                  */
          __IOM uint32_t DMINLOFEN : 1;           /* [30..30] Destination Address Minor Loop Offset Enable                     */
          __IOM uint32_t SMINLOFEN : 1;           /* [31..31] Source Address Minor Loop Offset Enable                          */
        } bit;
      } SMLOF_MINLMENOFD;

      union {
        __IOM uint32_t reg;                       /* (@ 0x00001008) TCD Signed Minor Loop Offset (Minor Loop Mapping
                                                                      and Offset Enabled) Register                             */

        struct {
          __IOM uint32_t MINBTCNT : 10;           /* [9..0] Minor Byte Number Transfer Count                                   */
          __IOM uint32_t MINSELOF : 20;           /* [29..10] Minor Loop Sign-extended Offset                                  */
          __IOM uint32_t DMINLOFEN : 1;           /* [30..30] Destination Address Minor Loop Offset Enable                     */
          __IOM uint32_t SMINLOFEN : 1;           /* [31..31] Source Address Minor Loop Offset Enable                          */
        } bit;
      } SMINLOF_MINLMOFEN;
    } MINBTCNT;

    union {
      __IOM uint32_t reg;                         /* (@ 0x0000100C) TCD Last Source Address Adjustment                        */

      struct {
        __IOM uint32_t SADDRAV    : 32;           /* [31..0] Source Address Adjustment Value                                   */
      } bit;
    } SADDRAV;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00001010) TCD Destination Address                                   */

      struct {
        __IOM uint32_t DADDR      : 32;           /* [31..0] Destination Address                                              */
      } bit;
    } DADDR;

    union {
      __IOM uint16_t reg;                         /* (@ 0x00001014) TCD Signed Destination Address Offset                     */

      struct {
        __IOM uint16_t DADDRSOF   : 16;           /* [15..0] Destination Address Signed Offset                                */
      } bit;
    } DADDRSOF;

    union {
      union {
        __IOM uint16_t reg;                       /* (@ 0x00001016) TCD Current Major Iteration Count (Channel Linking
                                                                      Disabled) Register                                       */

        struct {
          __IOM uint16_t CMAJICNT : 15;           /* [14..0] Current Major Iteration Count                                     */
          __IOM uint16_t LINKEN   : 1;            /* [15..15] Channel-to-channel Linking Enable                                */
        } bit;
      } LINKD;

      union {
        __IOM uint16_t reg;                       /* (@ 0x00001016) TCD Current Major Iteration Count (Channel Linking
                                                                      Enabled) Register                                        */

        struct {
          __IOM uint16_t CMAJICNT  : 9;            /* [8..0] Current Major Iteration Count                                      */
          __IOM uint16_t MINLINKCH : 4;            /* [12..9] Minor Loop Link Channel Number                                    */
                uint16_t           : 2;
          __IOM uint16_t LINKEN    : 1;            /* [15..15] Channel-to-channel Linking Enable                                */
        } bit;
      } LINKEN;
    } CMAJICNT;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00001018) TCD Destination Address Adjustment Value or
                                                                      SG next TCD Address Register                             */

      struct {
        __IOM uint32_t DADDRAVSGA : 32;           /* [31..0] Destination Address Adjustment Value or SG next TCD
                                                       Address                                                                 */
      } bit;
    } DADDRAVSGA;

    union {
      __IOM uint16_t reg;                         /* (@ 0x0000101C) TCD Control and Status Register                            */

      struct {
        __IOM uint16_t START      : 1;            /* [0..0] Channel Start                                                      */
        __IOM uint16_t MAJICMPIEN : 1;            /* [1..1] Major Iteration Count Complete Interrupt Enable                    */
        __IOM uint16_t MAJIHCMPIEN : 1;           /* [2..2] Major Iteration Counter Half Complete Interrupt Enable             */
        __IOM uint16_t DMAREQD    : 1;            /* [3..3] DMA Request Disable                                                */
        __IOM uint16_t SGFEN      : 1;            /* [4..4] Scatter Gather Format Enable                                       */
        __IOM uint16_t MAJILINKEN : 1;            /* [5..5] Major Iteration Channel-to-channel Linking Enable                  */
        __IOM uint16_t ACTFLG     : 1;            /* [6..6] Channel Active Flag Flag Flag                                      */
        __IOM uint16_t MAJLCMPFLG : 1;            /* [7..7] Major Loop Complete Flag                                           */
        __IOM uint16_t MAJLINKCH  : 4;            /* [11..8] Major Loop Link Channel Number                                    */
              uint16_t            : 2;
        __IOM uint16_t BWCTRL     : 2;            /* [15..14] DMA Bandwidth Control                                            */
      } bit;
    } CSTS;

    union {
      union {
        __IOM uint16_t reg;                       /* (@ 0x0000101E) TCD Major Iteration Count Start(Channel Linking
                                                                      Disabled) Register                                       */

        struct {
          __IOM uint16_t MAJICSTAT : 15;          /* [14..0] Major Iteration Count Start                                       */
          __IOM uint16_t LINKEN    : 1;           /* [15..15] Channel-to-channel Linking Enable                                */
        } bit;
      } LINKD;

      union {
        __IOM uint16_t reg;                       /* (@ 0x0000101E) TCD Major Iteration Count Start (Channel Linking
                                                                      Enabled) Register                                        */

        struct {
          __IOM uint16_t MAJICSTAT : 9;           /* [8..0] Major Iteration Count Start                                        */
          __IOM uint16_t MINLINKCH : 4;           /* [12..9] Minor Loop Link Channel Number                                    */
                uint16_t           : 2;
          __IOM uint16_t LINKEN    : 1;           /* [15..15] Channel-to-channel Linking Enable                                */
        } bit;
      } LINKEN;
    } MAJICNTSTAT;
  } TCD[16u];
} DMA_T;                                     /* Size = 4608 (0x1200)                                                           */



/* =========================================================================================================================== */
/* ================                                            MPU                                            ================ */
/* =========================================================================================================================== */

/** MPU - Size of Registers Arrays */
#define MPU_EADDR_EDETAIL_COUNT                   4U
#define MPU_REGD_COUNT                            8U
#define MPU_RDAACC_COUNT                          8U

/**
  * @brief Memory protection (MPU)
  */

typedef struct {                                /* (@ 0x4000D000) MPU Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control/Error Status Register                              */

    struct {
      __IOM uint32_t MPUEN      : 1;            /* [0..0] MPU Global Enable                                                  */
      __IM  uint32_t RESERVED0  : 7;
      __IM  uint32_t RDINUM     : 4;            /* [11..8] Region Descriptors Number                                         */
      __IM  uint32_t SPCNUM     : 4;            /* [15..12] Slave Ports Connected Number                                     */
      __IM  uint32_t HWDRL      : 4;            /* [19..16] Hardware and Definition Revision Level                           */
      __IM  uint32_t RESERVED1  : 8;
      __IOM uint32_t SPEFLG3    : 1;            /* [28..28] Slave Port 3 Error Occurred Flag                                 */
      __IOM uint32_t SPEFLG2    : 1;            /* [29..29] Slave Port 2 Error Occurred Flag                                 */
      __IOM uint32_t SPEFLG1    : 1;            /* [30..30] Slave Port 2 Error Occurred Flag                                 */
      __IOM uint32_t SPEFLG0    : 1;            /* [31..31] Slave Port 2 Error Occurred Flag                                 */
    } bit;
  } CESTS;
  __IM  uint32_t  RESERVED[3];

  struct {
    union {
      __IM  uint32_t reg;                         /* (@ 0x00000010) Error Address Register, slave port 0                     */

      struct {
        __IM  uint32_t SACCEADDR  : 32;           /* [31..0] Error Address                                                   */
      } bit;
    } EADDR;

    union {
      __IM  uint32_t reg;                         /* (@ 0x00000014) Error Detail Register, slave port 0                      */

      struct {
        __IM  uint32_t RWE        : 1;            /* [0..0] Read/Write Error                                                   */
        __IM  uint32_t AINFOE     : 3;            /* [3..1] Attribute Information of Error                                     */
        __IM  uint32_t MNUME      : 4;            /* [7..4] Master Number of Error                                             */
        __IM  uint32_t PIDE       : 8;            /* [15..8] Process Identification of Error                                   */
        __IM  uint32_t RDACCE     : 16;           /* [31..16] Region Descriptor with the Access Error                          */
      } bit;
    } EDETAIL;
  } EADDR_EDETAIL[MPU_EADDR_EDETAIL_COUNT];
  __IM  uint32_t  RESERVED1[244];

  struct {
    union {
      __IOM uint32_t reg;                         /* (@ 0x00000400) Region Descriptor n, Word Register 0                                */

      struct {
        __IM  uint32_t RESERVED0  : 5;
        __IOM uint32_t SADDR      : 27;           /* [31..5] Start Address of the Memory Region                                */
      } bit;
    } WORD0;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00000404) Region Descriptor n, Word Register 1                                */

      struct {
        __IM  uint32_t RESERVED0  : 5;
        __IOM uint32_t ENDADDR    : 27;           /* [31..5] End Address of the Memory Region                                  */
      } bit;
    } WORD1;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00000408) Region Descriptor n, Word Register 2                                */

      struct {
        __IOM uint32_t UMCTRLM0   : 3;            /* [2..0] Bus Master 0 User Mode Access Control                              */
        __IOM uint32_t SMCTRLM0   : 2;            /* [4..3] Bus Master 0 Supervisor Mode Access Control                        */
        __IOM uint32_t PIDENM0    : 1;            /* [5..5] Bus Master 0 Process Identifier enable                             */
        __IOM uint32_t UMCTRLM1   : 3;            /* [8..6] Bus Master 1 User Mode Access Control                              */
        __IOM uint32_t SMCTRLM1   : 2;            /* [10..9] Bus Master 1 Supervisor Mode Access Control                       */
        __IOM uint32_t PIDENM1    : 1;            /* [11..11] Bus Master 1 Process Identifier enable                           */
        __IOM uint32_t UMCTRLM2   : 3;            /* [14..12] Bus Master 2 User Mode Access control                            */
        __IOM uint32_t SMCTRLM2   : 2;            /* [16..15] Bus Master 2 Supervisor Mode Access Control                      */
        __IM  uint32_t RESERVED0  : 1;
        __IOM uint32_t UMCTRLM3   : 3;            /* [20..18] Bus Master 3 User Mode Access Control                            */
        __IOM uint32_t SMCTRLM3   : 2;            /* [22..21] Bus Master 3 Supervisor Mode Access Control                      */
        __IM  uint32_t RESERVED1  : 1;
        __IOM uint32_t WENM4      : 1;            /* [24..24] Bus Master 4 Write Enable                                        */
        __IOM uint32_t RENM4      : 1;            /* [25..25] Bus Master 4 Read Enable                                         */
        __IOM uint32_t WENM5      : 1;            /* [26..26] Bus Master 5 Write Enable                                        */
        __IOM uint32_t RENM5      : 1;            /* [27..27] Bus Master 5 Read Enable                                         */
        __IOM uint32_t WENM6      : 1;            /* [28..28] Bus Master 6 Write Enable                                        */
        __IOM uint32_t RENM6      : 1;            /* [29..29] Bus Master 6 Read Enable                                         */
        __IOM uint32_t WENM7      : 1;            /* [30..30] Bus Master 7 Write Enable                                        */
        __IOM uint32_t RENM7      : 1;            /* [31..31] Bus Master 7 Read Enable                                         */
      } bit;
    } WORD2;

    union {
      __IOM uint32_t reg;                         /* (@ 0x0000040C) Region Descriptor n, Word Register 3                                */

      struct {
        __IOM uint32_t RDVALID    : 1;            /* [0..0] Region Descriptor Valid                                            */
        __IM  uint32_t RESERVED0  : 15;
        __IOM uint32_t PIDMASK    : 8;            /* [23..16] Process Identifier Mask                                          */
        __IOM uint32_t PID        : 8;            /* [31..24] Process Identifier                                               */
      } bit;
    } WORD3;
  } REGD[MPU_REGD_COUNT];
  __IM  uint32_t  RESERVED2[224];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000800) Region Descriptor Alternate Access Control 0               */

    struct {
      __IOM uint32_t UMCTRLM0   : 3;            /* [2..0] Bus Master 0 User Mode Access Control                              */
      __IOM uint32_t SMCTRLM0   : 2;            /* [4..3] Bus Master 0 Supervisor Mode Access Control                        */
      __IOM uint32_t PIDENM0    : 1;            /* [5..5] Bus Master 0 Process Identifier Enable                             */
      __IOM uint32_t UMCTRLM1   : 3;            /* [8..6] Bus Master 1 User Mode Access Control                              */
      __IOM uint32_t SMCTRLM1   : 2;            /* [10..9] Bus Master 1 Supervisor Mode Access Control                       */
      __IOM uint32_t PIDENM1    : 1;            /* [11..11] Bus Master 1 Process Identifier Enable                           */
      __IOM uint32_t UMCTRLM2   : 3;            /* [14..12] Bus Master 2 User Mode Access Control                            */
      __IOM uint32_t SMCTRLM2   : 2;            /* [16..15] Bus Master 2 Supervisor Mode Access Control                      */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t UMCTRLM3   : 3;            /* [20..18] Bus Master 3 User Mode Access Control                            */
      __IOM uint32_t SMCTRLM3   : 2;            /* [22..21] Bus Master 3 Supervisor Mode Access Control                      */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t WENM4      : 1;            /* [24..24] Bus Master 4 Write Enable                                        */
      __IOM uint32_t RENM4      : 1;            /* [25..25] Bus Master 4 Read Enable                                         */
      __IOM uint32_t WENM5      : 1;            /* [26..26] Bus Master 5 Write Enable                                        */
      __IOM uint32_t RENM5      : 1;            /* [27..27] Bus Master 5 Read Enable                                         */
      __IOM uint32_t WENM6      : 1;            /* [28..28] Bus Master 6 Write Enable                                        */
      __IOM uint32_t RENM6      : 1;            /* [29..29] Bus Master 6 Read Enable                                         */
      __IOM uint32_t WENM7      : 1;            /* [30..30] Bus Master 7 Write Enable                                        */
      __IOM uint32_t RENM7      : 1;            /* [31..31] Bus Master 7 Read Enable                                         */
    } bit;
  } RDAACC[MPU_RDAACC_COUNT];
} MPU_T;                                     /* Size = 2080 (0x820)                                                       */



/* =========================================================================================================================== */
/* ================                                           EREP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Error Reporting (EREP)
  */

typedef struct {                                /* (@ 0x40018000) EREP Structure                                             */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Configure Register 0                                       */

    struct {
      __IM  uint32_t RESERVED0  : 26;
      __IOM uint32_t UINTNENM1  : 1;            /* [26..26] Memory 1 Uncorrectable Interrupt Notification Enable             */
      __IOM uint32_t SCINTNENM1 : 1;            /* [27..27] Memory 1 Single-Bit Correction Interrupt Notification
                                                     Enable                                                                  */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t UINTNENM0  : 1;            /* [30..30] Memory 0 Uncorrectable Interrupt Notification Enable             */
      __IOM uint32_t SCINTNENM0 : 1;            /* [31..31] Memory 0 Single-Bit Correction Interrupt Notification
                                                     Enable                                                                  */
    } bit;
  } CFG0;
  __IM  uint32_t  RESERVED[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Status Register 0                                          */

    struct {
      __IM  uint32_t RESERVED0  : 26;
      __IOM uint32_t UEFLGM1    : 1;            /* [26..26] Memory 1 Uncorrectable Error Event Flag                          */
      __IOM uint32_t SBCFLGM1   : 1;            /* [27..27] Memory 1 Single-Bit Correction Event Flag                        */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t UEFLGM0    : 1;            /* [30..30] Memory 0 Uncorrectable Error Event Flag                          */
      __IOM uint32_t SBCFLGM0   : 1;            /* [31..31] Memory 0 Single-Bit Correction Event Flag                        */
    } bit;
  } STS0;
  __IM  uint32_t  RESERVED1[59];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000100) Error Address Register 0                                   */

    struct {
      __IM  uint32_t EADDR      : 32;           /* [31..0] EADDR                                                             */
    } bit;
  } EADDR0;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000110) Error Address Register 1                                   */

    struct {
      __IM  uint32_t EADDR      : 32;           /* [31..0] EADDR                                                             */
    } bit;
  } EADDR1;
} EREP_T;                                    /* Size = 276 (0x114)                                                        */



/* =========================================================================================================================== */
/* ================                                           EINJ                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Error Injection (EINJ)
  */

typedef struct {                                /* (@ 0x40019000) EINJ Structure                                             */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Configure Register                                         */

    struct {
      __IOM uint32_t GEINJEN    : 1;            /* [0..0] Global Error Injection Function Enable                             */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } CFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Channel Enable Register                                    */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t EINJENCH1  : 1;            /* [30..30] Error Injection CH1 Enable                                       */
      __IOM uint32_t EINJENCH0  : 1;            /* [31..31] Error Injection CH0 Enable                                       */
    } bit;
  } CHEN;
  __IM  uint32_t  RESERVED[62];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000100) Channel Descriptor 0, Word0 Register                       */

    struct {
      __IM  uint32_t RESERVED0  : 25;
      __IOM uint32_t CBCBINV    : 7;            /* [31..25] Checkbit Bus Corresponding Bit Invert                            */
    } bit;
  } CHD0_WORD0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000104) Channel Descriptor 0, Word1 Register                       */

    struct {
      __IOM uint32_t DBCBINVB0_3 : 32;          /* [31..0] Data Bus 0-3 Bytes Corresponding Bit Invert                       */
    } bit;
  } CHD0_WORD1;
  __IM  uint32_t  RESERVED1[62];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000200) Channel Descriptor 1, Word0 Register                       */

    struct {
      __IM  uint32_t RESERVED0  : 25;
      __IOM uint32_t CBCBINV    : 7;            /* [31..25] Checkbit Bus Corresponding Bit Invert                            */
    } bit;
  } CHD1_WORD0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000204) Channel Descriptor 1, Word1 Register                       */

    struct {
      __IOM uint32_t DBCBINVB0_3 : 32;          /* [31..0] Data Bus 0-3 Bytes Corresponding Bit Invert                       */
    } bit;
  } CHD1_WORD1;
} EINJ_T;                                    /* Size = 520 (0x208)                                                        */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash Memory (FLASH)
  */

typedef struct {                                /* (@ 0x40020000) FLASH Structure                                            */

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000000) Status Register                                            */

    struct {
      __IM  uint8_t EDFLG       : 1;            /* [0..0] Error Detect Flag                                                  */
            uint8_t             : 3;
      __IOM uint8_t PROVFLG     : 1;            /* [4..4] Protection Violation Flag                                          */
      __IOM uint8_t ACCEFLG     : 1;            /* [5..5] Access Error Flag                                                  */
      __IOM uint8_t COLEFLG     : 1;            /* [6..6] Collision Error Flag                                               */
      __IOM uint8_t OCIFLG      : 1;            /* [7..7] Operation Completed Interrupt Flag                                 */
    } bit;
  } STS;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000001) Configure Register                                         */

    struct {
      __IM  uint8_t EERAMSTS    : 1;           /* [0..0] EERAM State, RAM Available for EEPROM                              */
      __IM  uint8_t RAMCSTS     : 1;            /* [1..1] RAM Current State                                                  */
            uint8_t             : 2;
      __IOM uint8_t ERACMDSUS   : 1;            /* [4..4] Erase Command Suspend                                              */
      __IM  uint8_t ERAABREQ    : 1;            /* [5..5] Erase All Blocks Request                                           */
      __IOM uint8_t RCOLEIEN    : 1;            /* [6..6] Read Collision Error Interrupt Enable                              */
      __IOM uint8_t CMDCIEN     : 1;            /* [7..7] Command Complete Interrupt Enable                                  */
    } bit;
  } CFG;

  union {
    __IM  uint8_t reg;                          /* (@ 0x00000002) Security Register                                          */

    struct {
      __IM  uint8_t SECFLG      : 2;            /* [1..0] Flash Secure Flag                                                  */
      __IM  uint8_t FCACCEN     : 2;            /* [3..2] Flash Content Access Enable                                        */
      __IM  uint8_t MERAEN      : 2;            /* [5..4] Mass Erase Enable                                                  */
      __IM  uint8_t BKEYACCEN   : 2;            /* [7..6] Backdoor Key Access Enable                                         */
    } bit;
  } SEC;

  union {
    __IM  uint8_t reg;                          /* (@ 0x00000003) Nonvolatile Option Register                                */

    struct {
      __IM  uint8_t NOPT        : 8;            /* [7..0] Nonvolatile Option                                                 */
    } bit;
  } NOPT;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000004) Common Command Data Registers 3                            */

    struct {
      __IOM uint8_t PCMDCODEP3  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA3;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000005) Common Command Data Registers 2                            */

    struct {
      __IOM uint8_t PCMDCODEP2  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA2;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000006) Common Command Data Registers 1                            */

    struct {
      __IOM uint8_t PCMDCODEP1  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA1;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000007) Common Command Data Registers 0                            */

    struct {
      __IOM uint8_t PCMDCODEP0  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA0;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000008) Common Command Data Registers 7                            */

    struct {
      __IOM uint8_t PCMDCODEP7  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA7;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000009) Common Command Data Registers 6                            */

    struct {
      __IOM uint8_t PCMDCODEP6  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA6;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000A) Common Command Data Registers 5                            */

    struct {
      __IOM uint8_t PCMDCODEP5  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA5;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000B) Common Command Data Registers 4                            */

    struct {
      __IOM uint8_t PCMDCODEP4  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA4;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000C) Common Command Data Registers B                            */

    struct {
      __IOM uint8_t PCMDCODEPB  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATAB;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000D) Common Command Data Registers A                            */

    struct {
      __IOM uint8_t PCMDCODEPA  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATAA;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000E) Common Command Data Registers 9                            */

    struct {
      __IOM uint8_t PCMDCODEP9  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA9;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000000F) Common Command Data Registers 8                            */

    struct {
      __IOM uint8_t PCMDCODEP8  : 8;            /* [7..0] Provide Command Code and Parameter                                 */
    } bit;
  } CCMDDATA8;

  union {
    __IOM uint8_t reg;                          /*!< (@ 0x00000010) Program Flash Protect Register 3                           */

    struct {
      __IOM uint8_t PFPRO0      : 1;            /*!< [0..0] Program Flash Protect Area 0                                       */
      __IOM uint8_t PFPRO1      : 1;            /*!< [1..1] Program Flash Protect Area 1                                       */
      __IOM uint8_t PFPRO2      : 1;            /*!< [2..2] Program Flash Protect Area 2                                       */
      __IOM uint8_t PFPRO3      : 1;            /*!< [3..3] Program Flash Protect Area 3                                       */
      __IOM uint8_t PFPRO4      : 1;            /*!< [4..4] Program Flash Protect Area 4                                       */
      __IOM uint8_t PFPRO5      : 1;            /*!< [5..5] Program Flash Protect Area 5                                       */
      __IOM uint8_t PFPRO6      : 1;            /*!< [6..6] Program Flash Protect Area 6                                       */
      __IOM uint8_t PFPRO7      : 1;            /*!< [7..7] Program Flash Protect Area 7                                       */
    } bit;
  } PFPRO3;

  union {
    __IOM uint8_t reg;                          /*!< (@ 0x00000011) Program Flash Protect Register 2                           */

    struct {
      __IOM uint8_t PFPRO8      : 1;            /*!< [0..0] Program Flash Protect Area 8                                       */
      __IOM uint8_t PFPRO9      : 1;            /*!< [1..1] Program Flash Protect Area 9                                       */
      __IOM uint8_t PFPRO10     : 1;            /*!< [2..2] Program Flash Protect Area 10                                      */
      __IOM uint8_t PFPRO11     : 1;            /*!< [3..3] Program Flash Protect Area 11                                      */
      __IOM uint8_t PFPRO12     : 1;            /*!< [4..4] Program Flash Protect Area 12                                      */
      __IOM uint8_t PFPRO13     : 1;            /*!< [5..5] Program Flash Protect Area 13                                      */
      __IOM uint8_t PFPRO14     : 1;            /*!< [6..6] Program Flash Protect Area 14                                      */
      __IOM uint8_t PFPRO15     : 1;            /*!< [7..7] Program Flash Protect Area 15                                      */
    } bit;
  } PFPRO2;

  union {
    __IOM uint8_t reg;                          /*!< (@ 0x00000012) Program Flash Protect Register 1                           */

    struct {
      __IOM uint8_t PFPRO16     : 1;            /*!< [0..0] Program Flash Protect Area 16                                      */
      __IOM uint8_t PFPRO17     : 1;            /*!< [1..1] Program Flash Protect Area 17                                      */
      __IOM uint8_t PFPRO18     : 1;            /*!< [2..2] Program Flash Protect Area 18                                      */
      __IOM uint8_t PFPRO19     : 1;            /*!< [3..3] Program Flash Protect Area 19                                      */
      __IOM uint8_t PFPRO20     : 1;            /*!< [4..4] Program Flash Protect Area 20                                      */
      __IOM uint8_t PFPRO21     : 1;            /*!< [5..5] Program Flash Protect Area 21                                      */
      __IOM uint8_t PFPRO22     : 1;            /*!< [6..6] Program Flash Protect Area 22                                      */
      __IOM uint8_t PFPRO23     : 1;            /*!< [7..7] Program Flash Protect Area 23                                      */
    } bit;
  } PFPRO1;

  union {
    __IOM uint8_t reg;                          /*!< (@ 0x00000013) Program Flash Protect Register 0                           */

    struct {
      __IOM uint8_t PFPRO24     : 1;            /*!< [0..0] Program Flash Protect Area 24                                      */
      __IOM uint8_t PFPRO25     : 1;            /*!< [1..1] Program Flash Protect Area 25                                      */
      __IOM uint8_t PFPRO26     : 1;            /*!< [2..2] Program Flash Protect Area 26                                      */
      __IOM uint8_t PFPRO27     : 1;            /*!< [3..3] Program Flash Protect Area 27                                      */
      __IOM uint8_t PFPRO28     : 1;            /*!< [4..4] Program Flash Protect Area 28                                      */
      __IOM uint8_t PFPRO29     : 1;            /*!< [5..5] Program Flash Protect Area 29                                      */
      __IOM uint8_t PFPRO30     : 1;            /*!< [6..6] Program Flash Protect Area 30                                      */
      __IOM uint8_t PFPRO31     : 1;            /*!< [7..7] Program Flash Protect Area 31                                      */
    } bit;
  } PFPRO0;
  __IM  uint8_t   RESERVED[2];

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000016) EEPROM Protect Register                                    */

    struct {
      __IOM uint8_t EEPRO        : 8;            /* [7..0] EEPROM Protect                                                     */
    } bit;
  } EEPRO;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000017) Data Flash Protect Register                                */

    struct {
      __IOM uint8_t DFPRO   : 8;            /* [7..0] Data Flash Protect                                                 */
    } bit;
  } DFPRO;
  __IM  uint8_t   RESERVED1[20];

  union {
    __IM  uint8_t reg;                          /* (@ 0x0000002C) CSE Status Register                                        */

    struct {
      __IM  uint8_t BUSY        : 1;            /* [0..0] Busy                                                               */
      __IM  uint8_t SBACTSTS    : 1;            /* [1..1] Secure Boot Activated Status                                       */
      __IM  uint8_t SBINITFLG   : 1;            /* [2..2] Secure Boot Initialization Completed flag                          */
      __IM  uint8_t SBCMPFLG    : 1;            /* [3..3] Secure Boot Complete Flag                                          */
      __IM  uint8_t SBSUCFLG    : 1;            /* [4..4] Secure Boot Successful Flag                                        */
      __IM  uint8_t RNGINITFLG  : 1;            /* [5..5] Random Number Generator Initialized Flag                           */
      __IM  uint8_t EXTDBGAFLG  : 1;            /* [6..6] External Debug Attached Flag                                       */
      __IM  uint8_t IDBGENFLG   : 1;            /* [7..7] Internal Debug Enable Flag                                         */
    } bit;
  } CSECSTS;
  __IM  uint8_t   RESERVED2;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000002E) Error Status Register                                      */

    struct {
            uint8_t             : 1;
      __IOM uint8_t DBFIFLG     : 1;            /* [1..1] Double Bit Fault Interrupt Flag                                    */
            uint8_t             : 6;
    } bit;
  } ESTS;

  union {
    __IOM uint8_t reg;                          /* (@ 0x0000002F) Error Configuration Register                               */

    struct {
            uint8_t             : 1;
      __IOM uint8_t DBFIEN      : 1;            /* [1..1] Double Bit Fault Interrupt Enable                                  */
            uint8_t             : 3;
      __IOM uint8_t EDBFINTD    : 1;            /* [5..5] Emulate Double Bit Fault Interrupt Detect                          */
            uint8_t             : 2;
    } bit;
  } ECFG;
} FLASH_T;                                   /* Size = 48 (0x30)                                                             */



/* =========================================================================================================================== */
/* ================                                          DMACHM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA Memory Access Channel Multiplexer (DMACHM)
  */

typedef struct {                                /* (@ 0x40021000) DMACHM Structure                                           */

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000000) Channel register 0                                         */

    struct {
      __IOM uint8_t SRCCFG      : 6;            /* [5..0] DMA Channel Source Configure                                       */
      __IOM uint8_t PRDTREN     : 1;            /* [6..6] DMA Channel Periodic Trigger Enable                                */
      __IOM uint8_t CHEN        : 1;            /* [7..7] DMA Channel Enable                                                 */
    } bit;
  } CFG[16u];
} DMACHM_T;                                  /* Size = 16 (0x10)                                                             */



/* =========================================================================================================================== */
/* ================                                         CAN                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Controller Local Area Network (CAN)
  */

typedef struct {                                /*  CAN Structure
                                                       (@ 0x40024000)CAN0 (@ 0x40025000)CAN1 (@ 0x4002B000)CAN2  */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Module Configure register                                  */

    struct {
      __IOM uint32_t LASTMB     : 7;            /* [6..0] Number of the Last Message Buffer                                  */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t IDFFMT     : 2;            /* [9..8] Rx FIFO ID Filter Format                                           */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t CANFDEN    : 1;            /* [11..11] CAN FD Operation Enable                                          */
      __IOM uint32_t TAEN       : 1;            /* [12..12] Tx Abort Mechanism Enable                                        */
      __IOM uint32_t LPRIEN     : 1;            /* [13..13] Local Priority Enable                                            */
      __IOM uint32_t PNEN       : 1;            /* [14..14] Pretended Networking Enable                                      */
      __IOM uint32_t DMAEN      : 1;            /* [15..15] DMA Enable for Rx FIFO                                           */
      __IOM uint32_t IRXMQEN    : 1;            /* [16..16] Individual Receive Masking and Queue Enable                      */
      __IOM uint32_t SRD        : 1;            /* [17..17] Self Reception Disable                                           */
      __IM  uint32_t RESERVED2  : 2;
      __IM  uint32_t LPM        : 1;            /* [20..20] Low-Power Mode                                                   */
      __IOM uint32_t WIEN       : 1;            /* [21..21] Warning Interrupt Enable                                         */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t SVEN       : 1;            /* [23..23] Supervisor Mode Enable                                           */
      __IM  uint32_t FRZFLG     : 1;            /* [24..24] Freeze Mode Flag                                                 */
      __IOM uint32_t CANRST     : 1;            /* [25..25] CAN Reset                                                        */
      __IM  uint32_t RESERVED4  : 1;
      __IM  uint32_t NRDY       : 1;            /* [27..27] Not Ready                                                        */
      __IOM uint32_t EFRZ       : 1;            /* [28..28] Enter Freeze Mode                                                */
      __IOM uint32_t FIFOEN     : 1;            /* [29..29] Rx FIFO Enable                                                   */
      __IOM uint32_t FRZEN      : 1;            /* [30..30] Freeze Mode Enable                                               */
      __IOM uint32_t CMD        : 1;            /* [31..31] CAN Module Disable                                               */
    } bit;
  } MCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Control register 1                                         */

    struct {
      __IOM uint32_t PTS        : 3;            /* [2..0] Propagation Time Segment                                           */
      __IOM uint32_t LOEN       : 1;            /* [3..3] Listen-Only Mode Enable                                            */
      __IOM uint32_t TXLB       : 1;            /* [4..4] Transmit Lowest Buffer First                                       */
      __IOM uint32_t TMRSYN     : 1;            /* [5..5] Timer Sync Feature Enable                                          */
      __IOM uint32_t BORD       : 1;            /* [6..6] Bus Off Recovery Disable                                           */
      __IOM uint32_t TSEN       : 1;            /* [7..7] Triple Sampling Enable                                             */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t RXWIEN     : 1;            /* [10..10] Rx Warning Interrupt Enable                                      */
      __IOM uint32_t TXWIEN     : 1;            /* [11..11] Tx Warning Interrupt Enable                                      */
      __IOM uint32_t LBEN       : 1;            /* [12..12] Loop Back Mode Enable                                            */
      __IOM uint32_t CLKSEL     : 1;            /* [13..13] CAN Engine Clock Source Select                                   */
      __IOM uint32_t ERRIEN     : 1;            /* [14..14] Error Interrupt Enable                                           */
      __IOM uint32_t BOIEN      : 1;            /* [15..15] Bus Off Interrupt Enable                                         */
      __IOM uint32_t PBS2       : 3;            /* [18..16] Phase Buffer Segment 2                                           */
      __IOM uint32_t PBS1       : 3;            /* [21..19] Phase Buffer Segment 1                                           */
      __IOM uint32_t SJW        : 2;            /* [23..22] Resynchronized Jump Width                                        */
      __IOM uint32_t PDF        : 8;            /* [31..24] Prescaler Division Factor                                        */
    } bit;
  } CTRL1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Free Running Timer register                                */

    struct {
      __IOM uint32_t FRTMR      : 16;           /* [15..0] Free Runnning Timer Value                                         */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } FRTMR;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Rx Mailboxes Global Mask register                          */

    struct {
      __IOM uint32_t RXMASK     : 32;           /* [31..0] Rx Mailboxes Global Mask                                          */
    } bit;
  } RXMASK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Rx 14 Mask register                                        */

    struct {
      __IOM uint32_t RX14MASK   : 32;           /* [31..0] Rx Buffer 14 Mask                                                 */
    } bit;
  } RX14MASK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Rx 15 Mask register                                        */

    struct {
      __IOM uint32_t RX15MASK   : 32;           /* [31..0] Rx Buffer 15 Mask                                                 */
    } bit;
  } RX15MASK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) Error Counter register                                     */

    struct {
      __IOM uint32_t TXERRCNT   : 8;            /* [7..0] Transmit Error Counter                                             */
      __IOM uint32_t RXERRCNT   : 8;            /* [15..8] Receive Error Counter                                             */
      __IOM uint32_t FTXERRCNT  : 8;            /* [23..16] Fast Transmit Error Counter                                      */
      __IOM uint32_t FRXERRCNT  : 8;            /* [31..24] Fast Receive Error Counter                                       */
    } bit;
  } ERRCNT;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Error Flag register 1                                      */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t ERRFLG     : 1;            /* [1..1] Error Interrupt Flag                                               */
      __IOM uint32_t BOFLG      : 1;            /* [2..2] Bus Off Flag                                                       */
      __IM  uint32_t RXFLG      : 1;            /* [3..3] Being Receive Flag                                                 */
      __IM  uint32_t FCFLG      : 2;            /* [5..4] Fault Confinement Flag                                             */
      __IM  uint32_t TXFLG      : 1;            /* [6..6] Being Transmit Flag                                                */
      __IM  uint32_t BIDLEFLG   : 1;            /* [7..7] Bus Idle Flag                                                      */
      __IM  uint32_t RXERRWFLG  : 1;            /* [8..8] RX Error Warning Flag                                              */
      __IM  uint32_t TXERRWFLG  : 1;            /* [9..9] TX Error Warning Flag                                              */
      __IM  uint32_t SERRFLG    : 1;            /* [10..10] Stuffing Error Flag                                              */
      __IM  uint32_t FERRFLG    : 1;            /* [11..11] Form Error Flag                                                  */
      __IM  uint32_t CRCERRFLG  : 1;            /* [12..12] CRC Error Flag                                                   */
      __IM  uint32_t ACKERRFLG  : 1;            /* [13..13] Acknowledge Error Flag                                           */
      __IM  uint32_t B0ERRFLG   : 1;            /* [14..14] Bit0 Error Flag                                                  */
      __IM  uint32_t B1ERRFLG   : 1;            /* [15..15] Bit1 Error Flag                                                  */
      __IOM uint32_t RXWINTFLG  : 1;            /* [16..16] Rx Warning Interrupt Flag                                        */
      __IOM uint32_t TXWINTFLG  : 1;            /* [17..17] Tx Warning Interrupt Flag                                        */
      __IM  uint32_t BSYNFLG    : 1;            /* [18..18] CAN Bus Synchronization Flag                                     */
      __IOM uint32_t BOCINTFLG  : 1;            /* [19..19] Bus Off Process Complete Flag                                    */
      __IOM uint32_t FDERRFLG   : 1;            /* [20..20] Error Interrupt Detected in CAN FD Frame Data Phase
                                                     with BRS bit Set Flag                                                   */
      __IOM uint32_t OVRFLG     : 1;            /* [21..21] Overrun Flag                                                     */
      __IM  uint32_t RESERVED1  : 4;
      __IM  uint32_t FDSERRFLG  : 1;            /* [26..26] Stuffing Error in CAN FD Frame Data Phase with BRS
                                                     bit Set                                                                 */
      __IM  uint32_t FDFERRFLG  : 1;            /* [27..27] Form Error in CAN FD Frame Data Phase with BRS bit
                                                     Set                                                                      */
      __IM  uint32_t FDCRCERRFLG : 1;           /* [28..28] CRC Error in CAN FD Frame Data Phasewith BRS bit Set              */
      __IM  uint32_t RESERVED2  : 1;
      __IM  uint32_t FDB0ERRFLG : 1;            /* [30..30] Bit0 Error in CAN FD Frames Data Phase with BRS bit
                                                     Set                                                                      */
      __IM  uint32_t FDB1ERRFLG : 1;            /* [31..31] Bit1 Error in CAN FD Frames Data Phase with BRS bit
                                                     Set                                                                      */
    } bit;
  } ERRFLG1;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000028) Message Buffer i Interrupt Enable register                 */

    struct {
      __IOM uint32_t MB0IEN     : 1;            /* [0..0] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB1IEN     : 1;            /* [1..1] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB2IEN     : 1;            /* [2..2] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB3IEN     : 1;            /* [3..3] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB4IEN     : 1;            /* [4..4] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB5IEN     : 1;            /* [5..5] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB6IEN     : 1;            /* [6..6] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB7IEN     : 1;            /* [7..7] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB8IEN     : 1;            /* [8..8] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB9IEN     : 1;            /* [9..9] Buffer MB 0-31 Mask                                                */
      __IOM uint32_t MB10IEN    : 1;            /* [10..10] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB11IEN    : 1;            /* [11..11] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB12IEN    : 1;            /* [12..12] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB13IEN    : 1;            /* [13..13] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB14IEN    : 1;            /* [14..14] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB15IEN    : 1;            /* [15..15] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB16IEN    : 1;            /* [16..16] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB17IEN    : 1;            /* [17..17] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB18IEN    : 1;            /* [18..18] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB19IEN    : 1;            /* [19..19] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB20IEN    : 1;            /* [20..20] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB21IEN    : 1;            /* [21..21] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB22IEN    : 1;            /* [22..22] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB23IEN    : 1;            /* [23..23] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB24IEN    : 1;            /* [24..24] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB25IEN    : 1;            /* [25..25] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB26IEN    : 1;            /* [26..26] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB27IEN    : 1;            /* [27..27] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB28IEN    : 1;            /* [28..28] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB29IEN    : 1;            /* [29..29] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB30IEN    : 1;            /* [30..30] Buffer MB 0-31 Mask                                              */
      __IOM uint32_t MB31IEN    : 1;            /* [31..31] Buffer MB 0-31 Mask                                              */
    } bit;
  } MBiIEN;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000030) Interrupt Flag register                                    */

    struct {
      __IOM uint32_t MB0INT     : 1;            /* [0..0] Buffer MB0 Interrupt or Clear FIFO Bit Flag                        */
      __IOM uint32_t MB1INT     : 1;            /* [1..1] Buffer MB1-4 Interrupt or Reserved Flag                            */
      __IOM uint32_t MB2INT     : 1;            /* [2..2] Buffer MB1-4 Interrupt or Reserved Flag                            */
      __IOM uint32_t MB3INT     : 1;            /* [3..3] Buffer MB1-4 Interrupt or Reserved Flag                            */
      __IOM uint32_t MB4INT     : 1;            /* [4..4] Buffer MB1-4 Interrupt or Reserved Flag                            */
      __IOM uint32_t MB5INT     : 1;            /* [5..5] Buffer MB5 Interrupt or Frames Available in Rx FIFO Flag           */
      __IOM uint32_t MB6INT     : 1;            /* [6..6] Buffer MB6 Interrupt or Rx FIFO Warning Flag                       */
      __IOM uint32_t MB7INT     : 1;            /* [7..7] Buffer MB7 Interrupt or Rx FIFO Overflow Flag                      */
      __IOM uint32_t MB8INT     : 1;            /* [8..8] MB8-31 Buffer Completed Transmission or Reception Flag             */
      __IOM uint32_t MB9INT     : 1;            /* [9..9] MB8-31 Buffer Completed Transmission or Reception Flag             */
      __IOM uint32_t MB10INT    : 1;            /* [10..10] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB11INT    : 1;            /* [11..11] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB12INT    : 1;            /* [12..12] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB13INT    : 1;            /* [13..13] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB14INT    : 1;            /* [14..14] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB15INT    : 1;            /* [15..15] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB16INT    : 1;            /* [16..16] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB17INT    : 1;            /* [17..17] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB18INT    : 1;            /* [18..18] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB19INT    : 1;            /* [19..19] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB20INT    : 1;            /* [20..20] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB21INT    : 1;            /* [21..21] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB22INT    : 1;            /* [22..22] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB23INT    : 1;            /* [23..23] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB24INT    : 1;            /* [24..24] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB25INT    : 1;            /* [25..25] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB26INT    : 1;            /* [26..26] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB27INT    : 1;            /* [27..27] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB28INT    : 1;            /* [28..28] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB29INT    : 1;            /* [29..29] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB30INT    : 1;            /* [30..30] MB8-31 Buffer Completed Transmission or Reception Flag           */
      __IOM uint32_t MB31INT    : 1;            /* [31..31] MB8-31 Buffer Completed Transmission or Reception Flag           */
    } bit;
  } IFLG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000034) Control register 2                                         */

    struct {
      __IM  uint32_t RESERVED0  : 11;
      __IOM uint32_t EFD        : 1;            /* [11..11] Edge Filter Disable                                              */
      __IOM uint32_t ISOFDEN    : 1;            /* [12..12] ISO CAN FD Protocol Enable                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t PEEN       : 1;            /* [14..14] Protocol Exception Enable                                        */
      __IOM uint32_t TMRSRC     : 1;            /* [15..15] Time Source for the Free Running Timer                           */
      __IOM uint32_t CMPEN      : 1;            /* [16..16] IDE and RTR Bit Comparison Enable For Receive Mailboxes          */
      __IOM uint32_t RFS        : 1;            /* [17..17] Remote Request Frame Storing                                     */
      __IOM uint32_t MBPRI      : 1;            /* [18..18] Mailboxes Reception Priority Configure                           */
      __IOM uint32_t TXASD      : 5;            /* [23..19] Transmit Arbitration Start Delay                                 */
      __IOM uint32_t NUMFIFO    : 4;            /* [27..24] Number of Receive FIFO Filters                                   */
      __IM  uint32_t RESERVED2  : 2;
      __IOM uint32_t BOCIEN     : 1;            /* [30..30] Bus Off Process Complete Interrupt Enable                        */
      __IOM uint32_t FDERRIEN   : 1;            /* [31..31] Error Interrupt Detected in Fast CAN FD Frame Data
                                                     Phase Enable                                                            */
    } bit;
  } CTRL2;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000038) Error Flag register 2                                      */

    struct {
      __IM  uint32_t RESERVED0  : 13;
      __IM  uint32_t IAMBFLG    : 1;            /* [13..13] Inactive Mailbox Flag                                            */
      __IM  uint32_t CVFLG      : 1;            /* [14..14] Contents Valid Flag                                              */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t LTXMB      : 7;            /* [22..16] Lowest Priority Transmission Mailbox Flag                        */
      __IM  uint32_t RESERVED2  : 9;
    } bit;
  } ERRFLG2;
  __IM  uint32_t  RESERVED3[2];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000044) CRC register                                               */

    struct {
      __IM  uint32_t CRCV       : 15;           /* [14..0] Transmitted CRC Value                                             */
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t CRCMB      : 7;            /* [22..16] Number of CRC Mailbox                                            */
      __IM  uint32_t RESERVED1  : 9;
    } bit;
  } CRC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000048) Rx FIFO Global Mask register                               */

    struct {
      __IOM uint32_t FIFOGMASK  : 32;           /* [31..0] Rx FIFO Global Mask                                               */
    } bit;
  } FIFOGMASK;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000004C) Rx FIFO Information register                               */

    struct {
      __IM  uint32_t IAF        : 9;            /* [8..0] ID Acceptance Filter Hit Indicator                                 */
      __IM  uint32_t RESERVED0  : 23;
    } bit;
  } FIFOINFO;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000050) Bit Timing register                                        */

    struct {
      __IOM uint32_t EPBS2      : 5;            /* [4..0] Extended Phase Buffer Segment 2                                    */
      __IOM uint32_t EPBS1      : 5;            /* [9..5] Extended Phase Buffer Segment 1                                    */
      __IOM uint32_t EPTS       : 6;            /* [15..10] Extended Propagation Time Segment                                */
      __IOM uint32_t ESJW       : 5;            /* [20..16] Extended Resynchronized Jump Width                               */
      __IOM uint32_t EPDF       : 10;           /* [30..21] Extended Prescaler Division Factor                               */
      __IOM uint32_t EBTEN      : 1;            /* [31..31] Extended Bit Time Enable                                         */
    } bit;
  } BTIM;
  __IM  uint32_t  RESERVED4[11];

  union {
    __IOM uint32_t reg;                    /* (@ 0x00000080) Embedded RAM                                                    */

    struct {
      __IOM uint32_t DATA_BYTE_3 : 8;           /* [7..0] Data byte 3 of Rx/Tx frame.                                        */
      __IOM uint32_t DATA_BYTE_2 : 8;           /* [15..8] Data byte 2 of Rx/Tx frame.                                       */
      __IOM uint32_t DATA_BYTE_1 : 8;           /* [23..16] Data byte 1 of Rx/Tx frame.                                      */
      __IOM uint32_t DATA_BYTE_0 : 8;           /* [31..24] Data byte 0 of Rx/Tx frame.                                      */
    } bit;
  } RAMn[128];
  __IM  uint32_t  RESERVED5[384];

  union {
    __IOM uint32_t reg;                     /* (@ 0x00000880) Rx Individual Mask registers                                   */

    struct {
      __IOM uint32_t IBMASK     : 32;           /* [31..0] Individual Bits Mask                                              */
    } bit;
  } RXIMASK[32];
  __IM  uint32_t  RESERVED6[128];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B00) Pretended Networking Control register 1                    */

    struct {
      __IOM uint32_t FCSEL      : 2;            /* [1..0] Filtering Criteria Select                                          */
      __IOM uint32_t IDFLSEL    : 2;            /* [3..2] ID Filtering Level Select                                          */
      __IOM uint32_t PFLSEL     : 2;            /* [5..4] Payload Filtering Level Select                                     */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t NUMMSG     : 8;            /* [15..8] Number of Messages Matching the Same Filtering Criteria           */
      __IOM uint32_t WUMEN      : 1;            /* [16..16] Wakeup by Match Event Enable                                     */
      __IOM uint32_t WUTEN      : 1;            /* [17..17] Wakeup by Timeout Event Enable                                   */
      __IM  uint32_t RESERVED1  : 14;
    } bit;
  } PNCTRL1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B04) Pretended Networking Contro register 2                     */

    struct {
      __IOM uint32_t TOV        : 16;           /* [15..0] Timeout Value for No Message Matching the Filtering
                                                     Criteria                                                                */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } PNCTRL2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B08) Pretended Networking Wake Up Match register                */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IM  uint32_t NUMM       : 8;            /* [15..8] Number of Matches when in Pretended Networking                    */
      __IOM uint32_t WUMFLG     : 1;            /* [16..16] Wakeup by Match Event Flag                                       */
      __IOM uint32_t WUTFLG     : 1;            /* [17..17] Wakeup by Timeout Event Flag                                     */
      __IM  uint32_t RESERVED1  : 14;
    } bit;
  } PNWM;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B0C) Pretended Networking ID Filter 1 register                  */

    struct {
      __IOM uint32_t IDF        : 29;           /* [28..0] ID Filter 1 for Pretended Networking                              */
      __IOM uint32_t RFF        : 1;            /* [29..29] Remote Frame Filter                                              */
      __IOM uint32_t EXFF       : 1;            /* [30..30] Extended Frame Format Filter                                     */
      __IM  uint32_t RESERVED0  : 1;
    } bit;
  } PNIDF1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B10) Pretended Networking Length Code Filter register          */

    struct {
      __IOM uint32_t DLCHI      : 4;            /* [3..0] Payload Data Length Code Higher Limit                             */
      __IM  uint32_t RESERVED0  : 12;
      __IOM uint32_t DLCLO      : 4;            /* [19..16] Payload Data Length Code Lower Limit                            */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } PNDLCF;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B14) Pretended Networking Payload Low Filter 1 register         */

    struct {
      __IOM uint32_t BYTE3      : 8;            /* [7..0] Byte3                                                              */
      __IOM uint32_t BYTE2      : 8;            /* [15..8] Byte2                                                             */
      __IOM uint32_t BYTE1      : 8;            /* [23..16] Byte1                                                            */
      __IOM uint32_t BYTE0      : 8;            /* [31..24] Byte0                                                            */
    } bit;
  } PNPLF1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B18) Pretended Networking Payload High Filter 1 register        */

    struct {
      __IOM uint32_t BYTE7      : 8;            /* [7..0] Byte7                                                              */
      __IOM uint32_t BYTE6      : 8;            /* [15..8] Byte6                                                             */
      __IOM uint32_t BYTE5      : 8;            /* [23..16] Byte5                                                            */
      __IOM uint32_t BYTE4      : 8;            /* [31..24] Byte4                                                            */
    } bit;
  } PNPHF1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B1C) Pretended Networking ID Filter 2 Register                  */

    struct {
      __IOM uint32_t IDMASK     : 29;           /* [28..0] ID Mask Bits for Pretended Networking ID Filtering                */
      __IOM uint32_t RFMASK     : 1;            /* [29..29] Remote Frame Filter Mask                                         */
      __IOM uint32_t EXFMASK    : 1;            /* [30..30] Extended Frame Format Filter Mask                                */
      __IM  uint32_t RESERVED0  : 1;
    } bit;
  } PNIDF2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B20) Pretended Networking Payload Low Filter 2 Register         */

    struct {
      __IOM uint32_t BYTE3      : 8;            /* [7..0] Byte3                                                              */
      __IOM uint32_t BYTE2      : 8;            /* [15..8] Byte2                                                             */
      __IOM uint32_t BYTE1      : 8;            /* [23..16] Byte1                                                            */
      __IOM uint32_t BYTE0      : 8;            /* [31..24] Byte0                                                            */
    } bit;
  } PNPLF2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000B24) Pretended Networking Payload High Filter 2 register        */

    struct {
      __IOM uint32_t BYTE7      : 8;            /* [7..0] Byte7                                                              */
      __IOM uint32_t BYTE6      : 8;            /* [15..8] Byte6                                                             */
      __IOM uint32_t BYTE5      : 8;            /* [23..16] Byte5                                                            */
      __IOM uint32_t BYTE4      : 8;            /* [31..24] Byte4                                                            */
    } bit;
  } PNPHF2;
  __IM  uint32_t  RESERVED7[6];

  struct {
    union {
      __IM  uint32_t reg;                         /* (@ 0x00000B40) Wake Up Message Buffer register a for C/S                */


        struct {
          __IM  uint32_t RESERVED0  : 16;
          __IM  uint32_t DLC        : 4;            /* [19..16] Data Length Code                                             */
          __IM  uint32_t RTR        : 1;            /* [20..20] Remote Transmission Request Bit                              */
          __IM  uint32_t IDE        : 1;            /* [21..21] Identifier Extension Bit                                     */
          __IM  uint32_t SRR        : 1;            /* [22..22] Substitute Remote Request                                    */
          __IM  uint32_t RESERVED1  : 9;
        } bit;
      } WMBn_CS;

      union {
        __IM  uint32_t reg;                         /* (@ 0x00000B44) Wake Up Message Buffer Register a for ID               */

        struct {
          __IM  uint32_t WMID       : 29;           /* [28..0] Wake Up Message ID                                            */
          __IM  uint32_t RESERVED0  : 3;
        } bit;
      } WMBn_ID;

      union {
        __IM  uint32_t reg;                         /* (@ 0x00000B48) Wake Up Message Buffer Register a Low Data              */

        struct {
          __IM  uint32_t BYTE3      : 8;            /* [7..0] Byte3                                                           */
          __IM  uint32_t BYTE2      : 8;            /* [15..8] Byte2                                                          */
          __IM  uint32_t BYTE1      : 8;            /* [23..16] Byte1                                                         */
          __IM  uint32_t BYTE0      : 8;            /* [31..24] Byte0                                                         */
        } bit;
      } WMBn_LDATA;

      union {
        __IM  uint32_t reg;                         /* (@ 0x00000B4C) Wake Up Message Buffer Register a for High Data         */

        struct {
          __IM  uint32_t BYTE7      : 8;            /* [7..0] Byte7                                                           */
          __IM  uint32_t BYTE6      : 8;            /* [15..8] Byte6                                                          */
          __IM  uint32_t BYTE5      : 8;            /* [23..16] Byte5                                                         */
          __IM  uint32_t BYTE4      : 8;            /* [31..24] Byte4                                                         */
        } bit;
      } WMBn_HDATA;
    }WMB[4];

  __IM  uint32_t  RESERVED8[32];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000C00) FD Control register                                        */

    struct {
      __IM  uint32_t TDCV       : 6;            /* [5..0] Transceiver Delay Compensation Value                               */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t TDCOF      : 5;            /* [12..8] Transceiver Delay Compensation Offset                             */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TDCF       : 1;            /* [14..14] Transceiver Delay Compensation Mechanism has Failed              */
      __IOM uint32_t TDCEN      : 1;            /* [15..15] Transceiver Delay Compensation Feature Enable                    */
      __IOM uint32_t MBSIZE     : 2;            /* [17..16] Message Buffer Data Size for Region 0                            */
      __IM  uint32_t RESERVED2  : 13;
      __IOM uint32_t BRSEN      : 1;            /* [31..31] Bit Rate Switch Enable                                           */
    } bit;
  } FDCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000C04) FD Bit Timing register                                     */

    struct {
      __IOM uint32_t FPBS2      : 3;            /* [2..0] Fast Phase Buffer Segment 2                                        */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t FPBS1      : 3;            /* [7..5] Fast Phase Buffer Segment 1                                        */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t FPTS       : 5;            /* [14..10] Fast Propagation Time Segment                                    */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t FSJW       : 3;            /* [18..16] Fast Resynchronized Jump Width                                   */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t FPDF       : 10;           /* [29..20] Fast Prescaler Division Factor                                   */
      __IM  uint32_t RESERVED4  : 2;
    } bit;
  } FDBTIM;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000C08) FD CRC register                                            */

    struct {
      __IM  uint32_t EXTCRCV    : 21;           /* [20..0] Extended CRC Value of the Transmitted Message                     */
      __IM  uint32_t RESERVED0  : 3;
      __IM  uint32_t EXTCRCMB   : 7;            /* [30..24] Number of Extended CRC Mailbox                                   */
      __IM  uint32_t RESERVED1  : 1;
    } bit;
  } FDCRC;
} CAN_T;                                /* Size = 3084 (0xc0c)                                                           */



/* =========================================================================================================================== */
/* ================                                           CFGTMR                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Configurable Timer (CFGTMR)
  */

typedef struct {                                /*  CFGTMR Structure
                                             (@ 0x40038000)CFGTMR0 (@ 0x40039000)CFGTMR1 (@ 0x4003A000)CFGTMR2 (@ 0x40026000)CFGTMR3
                                             (@ 0x4006E000)CFGTMR4 (@ 0x4006F000)CFGTMR5                                         */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control and Status Register                                */

    struct {
      __IOM uint32_t CLKDFSEL   : 3;            /* [2..0] Clock Division Factor Select                                       */
      __IOM uint32_t CCLKSSEL   : 2;            /* [4..3] Counter Clock Source Select                                        */
      __IOM uint32_t CMSEL      : 1;            /* [5..5] CFGTMR Counter Mode Select                                           */
      __IOM uint32_t RPIEN      : 1;            /* [6..6] Reload Point Interrupt Enable                                      */
      __IOM  uint32_t RFLG       : 1;            /* [7..7] Reload Flag                                                       */
      __IOM uint32_t CFGTMROIEN   : 1;            /* [8..8] CFGTMR Overflow Interrupt Enable                                     */
      __IOM  uint32_t CFGTMROFLG   : 1;            /* [9..9] CFGTMR Overflow Flag                                                */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t PWMOENCH0  : 1;            /* [16..16] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH1  : 1;            /* [17..17] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH2  : 1;            /* [18..18] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH3  : 1;            /* [19..19] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH4  : 1;            /* [20..20] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH5  : 1;            /* [21..21] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH6  : 1;            /* [22..22] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t PWMOENCH7  : 1;            /* [23..23] PWM Channel 0-7 Output Enable                                    */
      __IOM uint32_t FPSCSEL    : 4;            /* [27..24] Filter Prescale Select                                           */
      __IM  uint32_t RESERVED1  : 4;
    } bit;
  } CSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Counter Register                                           */

    struct {
      __IOM uint32_t CNT        : 16;           /* [15..0] Counter Value                                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CNT;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Modulo Register                                            */

    struct {
      __IOM uint32_t MOD        : 16;           /* [15..0] Modulo Value                                                      */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } MOD;

  struct {
      union {
        __IOM uint32_t reg;                         /* (@ 0x0000000C) Channel (n) Control And Status Register                */

        struct {
          __IOM uint32_t DMAEN      : 1;            /* [0..0] DMA Enable                                                     */
          __IOM uint32_t CRSTCTRL   : 1;            /* [1..1] CFGTMR Counter Reset Control                                     */
          __IOM uint32_t CHMSEL0    : 1;            /* [2..2] Channel (n) Mode Select 0                                      */
          __IOM uint32_t CHMSEL1    : 1;            /* [3..3] Channel (n) Mode Select 1                                      */
          __IOM uint32_t CHMSEL2    : 1;            /* [4..4] Channel (n) Mode Select 2                                      */
          __IOM uint32_t CHMSEL3    : 1;            /* [5..5] Channel (n) Mode Select 3                                      */
          __IOM uint32_t CHIEN      : 1;            /* [6..6] Channel (n) Interrupt Enable                                   */
          __IOM uint32_t CHEVFLG    : 1;            /* [7..7] Channel (n) Event Flag                                        */
          __IOM uint32_t CHOTMCTRL  : 1;            /* [8..8] Channel (n) Output Trigger Mode Control                        */
          __IM  uint32_t CHISTS     : 1;            /* [9..9] Channel (n) Input State                                        */
          __IM  uint32_t CHOLSEL    : 1;            /* [10..10] Channel (n) Output Value Select                              */
        __IM  uint32_t RESERVED0  : 21;
        } bit;
      } CHnCSTS;

      union {
        __IOM uint32_t reg;                         /* (@ 0x00000010) Channel (n) Value Register                             */

        struct {
          __IOM uint32_t CHV        : 16;           /* [15..0] Channel Value                                                 */
          __IM  uint32_t RESERVED0  : 16;
        } bit;
      } CHnV;
  } CONTROLS[8];

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000004C) Initial Value Register                                     */

    struct {
      __IOM uint32_t INITV      : 16;           /* [15..0] Initial Value                                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } INITV;

  union {
    __IOM  uint32_t reg;                         /* (@ 0x00000050) Capture and Compare Status Register                     */

    struct {
      __IOM  uint32_t CHEVFLG0   : 1;            /* [0..0] Channel 0 Flag                                                   */
      __IOM  uint32_t CHEVFLG1   : 1;            /* [1..1] Channel 1 Flag                                                   */
      __IOM  uint32_t CHEVFLG2   : 1;            /* [2..2] Channel 2 Flag                                                   */
      __IOM  uint32_t CHEVFLG3   : 1;            /* [3..3] Channel 3 Flag                                                   */
      __IOM  uint32_t CHEVFLG4   : 1;            /* [4..4] Channel 4 Flag                                                   */
      __IOM  uint32_t CHEVFLG5   : 1;            /* [5..5] Channel 5 Flag                                                   */
      __IOM  uint32_t CHEVFLG6   : 1;            /* [6..6] Channel 6 Flag                                                   */
      __IOM  uint32_t CHEVFLG7   : 1;            /* [7..7] Channel 7 Flag                                                   */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } CCSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000054) Features Mode Select Register                              */

    struct {
      __IOM uint32_t CFGTMREN     : 1;            /* [0..0] CFGTMR Module Enable                                                 */
      __OM  uint32_t INITSTS    : 1;            /* [1..1] Channels Output Initialization Status                              */
      __IOM uint32_t WPUNLOCK   : 1;            /* [2..2] Write Protection unlock                                            */
      __IOM uint32_t PWMSMCFG   : 1;            /* [3..3] PWM Synchronization Mode Configure                                 */
      __IOM uint32_t CTMEN      : 1;            /* [4..4] Capture Test Mode Enable                                           */
      __IOM uint32_t FCTRLMSEL  : 2;            /* [6..5] Fault Control Mode Select                                          */
      __IOM uint32_t FCTRLIEN   : 1;            /* [7..7] Fault Control Interrupt Enable                                     */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } FMSEL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000058) Synchronization Register                                   */

    struct {
      __IOM uint32_t MINLPEN    : 1;            /* [0..0] Minimum Loading Point Enable                                       */
      __IOM uint32_t MAXLPEN    : 1;            /* [1..1] Maximum Loading Point Enable                                       */
      __IOM uint32_t CFGTMRCRINT  : 1;            /* [2..2] Reinitialization CFGTMR Counter Value Synchronization                */
      __IOM uint32_t OVSMSEL    : 1;            /* [3..3] Output Value Synchronization Mode Select                           */
      __IOM uint32_t HWT0SEL    : 1;            /* [4..4] PWM Synchronization Hardware Trigger 0 Select                      */
      __IOM uint32_t HWT1SEL    : 1;            /* [5..5] PWM Synchronization Hardware Trigger 1 Select                      */
      __IOM uint32_t HWT2SEL    : 1;            /* [6..6] PWM Synchronization Hardware Trigger 2 Select                      */
      __IOM uint32_t SWTSEL     : 1;            /* [7..7] PWM Synchronization Software Trigger Select                        */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } SYN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000005C) Channel Output Initialization Register                 */

    struct {
      __IOM uint32_t CHOISEL0   : 1;            /* [0..0] Channel 0 Output Initialization Value                            */
      __IOM uint32_t CHOISEL1   : 1;            /* [1..1] Channel 1 Output Initialization Value                            */
      __IOM uint32_t CHOISEL2   : 1;            /* [2..2] Channel 2 Output Initialization Value                            */
      __IOM uint32_t CHOISEL3   : 1;            /* [3..3] Channel 3 Output Initialization Value                            */
      __IOM uint32_t CHOISEL4   : 1;            /* [4..4] Channel 4 Output Initialization Value                            */
      __IOM uint32_t CHOISEL5   : 1;            /* [5..5] Channel 5 Output Initialization Value                            */
      __IOM uint32_t CHOISEL6   : 1;            /* [6..6] Channel 6 Output Initialization Value                            */
      __IOM uint32_t CHOISEL7   : 1;            /* [7..7] Channel 7 Output Initialization Value                            */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } CHOI;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000060) Output Mask Register                                     */

    struct {
      __IOM uint32_t CHOMASK0   : 1;            /* [0..0] Channel 0 Output Mask                                            */
      __IOM uint32_t CHOMASK1   : 1;            /* [1..1] Channel 1 Output Mask                                            */
      __IOM uint32_t CHOMASK2   : 1;            /* [2..2] Channel 2 Output Mask                                            */
      __IOM uint32_t CHOMASK3   : 1;            /* [3..3] Channel 3 Output Mask                                            */
      __IOM uint32_t CHOMASK4   : 1;            /* [4..4] Channel 4 Output Mask                                            */
      __IOM uint32_t CHOMASK5   : 1;            /* [5..5] Channel 5 Output Mask                                            */
      __IOM uint32_t CHOMASK6   : 1;            /* [6..6] Channel 6 Output Mask                                            */
      __IOM uint32_t CHOMASK7   : 1;            /* [7..7] Channel 7 Output Mask                                            */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } OMASK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000064) Function For Linked Channels Register                      */

    struct {
      __IOM uint32_t CHCM0      : 1;            /* [0..0] Channels Combine Mode For n=0                                      */
      __IOM uint32_t CCHO0      : 1;            /* [1..1] Complement Channel (n) Output for n=0                              */
      __IOM uint32_t DECMEN0    : 1;            /* [2..2] Dual Edge Capture Mode Enable For n=0                              */
      __IOM uint32_t DECSTS0    : 1;            /* [3..3] Dual Edge Capture Status For n=0                                   */
      __IOM uint32_t DTIEN0     : 1;            /* [4..4] Deadtime Insertion Enable For n=0                                  */
      __IOM uint32_t PWMSYNEN0  : 1;            /* [5..5] PWM Synchronization Enable For n=0                                 */
      __IOM uint32_t FCTRLEN0   : 1;            /* [6..6] Fault Control Enable For n=0                                       */
      __IOM uint32_t MCM0       : 1;            /* [7..7] Modified Combine Mode For n=0                                      */
      __IOM uint32_t CHCM1      : 1;            /* [8..8] Channels Combine Mode For n=2                                      */
      __IOM uint32_t CCHO1      : 1;            /* [9..9] Dual Edge Capture Mode Enable For n=2                              */
      __IOM uint32_t DECMEN1    : 1;            /* [10..10] Dual Edge Capture Status For n=2                                 */
      __IOM uint32_t DECSTS1    : 1;            /* [11..11] Dual Edge Capture Status For n=2                                 */
      __IOM uint32_t DTIEN1     : 1;            /* [12..12] Deadtime Insertion Enable For n=2                                */
      __IOM uint32_t PWMSYNEN1  : 1;            /* [13..13] PWM Synchronization Enable For n=2                               */
      __IOM uint32_t FCTRLEN1   : 1;            /* [14..14] Fault Control Enable For n=2                                     */
      __IOM uint32_t MCM1       : 1;            /* [15..15] Modified Combine Mode For n=2                                    */
      __IOM uint32_t CHCM2      : 1;            /* [16..16] Channels Combine Mode For n=4                                    */
      __IOM uint32_t CCHO2      : 1;            /* [17..17] Complement Channel (n) Output for n=4                            */
      __IOM uint32_t DECMEN2    : 1;            /* [18..18] Dual Edge Capture Mode Enable For n=4                            */
      __IOM uint32_t DECSTS2    : 1;            /* [19..19] Dual Edge Capture Status For n=4                                 */
      __IOM uint32_t DTIEN2     : 1;            /* [20..20] Deadtime Insertion Enable For n=4                                */
      __IOM uint32_t PWMSYNEN2  : 1;            /* [21..21] PWM Synchronization Enable For n=4                               */
      __IOM uint32_t FCTRLEN2   : 1;            /* [22..22] Fault Control Enable For n=4                                     */
      __IOM uint32_t MCM2       : 1;            /* [23..23] Modified Combine Mode For n=4                                    */
      __IOM uint32_t CHCM3      : 1;            /* [24..24] Channels Combine Mode For n=6                                    */
      __IOM uint32_t CCHO3      : 1;            /* [25..25] Complement Channel (n) Output for n=6                            */
      __IOM uint32_t DECMEN3    : 1;            /* [26..26] Dual Edge Capture Mode Enable For n=6                            */
      __IOM uint32_t DECSTS3    : 1;            /* [27..27] Dual Edge Capture Status For n=6                                 */
      __IOM uint32_t DTIEN3     : 1;            /* [28..28] Deadtime Insertion Enable For n=6                                */
      __IOM uint32_t PWMSYNEN3  : 1;            /* [29..29] PWM Synchronization Enable For n=6                               */
      __IOM uint32_t FCTRLEN3   : 1;            /* [30..30] Fault Control Enable For n=6                                     */
      __IOM uint32_t MCM3       : 1;            /* [31..31] Modified Combine Mode For n=6                                    */
    } bit;
  } FLCH;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000068) Deadtime Configure Register                                */

    struct {
      __IOM uint32_t DTVSEL     : 6;            /* [5..0] Deadtime Value Select                                              */
      __IOM uint32_t DPSCCFG    : 2;            /* [7..6] Deadtime Prescaler Factor Configure                                */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t EDTV       : 4;            /* [19..16] Extended Deadtime Value                                          */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } DCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000006C) External Trigger Register                                  */

    struct {
      __IOM uint32_t EXTTRGENCH2 : 1;           /* [0..0] Channel 2 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH3 : 1;           /* [1..1] Channel 3 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH4 : 1;           /* [2..2] Channel 4 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH5 : 1;           /* [3..3] Channel 5 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH0 : 1;           /* [4..4] Channel 0 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH1 : 1;           /* [5..5] Channel 1 External Trigger Generation Enable                       */
      __IOM uint32_t INITTRGEN  : 1;            /* [6..6] Initialization Trigger Generate Enable                             */
      __IOM  uint32_t CHTRGFLG   : 1;            /* [7..7] Channel Trigger Flag                                              */
      __IOM uint32_t EXTTRGENCH6 : 1;           /* [8..8] Channel 6 External Trigger Generation Enable                       */
      __IOM uint32_t EXTTRGENCH7 : 1;           /* [9..9] Channel 7 External Trigger Generation Enable                       */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } EXTTRG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000070) Channel Output Polarity Register                         */

    struct {
      __IOM uint32_t CHPOL0     : 1;            /* [0..0] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL1     : 1;            /* [1..1] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL2     : 1;            /* [2..2] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL3     : 1;            /* [3..3] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL4     : 1;            /* [4..4] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL5     : 1;            /* [5..5] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL6     : 1;            /* [6..6] Channel 0-7 Output Polarity                                        */
      __IOM uint32_t CHPOL7     : 1;            /* [7..7] Channel 0-7 Output Polarity                                        */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } CHPOL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000074) Fault module status register                              */

    struct {
      __IOM uint32_t FIDFLG0    : 1;            /* [0..0] Fault Inputs Detection Flag 0                                     */
      __IOM uint32_t FIDFLG1    : 1;            /* [1..1] Fault Inputs Detection Flag 1                                     */
      __IOM uint32_t FIDFLG2    : 1;            /* [2..2] Fault Inputs Detection Flag 2                                     */
      __IOM uint32_t FIDFLG3    : 1;            /* [3..3] Fault Inputs Detection Flag 3                                     */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t FICTRL     : 1;            /* [5..5] Fault Inputs Control                                              */
      __IOM uint32_t WPEN       : 1;            /* [6..6] Write Protection Enable                                            */
      __IM  uint32_t FCDFLG     : 1;            /* [7..7] Fault Condition Detection Flag                                     */
      __IM  uint32_t RESERVED1  : 24;
    } bit;
  } FMSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000078) Input Capture Filter Control Register                      */

    struct {
      __IOM uint32_t IFVSELCH0  : 4;            /* [3..0] Channel 0 Input Filter Value Select                                */
      __IOM uint32_t IFVSELCH1  : 4;            /* [7..4] Channel 1 Input Filter Value Select                                */
      __IOM uint32_t IFVSELCH2  : 4;            /* [11..8] Channel 2 Input Filter Value Select                               */
      __IOM uint32_t IFVSELCH3  : 4;            /* [15..12] Channel 3 Input Filter Value Select                              */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } ICFCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000007C) Fault Control Register                                     */

    struct {
      __IOM uint32_t FIEN0      : 1;            /* [0..0] Fault Input 0 Enable                                               */
      __IOM uint32_t FIEN1      : 1;            /* [1..1] Fault Input 1 Enable                                               */
      __IOM uint32_t FIEN2      : 1;            /* [2..2] Fault Input 2 Enable                                               */
      __IOM uint32_t FIEN3      : 1;            /* [3..3] Fault Input 3 Enable                                               */
      __IOM uint32_t FIFEN0     : 1;            /* [4..4] Fault Input Filter 0 Enable                                        */
      __IOM uint32_t FIFEN1     : 1;            /* [5..5] Fault Input Filter 1 Enable                                        */
      __IOM uint32_t FIFEN2     : 1;            /* [6..6] Fault Input Filter 2 Enable                                        */
      __IOM uint32_t FIFEN3     : 1;            /* [7..7] Fault Input Filter 3 Enable                                        */
      __IOM uint32_t FIFVSEL    : 4;            /* [11..8] Fault Input Filter Value Select                                   */
      __IM  uint32_t RESERVED0  : 3;
      __IOM uint32_t FEOSTS     : 1;            /* [15..15] Fault Event Output Status                                        */
      __IM  uint32_t RESERVED1  : 16;
    } bit;
  } FCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000080) Quadrature Decoder Control And Status Register             */

    struct {
      __IOM uint32_t QDMEN      : 1;            /* [0..0] Quadrature Decoder Mode Enable                                     */
      __IM  uint32_t TMRODSEL   : 1;            /* [1..1] Timer Overflow Direction Select                                    */
      __IM  uint32_t CNTDIR     : 1;            /* [2..2] CFGTMR Counter Direction                                             */
      __IOM uint32_t EMSEL      : 1;            /* [3..3] Encoding Mode Select                                               */
      __IOM uint32_t PBISPOL    : 1;            /* [4..4] Phase B Input Signal Polarity Select                               */
      __IOM uint32_t PAISPOL    : 1;            /* [5..5] Phase A Input Signal Polarity Select                               */
      __IOM uint32_t PBIFEN     : 1;            /* [6..6] Phase B Input Filter Value Enable                                  */
      __IOM uint32_t PAIFEN     : 1;            /* [7..7] Phase A Input Filter Value Enable                                  */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } QDCSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000084) Configure Register                                         */

    struct {
      __IOM uint32_t ROCFG      : 5;            /* [4..0] Reload Opportunities Configure                                     */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t DBG        : 2;            /* [7..6] Debug Mode                                                         */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t EGTIMBEN   : 1;            /* [9..9] External Global Time Base Enable                                   */
      __IOM uint32_t GTIMBSGEN  : 1;            /* [10..10] Global Time Base Signal Generation Enable                        */
      __IOM uint32_t INITTRGRP  : 1;            /* [11..11] Initialization Trigger on Reload Point                           */
      __IM  uint32_t RESERVED2  : 20;
    } bit;
  } CFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000088) Fault Input Polarity Select Register                       */

    struct {
      __IOM uint32_t FIPOLSEL0  : 1;            /* [0..0] Fault Input 0 Polarity Select                                      */
      __IOM uint32_t FIPOLSEL1  : 1;            /* [1..1] Fault Input 1 Polarity Select                                      */
      __IOM uint32_t FIPOLSEL2  : 1;            /* [2..2] Fault Input 2 Polarity Select                                      */
      __IOM uint32_t FIPOLSEL3  : 1;            /* [3..3] Fault Input 3 Polarity Select                                      */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } FIPOLSEL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000008C) Synchronization Configure Register                         */

    struct {
      __IOM uint32_t HWTRGD     : 1;            /* [0..0] Hardware Trigger Detect                                            */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t INITVSYN   : 1;            /* [2..2] CFGTMR_INITV Register Synchronization                                */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t ICTRLSYN   : 1;            /* [4..4] CFGTMR_ICTRL Register Synchronization                                */
      __IOM uint32_t SWOCTRLSYN : 1;            /* [5..5] CFGTMR_SWOCTRL Register Synchronization                              */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t SYNMSEL    : 1;            /* [7..7] Synchronization Mode Select                                        */
      __IOM uint32_t SWTAC      : 1;            /* [8..8] Software Trigger Activates CFGTMR Counter Register Synchronization   */
      __IOM uint32_t SWTAWRBUF  : 1;            /* [9..9] Software Trigger Activates CFGTMR_MOD,CFGTMR_HC,CFGTMR_INITV
                                                     and CFGTMR_CHnV (n=0...7) Register Synchronization                        */
      __IOM uint32_t SWTAOM     : 1;            /* [10..10] Software Trigger Activates CFGTMR_OMASK Register Synchronization   */
      __IOM uint32_t SWTAICTRL  : 1;            /* [11..11] Software Trigger Activates CFGTMR_ICTRL Register Synchronization   */
      __IOM uint32_t SWTASWO    : 1;            /* [12..12] Software Trigger Activates CFGTMR_SWOCTRL Register Synchronization */
      __IM  uint32_t RESERVED3  : 3;
      __IOM uint32_t HWTAC      : 1;            /* [16..16] Hardware Trigger Activates CFGTMR Counter Register Synchronization */
      __IOM uint32_t HWTAWRBUF  : 1;            /* [17..17] Hardware Trigger Activates CFGTMR_MOD,CFGTMR_HC,CFGTMR_INITV
                                                     and CFGTMR_CHnV (n=0...7) Register Synchronization                        */
      __IOM uint32_t HWTAOM     : 1;            /* [18..18] Hardware Trigger Activates CFGTMR_OMASK Register Synchronization   */
      __IOM uint32_t HWTAICTRL  : 1;            /* [19..19] Hardware Trigger Activates CFGTMR_ICTRL Register Synchronization   */
      __IOM uint32_t HWTASWO    : 1;            /* [20..20] Hardware Trigger Activates CFGTMR_SWOCTRL Register Synchronization */
      __IM  uint32_t RESERVED4  : 11;
    } bit;
  } SYNCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000090) Inverting Control Register                                 */

    struct {
      __IOM uint32_t CHPIEN0    : 1;            /* [0..0] Channels Pair 0 Inverting Enable                                   */
      __IOM uint32_t CHPIEN1    : 1;            /* [1..1] Channels Pair 1 Inverting Enable                                   */
      __IOM uint32_t CHPIEN2    : 1;            /* [2..2] Channels Pair 2 Inverting Enable                                   */
      __IOM uint32_t CHPIEN3    : 1;            /* [3..3] Channels Pair 3 Inverting Enable                                   */
      __IM  uint32_t RESERVED5  : 28;
    } bit;
  } ICTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000094) Software Output Control Register                         */

    struct {
      __IOM uint32_t CHSWOCTRLEN0 : 1;          /* [0..0] Channel 0 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN1 : 1;          /* [1..1] Channel 1 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN2 : 1;          /* [2..2] Channel 2 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN3 : 1;          /* [3..3] Channel 3 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN4 : 1;          /* [4..4] Channel 4 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN5 : 1;          /* [5..5] Channel 5 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN6 : 1;          /* [6..6] Channel 6 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLEN7 : 1;          /* [7..7] Channel 7 Software Output Control Enable                         */
      __IOM uint32_t CHSWOCTRLVSEL0 : 1;        /* [8..8] Channel 0 Software Output Control Value                          */
      __IOM uint32_t CHSWOCTRLVSEL1 : 1;        /* [9..9] Channel 1 Software Output Control Value                          */
      __IOM uint32_t CHSWOCTRLVSEL2 : 1;        /* [10..10] Channel 2 Software Output Control Value                        */
      __IOM uint32_t CHSWOCTRLVSEL3 : 1;        /* [11..11] Channel 3 Software Output Control Value                        */
      __IOM uint32_t CHSWOCTRLVSEL4 : 1;        /* [12..12] Channel 4 Software Output Control Value                        */
      __IOM uint32_t CHSWOCTRLVSEL5 : 1;        /* [13..13] Channel 5 Software Output Control Value                        */
      __IOM uint32_t CHSWOCTRLVSEL6 : 1;        /* [14..14] Channel 6 Software Output Control Value                        */
      __IOM uint32_t CHSWOCTRLVSEL7 : 1;        /* [15..15] Channel 7 Software Output Control Value                        */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } SWOCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000098) PWM Load Register                                        */

    struct {
      __IOM uint32_t CHMSEL0    : 1;            /* [0..0] Channel 0 Match Select                                           */
      __IOM uint32_t CHMSEL1    : 1;            /* [1..1] Channel 1 Match Select                                           */
      __IOM uint32_t CHMSEL2    : 1;            /* [2..2] Channel 2 Match Select                                           */
      __IOM uint32_t CHMSEL3    : 1;            /* [3..3] Channel 3 Match Select                                           */
      __IOM uint32_t CHMSEL4    : 1;            /* [4..4] Channel 4 Match Select                                           */
      __IOM uint32_t CHMSEL5    : 1;            /* [5..5] Channel 5 Match Select                                           */
      __IOM uint32_t CHMSEL6    : 1;            /* [6..6] Channel 6 Match Select                                           */
      __IOM uint32_t CHMSEL7    : 1;            /* [7..7] Channel 7 Match Select                                           */
      __IOM uint32_t HCREN      : 1;            /* [8..8] Half Cycle Reload Enable                                         */
      __IOM uint32_t LUVEN      : 1;            /* [9..9] Load Updated Values Enable                                       */
      __IOM uint32_t GLOKEN     : 1;            /* [10..10] Global Load OK Enable                                          */
      __OM  uint32_t GLOP       : 1;            /* [11..11] Global Load OK Present                                         */
      __IM  uint32_t RESERVED0  : 20;
    } bit;
  } PWMLD;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000009C) Half Cycle Register                                      */

    struct {
      __IOM uint32_t HCV        : 16;           /* [15..0] Half Cycle Value                                                */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } HC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A0) Pair x Deadtime Configure Register                       */

    struct {
      __IOM uint32_t DVSEL      : 6;            /* [5..0] Deadtime Value Select                                            */
      __IOM uint32_t PSCCFG     : 2;            /* [7..6] Deadtime Prescaler Factor Configure                              */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t EDTV       : 4;            /* [19..16] Extended Deadtime Value                                        */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } P0DCFG;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A8) Pair x Deadtime Configure Register                       */

    struct {
      __IOM uint32_t DVSEL      : 6;            /* [5..0] Deadtime Value Select                                            */
      __IOM uint32_t PSCCFG     : 2;            /* [7..6] Deadtime Prescaler Factor Configure                              */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t EDTV       : 4;            /* [19..16] Extended Deadtime Value                                        */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } P1DCFG;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B0) Pair x Deadtime Configure Register                       */

    struct {
      __IOM uint32_t DVSEL      : 6;            /* [5..0] Deadtime Value Select                                            */
      __IOM uint32_t PSCCFG     : 2;            /* [7..6] Deadtime Prescaler Factor Configure                              */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t EDTV       : 4;            /* [19..16] Extended Deadtime Value                                        */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } P2DCFG;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B8) Pair x Deadtime Configure Register                       */

    struct {
      __IOM uint32_t DVSEL      : 6;            /* [5..0] Deadtime Value Select                                            */
      __IOM uint32_t PSCCFG     : 2;            /* [7..6] Deadtime Prescaler Factor Configure                              */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t EDTV       : 4;            /* [19..16] Extended Deadtime Value                                        */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } P3DCFG;

  __IM  uint32_t  RESERVED3[81];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000200) Mirror of Modulo Value Register                          */

    struct {
      __IM  uint32_t RESERVED0  : 11;
      __IOM uint32_t MFV        : 5;            /* [15..11] Modulo Fractional Value                                        */
      __IOM uint32_t MMIV       : 16;           /* [31..16] Mirror of Modulo Integer Value                                 */
    } bit;
  } MMV;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000204) Mirror of Channel (n) Match Value Register               */

    struct {
      __IM  uint32_t RESERVED0  : 11;
      __IOM uint32_t MFCHV      : 5;            /* [15..11] Channel (n) Match Fractional Value                             */
      __IOM uint32_t MMICHV     : 16;           /* [31..16] Mirror of the Channel (n) Match Integer Value                  */
    } bit;
  } MCHM[8];

} CFGTMR_T;                                   /* Size = 548 (0x224)                                                            */



/* =========================================================================================================================== */
/* ================                                           ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog-to-Digital Converter (ADC)
  */
/** ADC - Size of Registers Arrays */
#define ADC_DATARESULT_COUNT                       16U
#define ADC_CSTS1_COUNT                            16U
#define ADC_DATA_COUNT                             16U
#define ADC_ACSTS1_COUNT                           24U
#define ADC_ADATA_COUNT                            24U
#define ADC_COMPVAL_COUNT                          2U

typedef struct {                                /*  ADC Structure  (@ 0x4003B000)ADC0 (@ 0x40027000)ADC1                     */
  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control and Status Register 1x                             */

    struct {
      __IOM uint32_t ICHSEL     : 6;            /* [5..0] Input Channel Select                                               */
      __IOM uint32_t CCIEN      : 1;            /* [6..6] Conversion Complete Interrupt Enable                               */
      __IM  uint32_t CCFLG      : 1;            /* [7..7] Input Clock Source Select                                          */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } CSTS1[ADC_CSTS1_COUNT];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Configure Register 1                                       */

    struct {
      __IOM uint32_t ICLKSSEL   : 2;            /* [1..0] Input Clock Source Select                                          */
      __IOM uint32_t CMODSEL    : 2;            /* [3..2] Conversion Mode Select                                             */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t CLKDIVCFG  : 2;            /* [6..5] Clock Divider Factor Configure                                     */
      __IM  uint32_t RESERVED1  : 1;
      __OM  uint32_t LTRGCLR    : 1;            /* [8..8] Latch Triggers Clear                                               */
      __IM  uint32_t RESERVED2  : 23;
    } bit;
  } CFG1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000044) Configure Register 2                                       */

    struct {
      __IOM uint32_t SMPTCFG    : 8;            /* [7..0] Sample Time Configure                                              */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } CFG2;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000048) Data Result Registers x                                    */

    struct {
      __IM  uint32_t DATA       : 12;           /* [11..0] Conversion Data                                                   */
      __IM  uint32_t RESERVED0  : 20;
    } bit;
  } DATA[ADC_DATARESULT_COUNT];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000088) Compare Value Registers x                                  */

    struct {
      __IOM uint32_t COMPVAL    : 16;           /* [15..0] Compare Value                                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } COMPVAL[ADC_COMPVAL_COUNT];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000090) Status and Control Register 2                              */

    struct {
      __IOM uint32_t VREFSEL    : 2;            /* [1..0] Voltage Reference Source Select                                    */
      __IOM uint32_t DMAEN      : 1;            /* [2..2] DMA Mode Enable                                                    */
      __IOM uint32_t RCOMPEN    : 1;            /* [3..3] Range Compare Function Enable                                      */
      __IOM uint32_t GTCOMPEN   : 1;            /* [4..4] Greater Than Compare Function Enable                               */
      __IOM uint32_t COMPEN     : 1;            /* [5..5] Compare Function Enable                                            */
      __IOM uint32_t CTRGSEL    : 1;            /* [6..6] Software/Hardware Conversion Trigger Select                        */
      __IM  uint32_t CFLAG      : 1;            /* [7..7] Conversion Flag                                                    */
      __IM  uint32_t RESERVED0  : 5;
      __IM  uint32_t TRGNUM     : 2;            /* [14..13] Trigger Number                                                   */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t TRGSTS     : 4;            /* [19..16] Trigger Status                                                   */
      __IM  uint32_t RESERVED2  : 4;
      __IM  uint32_t TRGEFLG    : 4;            /* [27..24] Trigger Error Occur Flag                                         */
      __IM  uint32_t RESERVED3  : 4;
    } bit;
  } CSTS2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000094) Status and Control Register 3                              */

    struct {
      __IOM uint32_t HAVGCFG    : 2;            /* [1..0] Hardware Averaged Samples Configure                                */
      __IOM uint32_t HAVGEN     : 1;            /* [2..2] Hardware Average Function Enable                                   */
      __IOM uint32_t CONTCEN    : 1;            /* [3..3] Continuous Conversion Mode Enable                                  */
      __IM  uint32_t RESERVED0  : 3;
      __IOM uint32_t CAL        : 1;            /* [7..7] Calibration                                                        */
      __IM  uint32_t RESERVED1  : 24;
    } bit;
  } CSTS3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000098) Base Offset Error Correction Register                      */

    struct {
      __IOM uint32_t BOECVAL    : 8;            /* [7..0] Base Offset Error Correction Value                                 */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } BOEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000009C) Offset Error Correction Register                           */

    struct {
      __IOM uint32_t OECVAL     : 16;           /* [15..0] Offset Error Correction Value                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } OEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A0) User defined Offset Error Correction Value Register        */

    struct {
      __IOM uint32_t UOECVAL    : 8;            /* [7..0] User Defined Offset Error Correction Value                         */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } UOEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A4) X Offset Error Correction Register                         */

    struct {
      __IOM uint32_t XOECVAL    : 6;            /* [5..0] X Offset Error Correction Value                                    */
      __IM  uint32_t RESERVED0  : 26;
    } bit;
  } XOEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A8) Y Offset Error Correction Register                         */

    struct {
      __IOM uint32_t YOECVAL    : 8;            /* [7..0] Y Offset Error Correction Value                                    */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } YOEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000AC) ADC Gain Error Adjustment Factor Register                  */

    struct {
      __IOM uint32_t GEAF       : 11;           /* [10..0] Gain Error Adjustment Factor                                      */
      __IM  uint32_t RESERVED0  : 21;
    } bit;
  } GEAF;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B0) User defined Gain Error Correction Register                */

    struct {
      __IOM uint32_t UGECVAL    : 10;           /* [9..0] User defined Gain Error Correction Value                           */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } UGEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B4) General Calibration Register S                             */

    struct {
      __IOM uint32_t CALVAL     : 7;            /* [6..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 25;
    } bit;
  } GCALS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B8) Plus-Side General Calibration Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t CALVAL     : 10;           /* [9..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } PSGCAL3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000BC) Plus-Side General Calibration Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t CALVAL     : 10;           /* [9..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } PSGCAL2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C0) Plus-Side General Calibration Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t CALVAL     : 10;           /* [9..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } PSGCAL1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C4) Plus-Side General Calibration Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t CALVAL     : 10;           /* [9..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 22;
    } bit;
  } PSGCAL0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C8) Plus-Side General Calibration Value Register
                                                                    X                                                          */

    struct {
      __IOM uint32_t CALVAL     : 7;            /* [6..0] Calibration Value                                                  */
      __IM  uint32_t RESERVED0  : 25;
    } bit;
  } PSGCALX;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000CC) Plus-Side General Calibration Value Register
                                                                    9                                                          */

    struct {
      __IOM uint32_t CALVAL     : 7;            /* [6..0] CAL9                                                               */
      __IM  uint32_t RESERVED0  : 25;
    } bit;
  } PSGCAL9;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000D0) General Calibration Offset Value Register S                */

    struct {
      __IOM uint32_t COCVAL     : 4;            /* [3..0] Capacitor Offset Correction Value                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } GCALOS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000D4) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 4;            /* [3..0] Capacitor Offset Correction Value                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } PSGCALOV3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000D8) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 4;            /* [3..0] Capacitor Offset Correction Value                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } PSGCALOV2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000DC) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 4;            /* [3..0] Capacitor Offset Correction Value                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } PSGCALOV1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E0) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 4;            /* [3..0] Capacitor Offset Correction Value                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } PSGCALOV0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E4) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 12;           /* [11..0] Capacitor Offset Correction Value                                 */
      __IM  uint32_t RESERVED0  : 20;
    } bit;
  } PSGCALOVX;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E8) Plus-Side General Calibration Offset Value Register
                                                                    x                                                          */

    struct {
      __IOM uint32_t COCVAL     : 12;           /* [11..0] Capacitor Offset Correction Value                                 */
      __IM  uint32_t RESERVED0  : 20;
    } bit;
  } PSGCALOV9;

  __IM  uint32_t  RESERVED0[7];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000108) Control and Status Register 1x                             */

    struct {
      __IOM uint32_t ICHSEL     : 6;            /* [5..0] Input Channel Select                                               */
      __IOM uint32_t CCIEN      : 1;            /* [6..6] Conversion Complete Interrupt Enable                               */
      __IM  uint32_t CCFLG      : 1;            /* [7..7] Input Clock Source Select                                          */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } ACSTS1[ADC_ACSTS1_COUNT];
  __IM  uint32_t  RESERVED1[8];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000188) Plus-Side General Calibration Offset Value Register x      */

    struct {
      __IOM uint32_t DATA       : 12;           /* [11..0] Data result                                 */
      __IM  uint32_t RESERVED0  : 20;
    } bit;
  } ADATA[ADC_ADATA_COUNT];

} ADC_T;                                    /*                                                          */


/* =========================================================================================================================== */
/* ================                                          LPSPI                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief The LPSPI Memory Map/Register Definition can be found here. (LPSPI)
  */

typedef struct {                                /*  LPSPI Structure
                                                   (@ 0x4002C000)LPSPI0 (@ 0x4002D000)LPSPI1 (@ 0x4002E000)LPSPI2            */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Number                                                    */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t TXFSSET    : 8;            /* [7..0] Transmit FIFO Size Set                                             */
      __IM  uint32_t RXFSSET    : 8;            /* [15..8] Receive FIFO Size Set                                             */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } PARA;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Control Register                                           */

    struct {
      __IOM uint32_t MEN        : 1;            /* [0..0] Module Enable                                                      */
      __IOM uint32_t SWRST      : 1;            /* [1..1] Software Reset                                                     */
      __IOM uint32_t DOZEDIS    : 1;            /* [2..2] Disable LPSPI in Doze Mode                                         */
      __IOM uint32_t DBGEN      : 1;            /* [3..3] Enable LPSPI in Debug Mode                                         */
      __IM  uint32_t RESERVED0  : 4;
      __OM  uint32_t TXFRST     : 1;            /* [8..8] Transmit FIFO Reset                                                */
      __OM  uint32_t RXFRST     : 1;            /* [9..9] Receive FIFO Reset                                                 */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } CTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Status Register                                            */

    struct {
      __IM  uint32_t TXDATAFLG  : 1;            /* [0..0] Transmit Data Flag                                                 */
      __IM  uint32_t RXDATAFLG  : 1;            /* [1..1] Receive Data Flag                                                  */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t RXWCFLG    : 1;            /* [8..8] Received Word Complete Flag                                        */
      __IOM uint32_t FTXCFLG    : 1;            /* [9..9] Frame Complete Flag                                                */
      __IOM uint32_t TXCFLG     : 1;            /* [10..10] Transfer Complete Flag                                           */
      __IOM uint32_t TXEFLG     : 1;            /* [11..11] Transmit Error Flag                                              */
      __IOM uint32_t RXEFLG     : 1;            /* [12..12] Receive Error Flag                                               */
      __IOM uint32_t RXMFLG     : 1;            /* [13..13] Receive Data Match Flag                                          */
      __IM  uint32_t RESERVED1  : 10;
      __IM  uint32_t BSYFLG     : 1;            /* [24..24] LPSPI Busy Flag                                                  */
      __IM  uint32_t RESERVED2  : 7;
    } bit;
  } STS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Interrupt Enable Register                                  */

    struct {
      __IOM uint32_t TXIEN      : 1;            /* [0..0] Transmit Data Interrupt Enable                                     */
      __IOM uint32_t RXIEN      : 1;            /* [1..1] Receive Data Interrupt Enable                                      */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t RXWCIEN    : 1;            /* [8..8] Receive Word Complete Interrupt Enable                             */
      __IOM uint32_t FTCIEN     : 1;            /* [9..9] Frame Transfer Complete Interrupt Enable                           */
      __IOM uint32_t TXCIEN     : 1;            /* [10..10] Transfer Complete Interrupt Enable                               */
      __IOM uint32_t TXEIEN     : 1;            /* [11..11] Transmit Error Interrupt Enable                                  */
      __IOM uint32_t RXEIEN     : 1;            /* [12..12] Receive Error Interrupt Enable                                   */
      __IOM uint32_t RXMIEN     : 1;            /* [13..13] Receive Data Match Interrupt Enable                              */
      __IM  uint32_t RESERVED1  : 18;
    } bit;
  } IEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) DMA Enable Register                                        */

    struct {
      __IOM uint32_t TXDMAEN    : 1;            /* [0..0] Transmit Data DMA Enable                                           */
      __IOM uint32_t RXDMAEN    : 1;            /* [1..1] Receive Data DMA Enable                                            */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } DMAEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Configure Register 0                                       */

    struct {
      __IOM uint32_t HREQEN     : 1;            /* [0..0] Host Request Enable                                                */
      __IOM uint32_t HREQPCFG   : 1;            /* [1..1] Host Request Polarity Configure                                    */
      __IOM uint32_t HREQISEL   : 1;            /* [2..2] Host Request Input Select                                          */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t CIRFEN     : 1;            /* [8..8] Circular FIFO Enable                                               */
      __IOM uint32_t RXMOEN     : 1;            /* [9..9] Receive Data Match Only Enable                                     */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } CFG0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) Configure Register 1                                       */

    struct {
      __IOM uint32_t MSCFG      : 1;            /* [0..0] Master/Slave Mode Configure                                        */
      __IOM uint32_t IDSPCFG    : 1;            /* [1..1] Input Data Sample Point Configure                                  */
      __IOM uint32_t APCSEN     : 1;            /* [2..2] Automatic PCS Enable                                               */
      __IOM uint32_t DISTXS     : 1;            /* [3..3] Disable Transmit Stop                                              */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t PCSPPCFG   : 4;            /* [11..8] Peripheral Chip Select Pin Polarity Configure                     */
      __IM  uint32_t RESERVED1  : 4;
      __IOM uint32_t MCFG       : 3;            /* [18..16] Match Configure                                                  */
      __IM  uint32_t RESERVED2  : 5;
      __IOM uint32_t IOPCFG     : 2;            /* [25..24] Input/Output Pin Configure                                       */
      __IOM uint32_t ODCFG      : 1;            /* [26..26] Output Data Configure                                            */
      __IOM uint32_t PCSELCFG   : 1;            /* [27..27] Peripheral Chip Select Configure                                 */
      __IM  uint32_t RESERVED3  : 4;
    } bit;
  } CFG1;
  __IM  uint32_t  RESERVED1[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000030) Data Match Register 0                                      */

    struct {
      __IOM uint32_t COMPVAL0   : 32;           /* [31..0] Match 0 Value                                                     */
    } bit;
  } DATAM0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000034) Data Match Register 1                                      */

    struct {
      __IOM uint32_t COMPVAL1   : 32;           /* [31..0] Compare Match 1 Value                                             */
    } bit;
  } DATAM1;
  __IM  uint32_t  RESERVED2[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Clock Configure Register                                   */

    struct {
      __IOM uint32_t SCKDRCFG   : 8;            /* [7..0] SCK Divide Ratio Configure                                         */
      __IOM uint32_t TXDCFG     : 8;            /* [15..8] Transfers Delay Configure                                         */
      __IOM uint32_t PSDCFG     : 8;            /* [23..16] PCS-to-SCK Delay Configure                                       */
      __IOM uint32_t SPDCFG     : 8;            /* [31..24] SCK-to-PCS Delay Configure                                       */
    } bit;
  } CLKCFG;
  __IM  uint32_t  RESERVED3[5];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000058) FIFO Control Register                                      */

    struct {
      __IOM uint32_t TXFW       : 2;            /* [1..0] Transmit FIFO Watermark                                            */
      __IM  uint32_t RESERVED0  : 14;
      __IOM uint32_t RXFW       : 2;            /* [17..16] Receive FIFO Watermark                                           */
      __IM  uint32_t RESERVED1  : 14;
    } bit;
  } FCTRL;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000005C) FIFO Status Register                                       */

    struct {
      __IM  uint32_t TXFCNT     : 3;            /* [2..0] Transmit FIFO Count                                                */
      __IM  uint32_t RESERVED0  : 13;
      __IM  uint32_t RXFCNT     : 3;            /* [18..16] Receive FIFO Count                                               */
      __IM  uint32_t RESERVED1  : 13;
    } bit;
  } FSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000060) Transmit Command Register                                  */

    struct {
      __IOM uint32_t FSCFG      : 12;           /* [11..0] Frame Size Configure                                              */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t TXWIDCFG   : 2;            /* [17..16] Transfer Width Configure                                         */
      __IOM uint32_t TXDATAMASK : 1;            /* [18..18] Transmit Data Mask                                               */
      __IOM uint32_t RXDATAMASK : 1;            /* [19..19] Receive Data Mask                                                */
      __IOM uint32_t CTXCMDW    : 1;            /* [20..20] Continuing Transfer Command Word                                 */
      __IOM uint32_t CTXEN      : 1;            /* [21..21] Continuous Transfer Enable                                       */
      __IOM uint32_t BSEN       : 1;            /* [22..22] Byte Swap Enable                                                 */
      __IOM uint32_t DATAFSEL   : 1;            /* [23..23] Data First Select                                                */
      __IOM uint32_t PCSEL      : 2;            /* [25..24] Peripheral Chip Select                                           */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t PVALCFG    : 3;            /* [29..27] Prescaler Value Configure                                        */
      __IOM uint32_t CLKPHA     : 1;            /* [30..30] Clock Phase Configure                                            */
      __IOM uint32_t CLKPOL     : 1;            /* [31..31] Clock Polarity Configure                                         */
    } bit;
  } TXCMD;

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000064) Transmit Data Register                                     */

    struct {
      __OM  uint32_t TXDATA     : 32;           /* [31..0] Transmit Data                                                     */
    } bit;
  } TXDATA;
  __IM  uint32_t  RESERVED4[2];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000070) Receive Status Register                                    */

    struct {
      __IM  uint32_t FDATAWCFG  : 1;            /* [0..0] First Data Word Configure                                          */
      __IM  uint32_t RXFE       : 1;            /* [1..1] Receive FIFO Empty                                                 */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } RXSTS;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000074) Receive Data Register                                      */

    struct {
      __IM  uint32_t RXDATA     : 32;           /* [31..0] Receive Data                                                      */
    } bit;
  } RXDATA;
} LPSPI_T;                                  /* Size = 120 (0x78)                                                             */



/* =========================================================================================================================== */
/* ================                                           PDU                                            ================ */
/* =========================================================================================================================== */

/** PDU - Size of Registers Arrays */
#define PDU_CH_COUNT                            3u
#define PDU_CH_DELAY_COUNT                      8u
#define PDU_PODLY_COUNT                         1u

/**
  * @brief Programmable Delay Unit (PDU)
  */

typedef struct {                                /*  PDU Structure  (@ 0x40036000)PDU0 (@ 0x40031000)PDU1                     */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control and Status register                                */

    struct {
      __IOM uint32_t LDSUS      : 1;            /* [0..0] Load Success                                                       */
      __IOM uint32_t CMODEN     : 1;            /* [1..1] PDU in Continuous Mode Enable                                      */
      __IOM uint32_t MULPSCCFG  : 2;            /* [3..2] Multiplication Factor Prescaler Configure                          */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t IEN        : 1;            /* [5..5] Interrupt Enable                                                   */
      __IOM uint32_t IFLG       : 1;            /* [6..6] Interrupt Flag                                                     */
      __IOM uint32_t PDUEN      : 1;            /* [7..7] PDU Enable                                                         */
      __IOM uint32_t TRGINTSEL  : 4;            /* [11..8] Trigger Input Source Select                                       */
      __IOM uint32_t PSCDIVCFG  : 3;            /* [14..12] Prescaler Divider Configure                                      */
      __IOM uint32_t DMAEN      : 1;            /* [15..15] DMA Enable                                                       */
      __OM  uint32_t SWTRGSEL   : 1;            /* [16..16] Software Trigger Select                                          */
      __IOM uint32_t SEQEIEN    : 1;            /* [17..17] Sequence Error Interrupt Enable                                  */
      __IOM uint32_t LDMODSEL   : 2;            /* [19..18] Load Mode Select                                                 */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } CSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Counter Period register                                    */

    struct {
      __IOM uint32_t CNTPRD     : 16;           /* [15..0] Counter Period                                                    */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CNTPRD;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000008) Counter Contains Current Value register                    */

    struct {
      __IM  uint32_t CNTCUR     : 16;           /* [15..0] Counter Contains Current Value                                    */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CNTCUR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Scheduling Interrupt Delay Value register                  */

    struct {
      __IOM uint32_t SINTDLY    : 16;           /* [15..0] Scheduling Interrupt Delay Value                                  */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } SINTDLY;

  struct {
    union {
      __IOM uint32_t reg;                         /* (@ 0x00000010) Channel n Control register 1                             */

      struct {
        __IOM uint32_t CHPTOEN    : 8;            /* [7..0] Channel Pre-Trigger Output Enable                                */
        __IOM uint32_t CHPTOSEL   : 8;            /* [15..8] Channel Pre-Trigger Output Select                               */
        __IOM uint32_t PTBBEN     : 8;            /* [23..16] Pre-Trigger Back-to-Back Operation Enable                      */
        __IM  uint32_t RESERVED0  : 8;
      } bit;
    } CTRL1;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00000014) Channel n Status register                                */

      struct {
        __IOM uint32_t CHPTEFLG   : 8;            /* [7..0] Channel Pre-trigger Sequence Error Flags                         */
        __IM  uint32_t RESERVED0  : 8;
        __IOM uint32_t CHFLG      : 8;            /* [23..16] Channel Flags                                                  */
        __IM  uint32_t RESERVED1  : 8;
      } bit;
    } STS;

    union {
      __IOM uint32_t reg;                         /* (@ 0x00000018) Channel n Delay 0 register                               */

      struct {
        __IOM uint32_t CHPTDLY    : 16;           /* [15..0] Channel Pre-trigger Delay Value                                 */
        __IM  uint32_t RESERVED0  : 16;
      } bit;
    } D[PDU_CH_DELAY_COUNT];
  } CH[PDU_CH_COUNT];

  __IM  uint32_t  RESERVED[66];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000190) Pulse-Out Enable register                                  */

    struct {
      __IOM uint32_t POEN       : 8;            /* [7..0] Pulse Output Enble                                                 */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } POEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000194) Pulse-Out Delay register                                   */

    struct {
      __IOM uint32_t PODLY2     : 16;           /* [15..0] Pulse Output Delay 2 Value                                        */
      __IOM uint32_t PODLY1     : 16;           /* [31..16] Pulse Output Delay 1 Value                                       */
    } bit;
  } PODLY[PDU_PODLY_COUNT];
} PDU_T;                                    /* Size = 408 (0x198)                                                            */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Cyclic Redundancy Check (CRC)
  */

typedef struct {                                /* (@ 0x40032000) CRC Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Data register                                              */

    struct {
      __IOM uint32_t LBLB       : 8;            /* [7..0] CRC Low 16Bit Lower Byte                                           */
      __IOM uint32_t LBHB       : 8;            /* [15..8] Low 16 Bit Higher Byte                                            */
      __IOM uint32_t HBLB       : 8;            /* [23..16] High 16Bit Lower Byte                                            */
      __IOM uint32_t HBUB       : 8;            /* [31..24] High 16 Bit Higher Byte                                          */
    } bit;
  } DATA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Polynomial register                                        */

    struct {
      __IOM uint32_t LOWPOL     : 16;           /* [15..0] Low 16 Bit Polynominal                                            */
      __IOM uint32_t HIGHPOL    : 16;           /* [31..16] High 16 Bit Polynominal                                          */
    } bit;
  } POLY;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Control register                                           */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t WIDCRCP    : 1;            /* [24..24] Width of CRC Protocol                                            */
      __IOM uint32_t WASVAL     : 1;            /* [25..25] Write CRC Data Register As Seed Value                            */
      __IOM uint32_t XOR_RDATA  : 1;            /* [26..26] Invert/Complement Read of CRC Data Register                      */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TTRSEL     : 2;            /* [29..28] Type of Transpose For Read Select                                */
      __IOM uint32_t TTWSEL     : 2;            /* [31..30] Type of Transpose For Writes Select                              */
    } bit;
  } CTRL;
} CRC_T;                                     /* Size = 12 (0xc)                                                              */



/* =========================================================================================================================== */
/* ================                                          LPITMR                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Low Power Periodic Interrupt Timer (LPITMR)
  */

/** LPITMR - Size of Registers Arrays */
#define LPITMR_TMR_COUNT                           4U

/** LPITMR - Register Layout Typedef */
typedef struct {                                /*  (@ 0x40037000) LPITMR Structure                                          */
  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Support Number                                            */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;
  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t NUMTMRCH   : 8;            /* [7..0] Number of Timer Channels                                           */
      __IM  uint32_t NUMETRG    : 8;            /* [15..8] Number of External Triggers                                       */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } PARA;
  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Module Control Register                                    */

    struct {
      __IOM uint32_t PCLKTMREN  : 1;            /* [0..0] Peripheral Clock Timer Enable                                      */
      __IOM uint32_t SWRET      : 1;            /* [1..1] Software Reset                                                     */
      __IOM uint32_t DOZEEN     : 1;            /* [2..2] Enable timer channels run in doze mode                             */
      __IOM uint32_t DBGEN      : 1;            /* [3..3] Enable timer channels run in Debug Mode                            */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } MCTRL;
  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Module Status Register                                     */

    struct {
      __IOM uint32_t TITFLG0    : 1;            /* [0..0] Channel 0 Timer Interrupt Timeout Flag                             */
      __IOM uint32_t TITFLG1    : 1;            /* [1..1] Channel 1 Timer Interrupt Timeout Flag                             */
      __IOM uint32_t TITFLG2    : 1;            /* [2..2] Channel 2 Timer Interrupt Timeout Flag                             */
      __IOM uint32_t TITFLG3    : 1;            /* [3..3] Channel 3 Timer Interrupt Timeout Flag                             */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } MSTS;
  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Module Interrupt Enable Register                           */

    struct {
      __IOM uint32_t TIEN0      : 1;            /* [0..0] Channel 0 Timer Interrupt Enable                                   */
      __IOM uint32_t TIEN1      : 1;            /* [1..1] Channel 1 Timer Interrupt Enable                                   */
      __IOM uint32_t TIEN2      : 1;            /* [2..2] Channel 2 Timer Interrupt Enable                                   */
      __IOM uint32_t TIEN3      : 1;            /* [3..3] Channel 3 Timer Interrupt Enable                                   */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } MIEN;
  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Set Timer Enable Register                                  */

    struct {
      __IOM uint32_t TENCH0     : 1;            /* [0..0] Timer Channel 0 Enable                                             */
      __IOM uint32_t TENCH1     : 1;            /* [1..1] Timer Channel 1 Enable                                             */
      __IOM uint32_t TENCH2     : 1;            /* [2..2] Timer Channel 2 Enable                                             */
      __IOM uint32_t TENCH3     : 1;            /* [3..3] Timer Channel 3 Enable                                             */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } STMREN;
  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Clear Timer Enable Register                                */

    struct {
      __OM  uint32_t CLRTMREN0  : 1;            /* [0..0] Clear Timer Channel 0 Enable                                       */
      __OM  uint32_t CLRTMREN1  : 1;            /* [1..1] Clear Timer Channel 1 Enable                                       */
      __OM  uint32_t CLRTMREN2  : 1;            /* [2..2] Clear Timer Channel 2 Enable                                       */
      __OM  uint32_t CLRTMREN3  : 1;            /* [3..3] Clear Timer Channel 3 Enable                                       */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } CLRTMREN;

   uint8_t RESERVED_0[4];

  struct {                                         /* offset: 0x20, array step: 0x10 */
      union {
        __IOM uint32_t reg;                         /* (@ 0x00000020) Timer Value Register 0                                     */

        struct {
          __IOM uint32_t TMRV       : 32;           /* [31..0] Timer Value                                                       */
        } bit;
      } TMRV;

      union {
        __IM  uint32_t reg;                         /* (@ 0x00000024) Current Timer Value 0                                      */

        struct {
          __IM  uint32_t CTMRV      : 32;           /* [31..0] Current Timer Value                                               */
        } bit;
      } CTMRV;

      union {
        __IOM uint32_t reg;                         /* (@ 0x00000028) Timer Control Register 0                                   */

        struct {
          __IOM uint32_t TMREN      : 1;            /* [0..0] Timer Channel Enable                                               */
          __IOM uint32_t CHAINEN    : 1;            /* [1..1] Channel Chain Enable                                               */
          __IOM uint32_t TMROMCFG   : 2;            /* [3..2] Timer Operation Mode Configure                                     */
          __IM  uint32_t RESERVED0  : 12;
          __IOM uint32_t TMRDCTRL   : 1;            /* [16..16] Timer Decrement Control                                          */
          __IOM uint32_t TMRTOSCTRL : 1;            /* [17..17] Timer Timeout Stop Control                                       */
          __IOM uint32_t TMRRCTRL   : 1;            /* [18..18] Timer Reload Control                                             */
          __IM  uint32_t RESERVED1  : 4;
          __IOM uint32_t TRGSSEL    : 1;            /* [23..23] Trigger Source Select                                            */
          __IOM uint32_t TRGSEL     : 4;            /* [27..24] Trigger Select                                                   */
          __IM  uint32_t RESERVED2  : 4;
        } bit;
      } TMRCTRL;
      uint8_t RESERVED_0[4];
  } TMR[LPITMR_TMR_COUNT];

} LPITMR_T;


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real-time clock (RTC)
  */

typedef struct {                                /* (@ 0x4003D000) RTC Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) RTC Time Seconds Register                                  */

    struct {
      __IOM uint32_t TIMSEC     : 32;           /* [31..0] Time Seconds bit                                                  */
    } bit;
  } TIMSEC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) RTC Time Prescaler Register                                */

    struct {
      __IOM uint32_t TIMPSC     : 16;           /* [15..0] Time Prescaler                                                    */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } TIMPSC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) RTC Time Alarm Register                                    */

    struct {
      __IOM uint32_t TIMALR     : 32;           /* [31..0] Time Alarm bit                                                    */
    } bit;
  } TIMALR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) RTC Time Compensation Register                             */

    struct {
      __IOM uint32_t TIMCCFG    : 8;            /* [7..0] Time Compensation Configure                                        */
      __IOM uint32_t CICFG      : 8;            /* [15..8] Compensation Interval Configure                                   */
      __IM  uint32_t TIMCVSET   : 8;            /* [23..16] Time Compensation Value set                                      */
      __IM  uint32_t CICNT      : 8;            /* [31..24] Compensation Interval Counter                                    */
    } bit;
  } TIMC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) RTC Control Register                                       */

    struct {
      __IOM uint32_t SWREN      : 1;            /* [0..0] Software Reset Enable                                              */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t SACCCTRL   : 1;            /* [2..2] Supervisor Access Control                                          */
      __IOM uint32_t UMEN       : 1;            /* [3..3] Update Mode Enable                                                 */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t CLKPOSEL   : 1;            /* [5..5] Clock Pin Output Select                                            */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t LPOCSEL    : 1;            /* [7..7] LPO Clock Sclect                                                   */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t CLKOOUTEN  : 1;            /* [9..9] Clock Output Enable                                                */
      __IM  uint32_t RESERVED4  : 14;
      __IOM uint32_t CLKPEN     : 1;            /* [24..24] Clock Pin Enable                                                 */
      __IM  uint32_t RESERVED5  : 7;
    } bit;
  } CTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) RTC Status Register                                        */

    struct {
      __IM  uint32_t TIMINVFLG  : 1;            /* [0..0] Time Invalid Flag                                                  */
      __IM  uint32_t TIMOVRFLG  : 1;            /* [1..1] Time Overflow Flag                                                 */
      __IM  uint32_t TIMALRFLG  : 1;            /* [2..2] Time Alarm Flag                                                    */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TIMCNTEN   : 1;            /* [4..4] Time Counter Enable                                                */
      __IM  uint32_t RESERVED1  : 27;
    } bit;
  } STS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) RTC Lock Register                                          */

    struct {
      __IM  uint32_t RESERVED0  : 3;
      __IOM uint32_t TIMCPRO    : 1;            /* [3..3] Time Compensation Protect                                          */
      __IOM uint32_t CTRLPRO    : 1;            /* [4..4] Control Register Protect                                           */
      __IOM uint32_t STSPRO     : 1;            /* [5..5] Status Register Protect                                            */
      __IOM uint32_t LOCKPRO    : 1;            /* [6..6] Lock Register Protect                                              */
      __IM  uint32_t RESERVED1  : 25;
    } bit;
  } LOCK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) RTC Interrupt Enable Register                              */

    struct {
      __IOM uint32_t INVIEN     : 1;            /* [0..0] Invalid Interrupt Enable                                           */
      __IOM uint32_t OVRIEN     : 1;            /* [1..1] Overflow Interrupt Enable                                          */
      __IOM uint32_t ALRIEN     : 1;            /* [2..2] Alarm Interrupt Enable                                             */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t SECIEN     : 1;            /* [4..4] Second Interrupt Enable                                            */
      __IM  uint32_t RESERVED1  : 11;
      __IOM uint32_t TSECICFG   : 3;            /* [18..16] Timer Seconds Interrupt Frequency Configure                      */
      __IM  uint32_t RESERVED2  : 13;
    } bit;
  } IEN;
} RTC_T;                                     /* Size = 32 (0x20)                                                             */



/* =========================================================================================================================== */
/* ================                                           LPTMR                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Low Power Timer (LPTMR)
  */

typedef struct {                                /* (@ 0x40040000) LPTMR Structure                                            */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control Status Register                                    */

    struct {
      __IOM uint32_t LPTMREN    : 1;            /* [0..0] LPTMR Enable                                                       */
      __IOM uint32_t TMRMCFG    : 1;            /* [1..1] Timer Mode Configure                                               */
      __IOM uint32_t FRCNT      : 1;            /* [2..2] Free-Running Counter                                               */
      __IOM uint32_t TPIMSEL    : 1;            /* [3..3] Timer Pin Input Mode Select                                        */
      __IOM uint32_t TPISEL     : 2;            /* [5..4] Timer Pin Input Select                                             */
      __IOM uint32_t IEN        : 1;            /* [6..6] Interrupt Enable                                                   */
      __IOM uint32_t COMFLG     : 1;            /* [7..7] Compare Flag                                                       */
      __IOM uint32_t DMAREN     : 1;            /* [8..8] DMA Request Enable                                                 */
      __IM  uint32_t RESERVED0  : 23;
    } bit;
  } CSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Prescaler/Glitch Filter Register                          */

    struct {
      __IOM uint32_t PCLKSEL    : 2;            /* [1..0] Prescaler/Glitch Filter Clock Select                               */
      __IOM uint32_t PBYPEN     : 1;            /* [2..2] Prescaler/Glitch Filter Bypass Enable                              */
      __IOM uint32_t PVCFG      : 4;            /* [6..3] Prescaler/Glitch Filter Value Configure                            */
      __IM  uint32_t RESERVED0  : 25;
    } bit;
  } PSC;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Compare Register                                           */

    struct {
      __IOM uint32_t COMVAL     : 16;           /* [15..0] Compare Value                                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } COM;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Counter Register                                           */

    struct {
      __IOM uint32_t CNTVAL     : 16;           /* [15..0] Counter Value                                                     */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CNT;
} LPTMR_T;                                   /* Size = 16 (0x10)                                                             */



/* =========================================================================================================================== */
/* ================                                            SIM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System Integration Management (SIM)
  */

typedef struct {                                /* (@ 0x40048000) SIM Structure                                              */
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Chip Control register                                      */

    struct {
      __IOM uint32_t ADCIPSEL   : 4;            /* [3..0] ADC Interleave Pins Select                                         */
      __IOM uint32_t CLKOUTSEL  : 4;            /* [7..4] Clock Output Select                                                */
      __IOM uint32_t CLKOUTDIVCFG : 3;          /* [10..8] Clock Output Divide Ratio Configure                               */
      __IOM uint32_t CLKOUTEN   : 1;            /* [11..11] Clock Output Enable                                              */
      __IOM uint32_t TRACECLKSEL : 1;           /* [12..12] Trace Clock Source Select                                        */
      __IOM uint32_t PDUBBMSEL  : 1;            /* [13..13] PDU Back-to-Back Mode Select                                     */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t ADCSSEL    : 3;            /* [18..16] ADC Supply Select                                                */
      __IOM uint32_t ADCISMEN   : 1;            /* [19..19] ADC Internal Supply Monitoring Enable                            */
      __IOM uint32_t SRAMHREN   : 1;            /* [20..20] SRAMU Retention Enable                                           */
      __IOM uint32_t SRAMLREN   : 1;            /* [21..21] SRAML Retention Enable                                           */
      __IM  uint32_t RESERVED1  : 10;
    } bit;
  } CHIPCTRL;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) CFGTMR Option Register 0                                     */
    struct {
      __IOM uint32_t CFGTMR0FSxSEL : 3;            /* [2..0] CFGTMR0 Fault Source x Select                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t CFGTMR1FSxSEL : 3;            /* [6..4] CFGTMR1 Fault Source x Select                                       */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t CFGTMR2FSxSEL : 3;            /* [10..8] CFGTMR2 Fault Source x Select                                      */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t CFGTMR3FSxSEL : 3;            /* [14..12] CFGTMR3 Fault Source x Select                                     */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t CFGTMR4EXCLKPINSEL : 2;       /* [17..16] CFGTMR4 External Clock Pin Select                               */
      __IOM uint32_t CFGTMR5EXCLKPINSEL : 2;       /* [19..18] CFGTMR5 External Clock Pin Select                               */
      __IM  uint32_t RESERVED4  : 4;
      __IOM uint32_t CFGTMR0EXCLKPINSEL : 2;      /* [25..24] CFGTMR0 External Clock Pin Select                                  */
      __IOM uint32_t CFGTMR1EXCLKPINSEL : 2;      /* [27..26] CFGTMR1 External Clock Pin Select                                  */
      __IOM uint32_t CFGTMR2EXCLKPINSEL : 2;      /* [29..28] CFGTMR2 External Clock Pin Select                                  */
      __IOM uint32_t CFGTMR3EXCLKPINSEL : 2;      /* [31..30] CFGTMR3 External Clock Pin Select                                  */
    } bit;
  } CFGTMROPT0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) LPO Clock Select Register                                  */

    struct {
      __IOM uint32_t LPO1KCLKOEN : 1;           /* [0..0] 1 kHz LPOCLK Output Enable                                        */
      __IOM uint32_t LPO32KCLKOEN : 1;          /* [1..1] 32 kHz LPOCLK Output Enable                                       */
      __IOM uint32_t CLKLPOSSEL : 2;            /* [3..2] Peripherals LPO Clock Source Select                                */
      __IOM uint32_t CLK32KSSEL : 2;            /* [5..4] Peripherals 32 kHz Clock Source Select                             */
      __IM  uint32_t RESERVED0  : 26;
    } bit;
  } LPOCLKSEL;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) ADC Options Register                                       */

    struct {
      __IOM uint32_t ADC0TRGSSEL : 1;           /* [0..0] ADC0 Trigger Source Select                                         */
      __IOM uint32_t ADC0SWPTSEL : 3;           /* [3..1] ADC0 Software Pretrigger Sources Select                            */
      __IOM uint32_t ADC0PTSSEL : 2;            /* [5..4] ADC0 Pretrigger Source Select                                      */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t ADC1TRGSSEL : 1;           /* [8..8] ADC1 Trigger Source Select                                         */
      __IOM uint32_t ADC1SWPTSEL : 3;           /* [11..9] ADC1 Software Pretrigger Sources Select                           */
      __IOM uint32_t ADC1PTSSEL : 2;            /* [13..12] ADC1 Pretrigger Source Select                                    */
      __IM  uint32_t RESERVED1  : 18;
    } bit;
  } ADCOPT;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) CFGTMR Option Register 1                                     */

    struct {
      __IOM uint32_t CFGTMR0SYNC  : 1;            /* [0..0] CFGTMR0 Synchronization                                              */
      __IOM uint32_t CFGTMR1SYNC  : 1;            /* [1..1] CFGTMR1 Synchronization                                              */
      __IOM uint32_t CFGTMR2SYNC  : 1;            /* [2..2] CFGTMR2 Synchronization                                              */
      __IOM uint32_t CFGTMR3SYNC  : 1;            /* [3..3] CFGTMR3 Synchronization                                              */
      __IOM uint32_t CFGTMR1CH0ISEL : 2;          /* [5..4] CFGTMR1 CH0 Input Select                                             */
      __IOM uint32_t CFGTMR2CH0ISEL : 2;          /* [7..6] CFGTMR2 CH1 Input Select                                             */
      __IOM uint32_t CFGTMR2CH1ISEL : 1;          /* [8..8] CFGTMR2 CH1 Input Select                                             */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t CFGTMR4SYNC  : 1;          /* [11..11] CFGTMR4 Synchronization                                              */
      __IOM uint32_t CFGTMR5SYNC  : 1;          /* [12..12] CFGTMR5 Synchronization                                              */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t CFGTMRGLDMEN : 1;            /* [15..15] CFGTMR Global Load Mechanism Enable                                */
      __IOM uint32_t CFGTMR0MEN   : 8;            /* [23..16] CFGTMR0 Modulation with CFGTMR1_CH1 Enable                           */
      __IOM uint32_t CFGTMR3MEN   : 8;            /* [31..24] CFGTMR3 Modulation with CFGTMR2_CH1 Enable                           */
    } bit;
  } CFGTMROPT1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Miscellaneous control register 0                           */

    struct {
      __IM  uint32_t RESERVED0  : 9;
      __IOM uint32_t STOP1MON   : 1;            /* [9..9] STOP1 Monitor                                                      */
      __IOM uint32_t STOP2MON   : 1;            /* [10..10] STOP2 Monitor                                                    */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMRSTBEN_D : 1;           /* [14..14] CFGTMR Split Time Base Enable/Disable                              */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t CFGTMR0OBECTRL : 1;          /* [16..16] CFGTMR0 OBE Control                                                */
      __IOM uint32_t CFGTMR1OBECTRL : 1;          /* [17..17] CFGTMR1 OBE Control                                                */
      __IOM uint32_t CFGTMR2OBECTRL : 1;          /* [18..18] CFGTMR2 OBE Control                                                */
      __IOM uint32_t CFGTMR3OBECTRL : 1;          /* [19..19] CFGTMR3 OBE Control                                                */
      __IOM uint32_t CFGTMR4OBECTRL : 1;          /* [20..20] CFGTMR4 OBE Control                                                */
      __IOM uint32_t CFGTMR5OBECTRL : 1;          /* [21..21] CFGTMR5 OBE Control                                                */
      __IM  uint32_t RESERVED3  : 10;
    } bit;
  } MCTRL0;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000024) System Device Identification Register                      */

    struct {
      __IM  uint32_t CFEA       : 8;            /* [7..0] Chip Features                                                      */
      __IM  uint32_t APOC       : 4;            /* [11..8] Available Package Options for Chips                               */
      __IM  uint32_t CSIPNUM    : 4;            /* [15..12] Chip Silicon Implementation Number                               */
      __IM  uint32_t TASYSRAM   : 4;            /* [19..16] Total Available System RAM                                       */
      __IM  uint32_t CDER       : 4;            /* [23..20] Chip Derivate                                                    */
      __IM  uint32_t CSUB       : 4;            /* [27..24] Chip Subseries                                                   */
      __IM  uint32_t CPSG       : 4;            /* [31..28] Chip Product Series Generation                                   */
    } bit;
  } SYSDEVID;
  __IM  uint32_t  RESERVED3[6];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Platform Clock Gating Control Register                     */

    struct {
      __IOM uint32_t MSCCLKEN   : 1;            /* [0..0] MSC Clock Enable                                                   */
      __IOM uint32_t MPUCLKEN   : 1;            /* [1..1] MPU Clock Enable                                                   */
      __IOM uint32_t DMACLKEN   : 1;            /* [2..2] DMA Clock Gating Control                                           */
      __IOM uint32_t EREPCLKEN  : 1;            /* [3..3] EREP Clock Enable                                                  */
      __IOM uint32_t EINJCLKEN  : 1;            /* [4..4] EINJ Clock Enable                                                  */
      __IM  uint32_t RESERVED0  : 27;
    } bit;
  } PCLKGCTRL;
  __IM  uint32_t  RESERVED4[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000004C) Flash Configure Register 1                                 */

    struct {
      __IM  uint32_t RESERVED0  : 12;
      __IM  uint32_t CFGNVMP    : 4;            /* [15..12] Configurable NVM Partition                                       */
      __IM  uint32_t ERAMDS     : 4;            /* [19..16] EEPROM SRAM Data Size                                            */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } FLASHCFG1;
  __IM  uint32_t  RESERVED5;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000054) Unique Identification127_96 Register                       */

    struct {
      __IM  uint32_t CUID96TO127 : 32;          /* [31..0] Chip Unique Identification127_96                                  */
    } bit;
  } UID127_96;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000058) Unique Identification95_64Register                         */

    struct {
      __IM  uint32_t CUID64TO95 : 32;           /* [31..0] Chip Unique Identification95_64                                   */
    } bit;
  } UID95_64;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000005C) Unique Identification63_32Register                         */

    struct {
      __IM  uint32_t CUID32TO63 : 32;           /* [31..0] Chip Unique Identification63_32                                   */
    } bit;
  } UID63_32;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000060) Unique Identification31_0Register                          */

    struct {
      __IM  uint32_t CUID0TO31  : 32;           /* [31..0] Chip Unique Identification31_0                                    */
    } bit;
  } UID31_0;
  __IM  uint32_t  RESERVED6;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000068) System Clock Divider Register 4                            */

    struct {
      __IOM uint32_t TCLKDIVNCFG : 1;           /* [0..0] Trace Fractional Clock Division Numerator Factor Configure         */
      __IOM uint32_t TCLKDIVDCFG : 3;           /* [3..1] Trace Fractional Clock Division Denominator Factor Configure       */
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t DTRACEDEN  : 1;            /* [28..28] Debug Trace Divider Enable                                       */
      __IM  uint32_t RESERVED1  : 3;
    } bit;
  } SYSCLKDIV4;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000006C) Miscellaneous Control register 1                           */

    struct {
      __IOM uint32_t TMC_PSWTR      : 1;            /* [0..0] TMC Peripheral Software Trigger                                    */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } MCTRL1;
} SIM_T;                                     /* Size = 112 (0x70)                                                            */



/* =========================================================================================================================== */
/* ================                                            PM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Port Management (PM)
  */

typedef struct {                                /*  PM Structure
                                     (@ 0x40049000)PMA (@ 0x4004A000)PMB (@ 0x4004B000)PMC (@ 0x4004C000)PMD (@ 0x4004D000)PME */

  union {
    __IOM uint32_t reg;                     /* (@ 0x00000000) Pin Control Register x                                          */

    struct {
      __IOM uint32_t RSEL       : 1;            /* [0..0] Pullup or Pulldown Resistor Select                                 */
      __IOM uint32_t IREN       : 1;            /* [1..1] Internal Pullup or Pulldown Resistor Enable                        */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t PIFEN      : 1;            /* [4..4] Passive Input Filter Enable                                        */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t DSCFG      : 1;            /* [6..6] Drive Strength Configure                                           */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t MUXCTRL    : 3;            /* [10..8] Pin Mux Control                                                   */
      __IM  uint32_t RESERVED3  : 4;
      __IOM uint32_t LOCKCTRL   : 1;            /* [15..15] Control Register Lock                                            */
      __IOM uint32_t INTREQCFG  : 4;            /* [19..16] Interrupt Request Configure                                      */
      __IM  uint32_t RESERVED4  : 4;
      __IOM uint32_t INTFLG     : 1;            /* [24..24] Interrupt Flag                                                   */
      __IM  uint32_t RESERVED5  : 7;
    } bit;
  } PINCTRL[18];
  __IM  uint32_t  RESERVED[14];

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000080) Global Pin Control Low Register                            */

    struct {
      __OM  uint32_t PINW       : 16;           /* [15..0] Global Pin Value Write                                            */
      __OM  uint32_t PINEN      : 16;           /* [31..16] Global Pin Enable                                                */
    } bit;
  } GPINCTRLL;

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000084) Global Pin Control High Register                           */

    struct {
      __OM  uint32_t PINW       : 16;           /* [15..0] Global Pin Value Write                                            */
      __OM  uint32_t PINEN      : 16;           /* [31..16] Global Interrupt Enable                                          */
    } bit;
  } GPINCTRLH;

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000088) Global Interrupt Control Low Register                      */

    struct {
      __OM  uint32_t INTEN     : 16;           /* [15..0] Global Interrupt Enable                                           */
      __OM  uint32_t INTW      : 16;           /* [31..16] Global Interrupt Value Write                                     */
    } bit;
  } GINTCTRLL;

  union {
    __OM  uint32_t reg;                         /* (@ 0x0000008C) Global Interrupt Control High Register                     */

    struct {
      __OM  uint32_t INTEN      : 16;           /* [15..0] Global Interrupt Enable                                           */
      __OM  uint32_t INTW       : 16;           /* [31..16] Global Interrupt Value Write                                     */
    } bit;
  } GINTCTRLH;
  __IM  uint32_t  RESERVED1[4];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000A0) Interrupt Status Register                                  */

    struct {
      __IOM uint32_t INTFLG    : 32;           /* [31..0] Interrupt Flag                                                    */
    } bit;
  } INTSTS;
  __IM  uint32_t  RESERVED2[7];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C0) Digital Filter Enable Register                             */

    struct {
      __IOM uint32_t DOFEN      : 32;           /* [31..0] Digital Output Filter Enable                                      */
    } bit;
  } DFEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C4) Digital Filter Clock Source Register                       */

    struct {
      __IOM uint32_t DFCLKS     : 1;            /* [0..0] Digital Filter Clock Source                                        */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } DFCLKS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C8) Digital Filter Length Register                             */

    struct {
      __IOM uint32_t DFWID      : 5;            /* [4..0] Digital Filter Width                                               */
      __IM  uint32_t RESERVED0  : 27;
    } bit;
  } DFWID;
} PM_T;                                     /* Size = 204 (0xcc)                                                            */



/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Software Watchdog Timer (WDT)
  */

typedef struct {                                /* (@ 0x40052000) WDT Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Control and Status Register                                */

    struct {
      __IOM uint32_t STOPEN     : 1;            /* [0..0] Watchdog in Stop Mode Enable                                       */
      __IOM uint32_t WEN        : 1;            /* [1..1] Watchdog in Wait Mode Enable                                       */
      __IOM uint32_t DBGEN      : 1;            /* [2..2] Watchdog in Debug Mode Enable                                      */
      __IOM uint32_t FTEN       : 2;            /* [4..3] Fast Test Enable                                                   */
      __IOM uint32_t RECFGEN    : 1;            /* [5..5] Watchdog Reconfigure Enable                                        */
      __IOM uint32_t WDTIEN     : 1;            /* [6..6] Watchdog Interrupt Enable                                          */
      __IOM uint32_t CNTEN      : 1;            /* [7..7] Watchdog Count Enable                                              */
      __IOM uint32_t CLKSRCSEL  : 2;            /* [9..8] Watchdog Clock Source Select                                       */
      __IM  uint32_t RCSUSFLG   : 1;            /* [10..10] Reconfigure Success Flag                                         */
      __IM  uint32_t ULFLG      : 1;            /* [11..11] Unlock Flag                                                      */
      __IOM uint32_t PSCEN      : 1;            /* [12..12] Prescaler Enable                                                 */
      __IOM uint32_t CMDEN32    : 1;            /* [13..13] 32-bit Refresh / UnlockCommand Write Word Enable                 */
      __IOM uint32_t WDTIFLG    : 1;            /* [14..14] Watchdog Interrupt Flag                                          */
      __IOM uint32_t WINMEN     : 1;            /* [15..15] Window Mode Enable                                               */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Counter Register                                           */

    struct {
      __IOM uint32_t LOWCNT     : 8;            /* [7..0] Low Byte of Counter                                                */
      __IOM uint32_t HIGHCNT    : 8;            /* [15..8] High Byte of Counter                                              */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } CNT;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Timeout Value Register                                     */

    struct {
      __IOM uint32_t LOWTOVAL   : 8;            /* [7..0] Low Byte of Timeout Value                                          */
      __IOM uint32_t HIGHTOVAL  : 8;            /* [15..8] High Byte of Timeout Value                                        */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } TOVAL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Window Register                                            */

    struct {
      __IOM uint32_t LOWWIN     : 8;            /* [7..0] Low Byte of Window                                                 */
      __IOM uint32_t HIGHWIN    : 8;            /* [15..8] High Byte of Window                                               */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } WIN;
} WDT_T;                                     /* Size = 16 (0x10)                                                             */



/* =========================================================================================================================== */
/* ================                                            CFGIO                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief I/O (CFGIO)
  */

typedef struct {                                /* (@ 0x4005A000) CFGIO Structure                                          */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Number                                                    */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t SHINUMI    : 8;            /* [7..0] Shifter Number Implemented                                         */
      __IM  uint32_t TMRNUMI    : 8;            /* [15..8] Timer Number Implemented                                          */
      __IM  uint32_t PNUMI      : 8;            /* [23..16] Pin Number Implemented                                           */
      __IM  uint32_t TRGNUMI    : 8;            /* [31..24] Trigger Number Implemented                                       */
    } bit;
  } PARA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Control Register                                           */

    struct {
      __IOM uint32_t CFGIOEN       : 1;         /* [0..0] CFGIO Module Enable                                              */
      __IOM uint32_t SWRSTEN    : 1;            /* [1..1] Software Reset Enable                                              */
      __IOM uint32_t FRACCEN    : 1;            /* [2..2] Fast Register Access Enable                                        */
      __IM  uint32_t RESERVED0  : 27;
      __IOM uint32_t DBGEN      : 1;            /* [30..30] In Debug Mode CFGIO Enable                                     */
      __IOM uint32_t DOZEEN     : 1;            /* [31..31] In Doze Mode CFGIO Enable                                      */
    } bit;
  } CTRL;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000000C) Pin Input Data Register                                    */

    struct {
      __IM  uint32_t PIDATA     : 8;            /* [7..0] Pin Input Data                                                     */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } PIDATA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Shifter Status Register                                    */

    struct {
      __IOM uint32_t SSTS       : 4;            /* [3..0] Shifter Status                                                     */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } SSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Shifter Error Flags Register                               */

    struct {
      __IOM uint32_t SERRFLG    : 4;            /* [3..0] Shifter Error Flag                                                 */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } SERRFLG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Timer Status Register                                      */

    struct {
      __IOM uint32_t TMRSTS     : 4;            /* [3..0] Timer Status                                                       */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } TMRSTS;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Shifter Status Interrupt Enable Register                   */

    struct {
      __IOM uint32_t SSTSIEN    : 4;            /* [3..0] Shifter Status Interrupt Enable                                    */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } SSTSIEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) Shifter Error Flag Interrupt Enable Register               */

    struct {
      __IOM uint32_t SEFIEN     : 4;            /* [3..0] Shifter Error Flag Interrupt Enable                                */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } SEFIEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000028) Timer Status Interrupt Enable Register                     */

    struct {
      __IOM uint32_t TMRSTSIEN  : 4;            /* [3..0] Timer Status Interrupt Enable                                      */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } TMRSTSIEN;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000030) Shifter Status DMA request Enable Register                 */

    struct {
      __IOM uint32_t DMAREQEN   : 4;            /* [3..0] Shifter Status DMA Request Enable                                  */
      __IM  uint32_t RESERVED0  : 28;
    } bit;
  } DMAREQEN;
  __IM  uint32_t  RESERVED2[19];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000080) Shifter Control Register 0                                 */

    struct {
      __IOM uint32_t SMCFG      : 3;            /* [2..0] Shifter Mode Configure                                             */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t SPPOLCFG   : 1;            /* [7..7] Shifter Pin Polarity Configure                                     */
      __IOM uint32_t SUPSEL     : 3;            /* [10..8] Shifter Use Pin Select                                            */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t SOPCFG     : 2;            /* [17..16] Shifter Output Pin Configure                                     */
      __IM  uint32_t RESERVED2  : 5;
      __IOM uint32_t SCLKLCFG   : 1;            /* [23..23] Shift clock location Configure                                   */
      __IOM uint32_t TMRSEL     : 2;            /* [25..24] (Timer Select)                                                   */
      __IM  uint32_t RESERVED3  : 6;
    } bit;
  } SCTRL[4];

  __IM  uint32_t  RESERVED3[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000100) Shifter Configure Register 0                               */

    struct {
      __IOM uint32_t SSTAFSEL   : 2;            /* [1..0] Shifter Start Bit Function Select                                  */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t SSTOPFSEL  : 2;            /* [5..4] Shifter Stop Bit Function Select                                   */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t ISRCSEL    : 1;            /* [8..8] Input Source Select                                                */
      __IM  uint32_t RESERVED2  : 23;
    } bit;
  } SCFG[4];

  __IM  uint32_t  RESERVED4[60];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000200) Shifter Buffer Register 0                                  */

    struct {
      __IOM uint32_t SBUFDATA   : 32;           /* [31..0] Shift Buffer Data                                                 */
    } bit;
  } SBUF[4];

  __IM  uint32_t  RESERVED5[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000280) Shifter Buffer 0 Bit Swapped Register                      */

    struct {
      __IOM uint32_t BITSWA     : 32;           /* [31..0] Bit Swap                                                          */
    } bit;
  } SBUFBITSWA[4];

  __IM  uint32_t  RESERVED6[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000300) Shifter Buffer0 Byte Swapped Register                      */

    struct {
      __IOM uint32_t BYTSWA     : 32;           /* [31..0] Byte Swap                                                         */
    } bit;
  } SBUFBYTSWA[4];

  __IM  uint32_t  RESERVED7[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000380) Shifter Buffer0 Bit Byte Swapped Register                  */

    struct {
      __IOM uint32_t BSWAWEB    : 32;           /* [31..0] Bit Swapped Within Each Byte                                      */
    } bit;
  } SBUFBSWA[4];

  __IM  uint32_t  RESERVED8[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000400) Timer Control Register 0                                   */

    struct {
      __IOM uint32_t TMRMCFG    : 2;            /* [1..0] Timer Mode Configure                                               */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t TMRPPOLCFG : 1;            /* [7..7] Timer Pin Polarity Configure                                       */
      __IOM uint32_t TMRUPSEL   : 3;            /* [10..8] Timer Use Pin Select                                              */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t TMROPCFG   : 2;            /* [17..16] Timer output Pin Configure                                       */
      __IM  uint32_t RESERVED2  : 4;
      __IOM uint32_t TRGSSEL    : 1;            /* [22..22] Trigger Source Select                                            */
      __IOM uint32_t TRGPOLCFG  : 1;            /* [23..23] Trigger Polarity Configure                                       */
      __IOM uint32_t TRGVSEL    : 4;            /* [27..24] Trigger Valid Value Select                                       */
      __IM  uint32_t RESERVED3  : 4;
    } bit;
  } TMRCTRL[4];

  __IM  uint32_t  RESERVED9[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000480) Timer Configure Register 0                                 */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TMRSTAEN   : 1;            /* [1..1] Timer Start Bit Enable                                             */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t TMRSTOPFSEL : 2;           /* [5..4] Timer Stop Bit function select                                     */
      __IM  uint32_t RESERVED2  : 2;
      __IOM uint32_t TMRENCFG   : 3;            /* [10..8] Timer Enable Condition Configure                                  */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t TMRDISCFG  : 3;            /* [14..12] Timer Disable Condition Configure                                */
      __IM  uint32_t RESERVED4  : 1;
      __IOM uint32_t TMRRSTCFG  : 3;            /* [18..16] Timer Reset Condition Configure                                  */
      __IM  uint32_t RESERVED5  : 1;
      __IOM uint32_t TMRDCFG    : 2;            /* [21..20] Timer Decrement Configure                                        */
      __IM  uint32_t RESERVED6  : 2;
      __IOM uint32_t TMROCFG    : 2;            /* [25..24] Timer Output Configure                                           */
      __IM  uint32_t RESERVED7  : 6;
    } bit;
  } TMRCFG[4];

  __IM  uint32_t  RESERVED10[28];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000500) Timer Compare Register 0                                   */

    struct {
      __IOM uint32_t TMRCOMPV   : 16;           /* [15..0] Timer Compare Value                                               */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } TMRCOMP[4];
} CFGIO_T;                                      /* Size = 1296 (0x510)                                                       */



/* =========================================================================================================================== */
/* ================                                           EWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief External Watchdog (EWDT)
  */

typedef struct {                                /* (@ 0x40061000) EWDT Structure                                             */

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000000) Control Register                                           */

    struct {
      __OM  uint8_t EWDTEN      : 1;            /* [0..0] EWDT Module Enable                                                 */
      __OM  uint8_t INSIGSEL    : 1;            /* [1..1] EWDT_in Signal Assertion State Select                              */
      __OM  uint8_t INPEN       : 1;            /* [2..2] Input Port Enable                                                  */
      __IOM uint8_t INTREQEN    : 1;            /* [3..3] Interrupt Request Enable                                           */
            uint8_t             : 4;
    } bit;
  } CTRL;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000001) Service Register                                           */

    struct {
      __OM  uint8_t SEQDATA     : 8;            /* [7..0] Sequence Data Area                                                 */
    } bit;
  } SEQ;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000002) Compare Low Register                                       */

    struct {
      __OM  uint8_t COMPL       : 8;            /* [7..0] Compare Low                                                        */
    } bit;
  } COMPL;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000003) Compare High Register                                      */

    struct {
      __OM  uint8_t COMPH       : 8;            /* [7..0] Compare High                                                       */
    } bit;
  } COMPH;
  __IM  uint8_t   RESERVED;

  union {
    __OM  uint8_t reg;                          /* (@ 0x00000005) Clock Prescaler Register                                   */

    struct {
      __OM  uint8_t CLKPSC      : 8;            /* [7..0] Clock Prescaler                                                    */
    } bit;
  } CLKPSC;
} EWDT_T;                                    /* Size = 6 (0x6)                                                               */



/* =========================================================================================================================== */
/* ================                                            TMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Trigger MUX Control (TMC)
  */

/** TMC - Size of Registers Arrays */
#define TMC_TMCn_COUNT                     30U

typedef struct {                                /* (@ 0x40063000) TMC Structure                                                */
  __IO uint32_t TMCn[TMC_TMCn_COUNT];     /* Array offset: 0x0, array step: 0x4                                                */
} TMC_T;


/* =========================================================================================================================== */
/* ================                                            SCG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System Clock Generator (SCG)
  */

typedef struct {                                /* (@ 0x40064000) SCG Structure                                              */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t VERID      : 32;           /* [31..0] Version Number                                                    */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t CLKS       : 8;            /* [7..0] Clock Sources                                                      */
      __IM  uint32_t RESERVED0  : 19;
      __IM  uint32_t SYSCLKDIVCFG : 5;          /* [31..27] System Clock Divider Configure                                   */
    } bit;
  } PARA;
  __IM  uint32_t  RESERVED[2];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000010) Clock Configure Register                                   */

    struct {
      __IM  uint32_t SCLKDIVRCFG : 4;           /* [3..0] Slow Clock Division Ratio Configure                                */
      __IM  uint32_t BCLKDIVRCFG : 4;           /* [7..4] Bus Clock Divide Ratio Configure                                   */
      __IM  uint32_t RESERVED1  : 8;
      __IM  uint32_t CCLKDIVRCFG : 4;           /* [19..16] Core Clock Divide Ratio Configure                                */
      __IM  uint32_t RESERVED2  : 4;
      __IM  uint32_t SYSCLKSSEL : 4;            /* [27..24] System Clock Source Select                                       */
      __IM  uint32_t RESERVED3  : 4;
    } bit;
  } CLKCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Run Clock Control Register                                 */

    struct {
      __IOM uint32_t SCLKDIVRCFG : 4;           /* [3..0] Slow Clock Division Ratio Configure                                */
      __IOM uint32_t BCLKDIVRCFG : 4;           /* [7..4] Bus Clock Divide Ratio Configure                                   */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t CCLKDIVRCFG : 4;           /* [19..16] Core Clock Divide Ratio Configure                                */
      __IM  uint32_t RESERVED1  : 4;
      __IOM uint32_t SYSCLKSSEL : 4;            /* [27..24] System Clock Source Select                                       */
      __IM  uint32_t RESERVED2  : 4;
    } bit;
  } RUNCLKCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) VLPR Clock Control Register                                */

    struct {
      __IOM uint32_t SCLKDIVRCFG : 4;           /* [3..0] Slow Clock Division Ratio Configure                                */
      __IOM uint32_t BCLKDIVRCFG : 4;           /* [7..4] Bus Clock Divide Ratio Configure                                   */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t CCLKDIVRCFG : 4;           /* [19..16] Core Clock Divide Ratio Configure                                */
      __IM  uint32_t RESERVED1  : 4;
      __IOM uint32_t SYSCLKSSEL : 4;            /* [27..24] System Clock Source Select                                       */
      __IM  uint32_t RESERVED2  : 4;
    } bit;
  } VLPRCLKCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) HSRUN Clock Control Register                               */

    struct {
      __IOM uint32_t SCLKDIVRCFG : 4;           /* [3..0] Slow Clock Division Ratio Configure                                */
      __IOM uint32_t BCLKDIVRCFG : 4;           /* [7..4] Bus Clock Divide Ratio Configure                                   */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t CCLKDIVRCFG : 4;           /* [19..16] Core Clock Divide Ratio Configure                                */
      __IM  uint32_t RESERVED1  : 4;
      __IOM uint32_t SYSCLKSSEL : 4;            /* [27..24] System Clock Source Select                                       */
      __IM  uint32_t RESERVED2  : 4;
    } bit;
  } HSRUNCLKCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) System Clock Output Select Register                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t SYSCLKOSEL : 4;            /* [27..24] System Clock Output Select                                       */
      __IM  uint32_t RESERVED1  : 4;
    } bit;
  } SYSCLKOSEL;
  __IM  uint32_t  RESERVED1[55];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000100) System OSC Control Status Register                         */

    struct {
      __IOM uint32_t SYSOSCEN   : 1;            /* [0..0] System OSC Enable                                                  */
      __IM  uint32_t RESERVED0  : 15;
      __IOM uint32_t SYSOSCMEN  : 1;            /* [16..16] System OSC Clock Monitor Enable                                  */
      __IOM uint32_t SYSOSCMRSTEN : 1;          /* [17..17] System OSC Clock Monitor Reset Enable                            */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t LOCK       : 1;            /* [23..23] Register Lock                                                    */
      __IM  uint32_t SYSOSCVLDFLG : 1;          /* [24..24] System OSC Valid Flag                                            */
      __IM  uint32_t SYSOSCSEL  : 1;            /* [25..25] System OSC Select                                                */
      __IOM uint32_t SYSOSCCLKEFLG : 1;         /* [26..26] System OSC Clock Error Flag                                      */
      __IM  uint32_t RESERVED2  : 5;
    } bit;
  } SYSOSCCSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000104) System OSC Divide Configure Register                       */

    struct {
      __IOM uint32_t SYSOSCDCFG1 : 3;           /* [2..0] System Clock Divide 1 Configure                                    */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t SYSOSCDCFG2 : 3;           /* [10..8] System OSC Clock Divide 2 Configure                               */
      __IM  uint32_t RESERVED1  : 21;
    } bit;
  } SYSOSCDIVCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000108) System Oscillator Configure Register                       */

    struct {
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t ERCLKSEL   : 1;            /* [2..2] External Reference Clock Select                                    */
      __IOM uint32_t GOSCSEL    : 1;            /* [3..3] Gain Oscillator Select                                             */
      __IOM uint32_t SYSOSCFSEL : 2;            /* [5..4] System OSC Frequency Select                                        */
      __IM  uint32_t RESERVED1  : 26;
    } bit;
  } SYSOSCCFG;
  __IM  uint32_t  RESERVED2[61];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000200) LSI Control Status Register                                */

    struct {
      __IOM uint32_t LSIEN      : 1;            /* [0..0] LSI Enable                                                         */
      __IOM uint32_t LSIEN_STOP : 1;            /* [1..1] LSI in STOP Mode Enable                                            */
      __IOM uint32_t LSIEN_LP   : 1;            /* [2..2] LSI Low Power Enable                                               */
      __IM  uint32_t RESERVED0  : 20;
      __IOM uint32_t LOCK       : 1;            /* [23..23] Register Lock                                                    */
      __IM  uint32_t LSIVLDFLG  : 1;            /* [24..24] LSI Valid Flag                                                   */
      __IM  uint32_t LSISEL     : 1;            /* [25..25] LSI Select                                                       */
      __IM  uint32_t RESERVED1  : 6;
    } bit;
  } LSICSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000204) LSICLK Divide Register                                     */

    struct {
      __IOM uint32_t LSIDIVCFG1 : 3;            /* [2..0] LSI Divide 1 Configure                                             */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t LSIDIVCFG2 : 3;            /* [10..8] LSI Divide 2 Configure                                            */
      __IM  uint32_t RESERVED1  : 21;
    } bit;
  } LSIDIV;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000208) LSICLK Frequency Select Register                           */

    struct {
      __IOM uint32_t LSIFSEL    : 1;            /* [0..0] LSICLK Frequency Select                                            */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } LSIFSEL;
  __IM  uint32_t  RESERVED3[61];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000300) HSI Control Status Register                                */

    struct {
      __IOM uint32_t HSIEN      : 1;            /* [0..0] HSI Enable                                                         */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t HSIREN     : 1;            /* [3..3] HSI Regulator Enable                                               */
      __IM  uint32_t RESERVED1  : 19;
      __IOM uint32_t LOCK       : 1;            /* [23..23] Register Lock                                                    */
      __IM  uint32_t HSIVLDFLG  : 1;            /* [24..24] HSI Valid Flag                                                   */
      __IM  uint32_t HSISEL     : 1;            /* [25..25] HSI Select                                                       */
      __IOM uint32_t HSIEFLG    : 1;            /* [26..26] HSI Error Flag                                                   */
      __IM  uint32_t RESERVED2  : 5;
    } bit;
  } HSICSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000304) HSI Divide Register                                        */

    struct {
      __IOM uint32_t HSIDIVCFG1 : 3;            /* [2..0] HSI Divide 1 Configure                                             */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t HSIDIVCFG2 : 3;            /* [10..8] HSI Divide 2 Configure                                            */
      __IM  uint32_t RESERVED1  : 21;
    } bit;
  } HSIDIV;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000308) HSI Frequency Select Register                              */

    struct {
      __IOM uint32_t HSIFSEL    : 2;            /* [1..0] HSI Frequency Select                                               */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } HSIFSEL;
  __IM  uint32_t  RESERVED4[189];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000600) System PLL Control Status Register                         */

    struct {
      __IOM uint32_t SYSPLLEN   : 1;            /* [0..0] System PLL Enable                                                  */
      __IM  uint32_t RESERVED0  : 15;
      __IOM uint32_t SYSPLLMEN  : 1;            /* [16..16] System PLL Clock Monitor Enable                                  */
      __IOM uint32_t SYSPLLMRSTEN : 1;          /* [17..17] System PLL Clock Monitor Reset Enable                            */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t LOCK       : 1;            /* [23..23] Register Lock                                                    */
      __IM  uint32_t SYSPLLVLDFLG : 1;          /* [24..24] System PLL Valid Flag                                            */
      __IM  uint32_t SYSPLLSEL  : 1;            /* [25..25] System PLL Select                                                */
      __IOM uint32_t SYSPLLCLKEFLG : 1;         /* [26..26] System PLL Clock Error Flag                                      */
      __IM  uint32_t RESERVED2  : 5;
    } bit;
  } SYSPLLCSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000604) System PLL Divide Register                                 */

    struct {
      __IOM uint32_t SYSPLLDIVCFG1 : 3;         /* [2..0] System PLL Clock Divide 1 Configuration                            */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t SYSPLLDIVCFG2 : 3;         /* [10..8] System PLL Clock Divide 2 Configuration                           */
      __IM  uint32_t RESERVED1  : 21;
    } bit;
  } SYSPLLDIV;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000608) System PLL Configuration Register                          */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t PLLRDIVCFG : 3;            /* [10..8] PLL Reference Clock Divider Configure                             */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t SYSPLLMULCFG : 5;          /* [20..16] System PLL Multiply Factor Configuration                         */
      __IM  uint32_t RESERVED2  : 11;
    } bit;
  } SYSPLLCFG;
} SCG_T;                                     /* Size = 1548 (0x60c)                                                          */



/* =========================================================================================================================== */
/* ================                                            PCM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Peripheral Clock management (PCM)
  */

typedef struct {                                /* (@ 0x40065000) PCM Structure                                              */
  __IM  uint32_t  RESERVED[32];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000080) FLASH Clock Register                                       */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t FLASHEN    : 1;            /* [30..30] Flash Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } FLASHCLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000084) DMACHM Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t DMACHMEN   : 1;            /* [30..30] DMACHM Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } DMACHMCLK;
  __IM  uint32_t  RESERVED1[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000090) CAN0 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t CAN0EN     : 1;            /* [30..30] CAN0 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CAN0CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000094) CAN1 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t CAN1EN     : 1;            /* [30..30] CAN1 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CAN1CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000098) CFGTMR3 Clock Register                                       */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR3CSSEL : 3;            /* [26..24] CFGTMR3 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR3EN    : 1;            /* [30..30] CFGTMR3 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR3CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000009C) ADC1 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t ADC1CSSEL  : 3;            /* [26..24] ADC1 Clock Source Select                                         */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t ADC1EN     : 1;            /* [30..30] ADC1 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } ADC1CLK;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000AC) CAN2 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t CAN2EN     : 1;            /* [30..30] CAN2 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CAN2CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B0) LPSPI0 Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t SPI0CSSEL  : 3;            /* [26..24] LPSPI0 Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPSPI0EN   : 1;            /* [30..30] LPSPI0 Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPSPI0CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B4) LPSPI1 Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t SPI1CSSEL  : 3;            /* [26..24] LPSPI1 Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPSPI1EN   : 1;            /* [30..30] LPSPI1 Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPSPI1CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000B8) LPSPI2 Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t SPI2CSSEL  : 3;            /* [26..24] LPSPI2 Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPSPI2EN   : 1;            /* [30..30] LPSPI2 Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPSPI2CLK;
  __IM  uint32_t  RESERVED3[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C4) PDU1 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PDU1EN     : 1;            /* [30..30] PDU1 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PDU1CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000C8) CRC Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t CRCEN      : 1;            /* [30..30] CRC Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CRCCLK;
  __IM  uint32_t  RESERVED4[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000D8) PDU0 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PDU0EN     : 1;            /* [30..30] PDU0 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PDU0CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000DC) PCC LPIT Clock Register                                    */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t LPITMRCSSEL : 3;           /* [26..24] LPITMR Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPITMREN   : 1;            /* [30..30] LPITMR Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPITMRCLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E0) CFGTMR0 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR0CSSEL : 3;            /* [26..24] CFGTMR0 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR0EN    : 1;            /* [30..30] CFGTMR0 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR0CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E4) CFGTMR1 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR1CSSEL : 3;            /* [26..24] CFGTMR1 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR1EN    : 1;            /* [30..30] CFGTMR1 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR1CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000E8) CFGTMR2 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR2CSSEL : 3;            /* [26..24] CFGTMR2 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR2EN    : 1;            /* [30..30] CFGTMR2 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR2CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000EC) ADC0 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t ADC0CSSEL  : 3;            /* [26..24] ADC0 Clock Source Select                                         */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t ADC0EN     : 1;            /* [30..30] ADC0 Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } ADC0CLK;
  __IM  uint32_t  RESERVED5;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000000F4) RTC Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t RTCEN      : 1;            /* [30..30] RTC Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } RTCCLK;
  __IM  uint32_t  RESERVED6[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000100) LPTMR Clock Register                                  */

    struct {
      __IOM uint32_t LPTMRDIVDCFG : 3;         /* [2..0] LPTMR Clock Divide Denominator Factor Configure                   */
      __IOM uint32_t LPTMRDIVNCFG : 1;         /* [3..3] LPTMR Clock Divide Numerator Factor Configure                     */
      __IM  uint32_t RESERVED0  : 20;
      __IOM uint32_t LPTMRCSSEL : 3;           /* [26..24] LPTMR Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPTMREN   : 1;            /* [30..30] LPTMR Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPTMRCLK;
  __IM  uint32_t  RESERVED7[8];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000124) PMA Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PMAEN      : 1;            /* [30..30] PMA Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PMACLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000128) PMB Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PMBEN      : 1;            /* [30..30] PMB Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PMBCLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000012C) PMC Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PMCEN      : 1;            /* [30..30] PMC Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PMCCLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000130) PMD Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PMDEN      : 1;            /* [30..30] PMD Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PMDCLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000134) PME Clock Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t PMEEN      : 1;            /* [30..30] PME Clock Enable                                                 */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } PMECLK;
  __IM  uint32_t  RESERVED8[12];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000168) CFGIO Clock Register                                     */

    struct {
      __IM  uint32_t RESERVED0       : 24;
      __IOM uint32_t CFGIOCSSEL    : 3;            /* [26..24] CFGIO Clock Source Select                                 */
      __IM  uint32_t RESERVED1       : 3;
      __IOM uint32_t CFGIOEN       : 1;            /* [30..30] CFGIO Clock Enable                                        */
      __IM  uint32_t PSTFLG          : 1;            /* [31..31] Peripheral Present Flag                                     */
    } bit;
  } CFGIOCLK;
  __IM  uint32_t  RESERVED9[6];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000184) EWDT Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t EWDTEN     : 1;            /* [30..30] EWDT Clock Enable                                                */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } EWDTCLK;
  __IM  uint32_t  RESERVED10[4];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000198) LPI2C0 Clock Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t LPI2CCSSEL : 3;           /* [26..24] LPI2C0 Clock Source Select                                       */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPI2CEN   : 1;            /* [30..30] LPI2C0 Clock Enable                                              */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPI2CCLK;
  __IM  uint32_t  RESERVED11[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000001A8) LPUART0 Clock Register                                     */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t LPUART0CSSEL : 3;          /* [26..24] LPUART0 Clock Source Select                                      */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPUART0EN  : 1;            /* [30..30] LPUART0 Clock Enable                                             */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPUART0CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000001AC) LPUART1 Clock Register                                     */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t LPUART1CSSEL : 3;          /* [26..24] LPUART1 Clock Source Select                                      */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPUART1EN  : 1;            /* [30..30] LPUART1 Clock Enable                                             */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPUART1CLK;

  union {
    __IOM uint32_t reg;                         /* (@ 0x000001B0) LPUART2 Clock Register                                     */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t LPUART2CSSEL : 3;          /* [26..24] LPUART2 Clock Source Select                                      */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t LPUART2EN  : 1;            /* [30..30] LPUART2 Clock Enable                                             */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } LPUART2CLK;

  __IM  uint32_t  RESERVED12[1];
    union {
    __IOM uint32_t reg;                         /* (@ 0x000001B8) CFGTMR4 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR4CSSEL : 3;            /* [26..24] CFGTMR4 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR4EN    : 1;            /* [30..30] CFGTMR4 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR4CLK;

    union {
    __IOM uint32_t reg;                         /* (@ 0x000001BC) CFGTMR5 Clock Register                                        */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t CFGTMR5CSSEL : 3;            /* [26..24] CFGTMR5 Clock Source Select                                        */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t CFGTMR5EN    : 1;            /* [30..30] CFGTMR5 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } CFGTMR5CLK;
  __IM  uint32_t  RESERVED13[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x000001CC) COMP0 Clock Register                                       */

    struct {
      __IM  uint32_t RESERVED0  : 30;
      __IOM uint32_t COMP0EN    : 1;            /* [30..30] COMP0 Clock Enable                                               */
      __IM  uint32_t PSTFLG     : 1;            /* [31..31] Peripheral Present Flag                                          */
    } bit;
  } COMP0CLK;
} PCM_T;                                     /* Size = 464 (0x1d0)                                                           */



/* =========================================================================================================================== */
/* ================                                           LPI2C                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief The LPI2C Memory Map/Register Definition can be found here. (LPI2C)
  */

typedef struct {                                /* (@ 0x40066000) LPI2C Structure                                            */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Number                                                    */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t MTXFS      : 4;            /* [3..0] Master Transmit FIFO Size                                          */
      __IM  uint32_t RESERVED0  : 4;
      __IM  uint32_t MRXFS      : 4;            /* [11..8] Master Receive FIFO Size                                          */
      __IM  uint32_t RESERVED1  : 20;
    } bit;
  } PARA;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Master Control Register                                    */

    struct {
      __IOM uint32_t MMEN       : 1;            /* [0..0] Master Mode Enable                                                 */
      __IOM uint32_t MRST       : 1;            /* [1..1] Master Logic Software Reset                                        */
      __IOM uint32_t DOZEDIS    : 1;            /* [2..2] Master Disabled in Doze Mode                                       */
      __IOM uint32_t DBGEN      : 1;            /* [3..3] Master Enabled in Debug Mode                                       */
      __IM  uint32_t RESERVED0  : 4;
      __OM  uint32_t TXFRST     : 1;            /* [8..8] Transmit FIFO Reset                                                */
      __OM  uint32_t RXFRST     : 1;            /* [9..9] Receive FIFO Reset                                                 */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } MCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Master Status Register                                     */

    struct {
      __IM  uint32_t TXFLG      : 1;            /* [0..0] Transmit Data Flag                                                 */
      __IM  uint32_t RXFLG      : 1;            /* [1..1] Receive Data Flag                                                  */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t ENDFLG     : 1;            /* [8..8] End Flag                                                           */
      __IOM uint32_t STOPFLG    : 1;            /* [9..9] STOP Flag                                                          */
      __IOM uint32_t NACKFLG    : 1;            /* [10..10] Unexpected NACK Detect Flag                                      */
      __IOM uint32_t MALFLG     : 1;            /* [11..11] Master Arbitration Lost Flag                                     */
      __IOM uint32_t FEFLG      : 1;            /* [12..12] FIFO Error Flag                                                  */
      __IOM uint32_t PLTFLG     : 1;            /* [13..13] Pin Low Timeout Flag                                             */
      __IOM uint32_t RXMFLG     : 1;            /* [14..14] Received Data Match Flag                                         */
      __IM  uint32_t RESERVED1  : 9;
      __IM  uint32_t MBSYFLG    : 1;            /* [24..24] LPI2C Master Busy Flag                                             */
      __IM  uint32_t BBSYFLG    : 1;            /* [25..25] LPI2C Bus Busy Flag                                                */
      __IM  uint32_t RESERVED2  : 6;
    } bit;
  } MSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Master Interrupt Enable Register                           */

    struct {
      __IOM uint32_t TXDIEN     : 1;            /* [0..0] Transmit Data Interrupt Enable                                     */
      __IOM uint32_t RXDIEN     : 1;            /* [1..1] Receive Data Interrupt Enable                                      */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t ENDIEN     : 1;            /* [8..8] End Packet Interrupt Enable                                        */
      __IOM uint32_t STOPIEN    : 1;            /* [9..9] STOP Detect Interrupt Enable                                       */
      __IOM uint32_t NACKIEN    : 1;            /* [10..10] Unexpected NACK Detect Interrupt Enable                          */
      __IOM uint32_t MALIEN     : 1;            /* [11..11] Master Arbitration Lost Interrupt Enable                         */
      __IOM uint32_t FEIEN      : 1;            /* [12..12] FIFO Error Interrupt Enable                                      */
      __IOM uint32_t PLTIEN     : 1;            /* [13..13] Pin Low Timeout Interrupt Enable                                 */
      __IOM uint32_t RXMIEN     : 1;            /* [14..14] Received Data Match Interrupt Enable                             */
      __IM  uint32_t RESERVED1  : 17;
    } bit;
  } MINTEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) Master DMA Enable Register                                 */

    struct {
      __IOM uint32_t TXDMAEN    : 1;            /* [0..0] Transmit Data DMA Enable                                           */
      __IOM uint32_t RXDMAEN    : 1;            /* [1..1] Receive Data DMA Enable                                            */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } MDMAEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Master Configure Register 0                                */

    struct {
      __IOM uint32_t HRIEN      : 1;            /* [0..0] Host Request Input Enable                                          */
      __IOM uint32_t HRPCFG     : 1;            /* [1..1] Host Request Polarity Configure                                    */
      __IOM uint32_t HRISRC     : 1;            /* [2..2] Host Request Input Source Select                                   */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t CFEN       : 1;            /* [8..8] Circular FIFO Enable                                               */
      __IOM uint32_t RXMEN      : 1;            /* [9..9] Receive Data Match Enable                                          */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } MCFG0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) Master Configure Register 1                                */

    struct {
      __IOM uint32_t CLKPS      : 3;            /* [2..0] Clock Prescaler Configure                                          */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t ASGEN      : 1;            /* [8..8] Automatic STOP Condition Generation                                */
      __IOM uint32_t INACK      : 1;            /* [9..9] Ignore NACK                                                        */
      __IOM uint32_t PINLTOCFG  : 1;            /* [10..10] Pin Low Timeout Configure                                        */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t MCCFG      : 3;            /* [18..16] Match Condition Configure                                        */
      __IM  uint32_t RESERVED2  : 5;
      __IOM uint32_t PINMCFG    : 3;            /* [26..24] Pin Mode Configure                                               */
      __IM  uint32_t RESERVED3  : 5;
    } bit;
  } MCFG1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000028) Master Configure Register 2                                */

    struct {
      __IOM uint32_t BITO       : 12;           /* [11..0] Bus Idle Timeout Value                                            */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t FILSCLCFG  : 4;            /* [19..16] Filter SCL Configure                                             */
      __IM  uint32_t RESERVED1  : 4;
      __IOM uint32_t FILSDACFG  : 4;            /* [27..24] Filter SDA Configure                                             */
      __IM  uint32_t RESERVED2  : 4;
    } bit;
  } MCFG2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000002C) Master Configure Register 3                                */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t PLTO       : 12;           /* [19..8] Pin Low Timeout Flag Configure                                    */
      __IM  uint32_t RESERVED1  : 12;
    } bit;
  } MCFG3;
  __IM  uint32_t  RESERVED1[4];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Master Data Match Register                                 */

    struct {
      __IOM uint32_t VAL0       : 8;            /* [7..0] Compare Match 0 Value                                              */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t VAL1       : 8;            /* [23..16] Compare Match 1 Value                                            */
      __IM  uint32_t RESERVED1  : 8;
    } bit;
  } MDATAM;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000048) Master Clock Configure Register 0                          */

    struct {
      __IOM uint32_t SCLLC      : 6;            /* [5..0] SCL Low Cycles                                                     */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t SCLHC      : 6;            /* [13..8] SCL High Cycles                                                   */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t SETUPT     : 6;            /* [21..16] Minimum Number of Cycles of Setup Time                           */
      __IM  uint32_t RESERVED2  : 2;
      __IOM uint32_t SDAHT      : 6;            /* [29..24] Minimum Cycle of SDA Hold Time                                   */
      __IM  uint32_t RESERVED3  : 2;
    } bit;
  } MCLKCFG0;
  __IM  uint32_t  RESERVED3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000050) Master Clock Configure Register 1                          */

    struct {
      __IOM uint32_t SCLLC      : 6;            /* [5..0] SCL Low Cycles                                                     */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t SCLHC      : 6;            /* [13..8] SCL High Cycles                                                   */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t SETUPT     : 6;            /* [21..16] Minimum Number of Cycles of Setup Time                           */
      __IM  uint32_t RESERVED2  : 2;
      __IOM uint32_t SDAHT      : 6;            /* [29..24] Minimum Cycle of SDA Hold Time                                   */
      __IM  uint32_t RESERVED3  : 2;
    } bit;
  } MCLKCFG1;
  __IM  uint32_t  RESERVED4;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000058) Master FIFO Control Register                               */

    struct {
      __IOM uint32_t TXFW       : 2;            /* [1..0] Transmit FIFO Watermark                                            */
      __IM  uint32_t RESERVED0  : 14;
      __IOM uint32_t RXFW       : 2;            /* [17..16] Receive FIFO Watermark                                           */
      __IM  uint32_t RESERVED1  : 14;
    } bit;
  } MFCTRL;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000005C) Master FIFO Status Register                                */

    struct {
      __IM  uint32_t TXCNT      : 3;            /* [2..0] Transmit FIFO Count                                                */
      __IM  uint32_t RESERVED0  : 13;
      __IM  uint32_t RXCNT      : 3;            /* [18..16] Receive FIFO Count                                               */
      __IM  uint32_t RESERVED1  : 13;
    } bit;
  } MFSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000060) Master Transmit Data Register                              */

    struct {
      __OM  uint32_t TXDATA     : 8;            /* [7..0] Transmit Data                                                      */
      __OM  uint32_t CMD        : 3;            /* [10..8] Command                                                           */
      __IM  uint32_t RESERVED0  : 21;
    } bit;
  } MTXDATA;
  __IM  uint32_t  RESERVED5[3];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000070) Master Receive Data Register                               */

    struct {
      __IM  uint32_t RXDATA     : 8;            /* [7..0] Read Undiscarded Received Data                                     */
      __IM  uint32_t RESERVED0  : 6;
      __IM  uint32_t RXFE       : 1;            /* [14..14] Receive FIFO Empty                                               */
      __IM  uint32_t RESERVED1  : 17;
    } bit;
  } MRXDATA;
  __IM  uint32_t  RESERVED6[39];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000110) Slave Control Register                                     */

    struct {
      __IOM uint32_t SMEN       : 1;            /* [0..0] Slave Mode Enable                                                  */
      __IOM uint32_t SRST       : 1;            /* [1..1] Slave Logic Software Reset                                         */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t SMFEN      : 1;            /* [4..4] Slave Mode Filter Enable                                           */
      __IOM uint32_t FDDM       : 1;            /* [5..5] Filter Disabled in Doze Mode                                       */
      __IM  uint32_t RESERVED1  : 2;
      __OM  uint32_t TXFRST     : 1;            /* [8..8] Transmit FIFO Reset                                                */
      __OM  uint32_t RXFRST     : 1;            /* [9..9] Receive FIFO Reset                                                 */
      __IM  uint32_t RESERVED2  : 22;
    } bit;
  } SCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000114) Slave Status Register                                      */

    struct {
      __IM  uint32_t TXFLG      : 1;            /* [0..0] Transmit Data Flag                                                 */
      __IM  uint32_t RXFLG      : 1;            /* [1..1] Receive Data Flag                                                  */
      __IM  uint32_t AVFLG      : 1;            /* [2..2] Address Status Register Valid Flag                                 */
      __IM  uint32_t TAFLG      : 1;            /* [3..3] Transmit ACK/NACK Flag                                             */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t RSFLG      : 1;            /* [8..8] Repeated Start Flag                                                */
      __IOM uint32_t STOPFLG    : 1;            /* [9..9] STOP Detect Flag                                                   */
      __IOM uint32_t BEFLG      : 1;            /* [10..10] Bit Error Flag                                                   */
      __IOM uint32_t FEFLG      : 1;            /* [11..11] FIFO Error Flag                                                  */
      __IM  uint32_t A0MFLG     : 1;            /* [12..12] Address 0 Match Address Flag                                     */
      __IM  uint32_t A1MFLG     : 1;            /* [13..13] Address 1 Match Address Flag                                     */
      __IM  uint32_t GCAFLG     : 1;            /* [14..14] General Call Address Flag                                        */
      __IM  uint32_t SARFLG     : 1;            /* [15..15] SMBus Alert Response Flag                                        */
      __IM  uint32_t RESERVED1  : 8;
      __IM  uint32_t SBSYFLG    : 1;            /* [24..24] LPI2C Slave Busy Flag                                              */
      __IM  uint32_t BBSYFLG    : 1;            /* [25..25] LPI2C Bus Busy Flag                                                */
      __IM  uint32_t RESERVED2  : 6;
    } bit;
  } SSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000118) Slave Interrupt Enable Register                            */

    struct {
      __IOM uint32_t TXIEN      : 1;            /* [0..0] Transmit Data Interrupt Enable                                     */
      __IOM uint32_t RXIEN      : 1;            /* [1..1] Receive Data Interrupt Enable                                      */
      __IOM uint32_t AVIEN      : 1;            /* [2..2] Address Valid Interrupt Enable                                     */
      __IOM uint32_t TAIEN      : 1;            /* [3..3] Transmit ACK/NACK Interrupt Enable                                 */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t RSIEN      : 1;            /* [8..8] Slave Repeated Start Interrupt Enable                              */
      __IOM uint32_t STOPIEN    : 1;            /* [9..9] Slave STOP Detect Interrupt Enable                                 */
      __IOM uint32_t BEIEN      : 1;            /* [10..10] Slave Bit Error Interrupt En                                     */
      __IOM uint32_t FEIEN      : 1;            /* [11..11] FIFO Error Enable                                                */
      __IOM uint32_t A0MIEN     : 1;            /* [12..12] Address 0 Match Address Interrupt Enable                         */
      __IOM uint32_t A1MIEN     : 1;            /* [13..13] Address 1 Match Address Interrupt Enable                         */
      __IOM uint32_t GCAIEN     : 1;            /* [14..14] General Call Interrupt Enable                                    */
      __IOM uint32_t SARIEN     : 1;            /* [15..15] SMBus Alert Interrupt Enable                                     */
      __IM  uint32_t RESERVED1  : 16;
    } bit;
  } SINTEN;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000011C) Slave DMA Enable Register                                  */

    struct {
      __IOM uint32_t TXDMAEN    : 1;            /* [0..0] Transmit Data DMA Enable                                           */
      __IOM uint32_t RXDMAEN    : 1;            /* [1..1] Receive Data DMA Enable                                            */
      __IOM uint32_t AVDMAEN    : 1;            /* [2..2] Address Valid DMA Enable                                           */
      __IM  uint32_t RESERVED0  : 29;
    } bit;
  } SDMAEN;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000124) Slave Configure Register 1                                 */

    struct {
      __IOM uint32_t ADDRSEN    : 1;            /* [0..0] Address SCL Stall Enable                                           */
      __IOM uint32_t RXDSEN     : 1;            /* [1..1] Receive Data SCL Stall Enable                                      */
      __IOM uint32_t TXDSEN     : 1;            /* [2..2] Transmit Data SCL Stall Enable                                     */
      __IOM uint32_t ACKSEN     : 1;            /* [3..3] ACK SCL Stall Enable                                               */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t GCAEN      : 1;            /* [8..8] General Call Address Enable                                        */
      __IOM uint32_t SAMEN      : 1;            /* [9..9] SMBus Alert Match Enable                                           */
      __IOM uint32_t TXFCFG     : 1;            /* [10..10] Transmit Data Flag Configure                                     */
      __IOM uint32_t RXFCFG     : 1;            /* [11..11] Receive Data Flag Configure                                      */
      __IOM uint32_t INACK      : 1;            /* [12..12] Ignore NACK                                                      */
      __IOM uint32_t HSMDEN     : 1;            /* [13..13] High Speed Mode Detection Enable                                 */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t ADDRMCFG   : 3;            /* [18..16] Address Match Configure                                          */
      __IM  uint32_t RESERVED2  : 13;
    } bit;
  } SCFG1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000128) Slave Configure Register 2                                 */

    struct {
      __IOM uint32_t CLKHLDCFG  : 4;            /* [3..0] Clock Hold Time Configure                                          */
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t DVDCFG     : 6;            /* [13..8] Data Valid Delay Configure                                        */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t SCLFCFG    : 4;            /* [19..16] SCL Glitch Fliter Configure                                      */
      __IM  uint32_t RESERVED2  : 4;
      __IOM uint32_t SDAFCFG    : 4;            /* [27..24] SDA Glitch Filter Configure                                      */
      __IM  uint32_t RESERVED3  : 4;
    } bit;
  } SCFG2;
  __IM  uint32_t  RESERVED8[5];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000140) Slave Address Match Register                               */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t A0CV       : 10;           /* [10..1] Address0 Compare 0 Value                                          */
      __IM  uint32_t RESERVED1  : 6;
      __IOM uint32_t A1CV       : 10;           /* [26..17] Address1 Compare 1 Value                                         */
      __IM  uint32_t RESERVED2  : 5;
    } bit;
  } SADDRM;
  __IM  uint32_t  RESERVED9[3];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000150) Slave Address Status Register                              */

    struct {
      __IM  uint32_t RXADDR     : 11;           /* [10..0] Received Address                                                  */
      __IM  uint32_t RESERVED0  : 3;
      __IM  uint32_t RXADDRNV   : 1;            /* [14..14] Received Address Not Vaild                                       */
      __IM  uint32_t RESERVED1  : 17;
    } bit;
  } SADDRSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000154) Slave Transmit ACK Register                                */

    struct {
      __IOM uint32_t TXNACK     : 1;            /* [0..0] Write a Transmit NACK                                              */
      __IM  uint32_t RESERVED0  : 31;
    } bit;
  } STXACK;
  __IM  uint32_t  RESERVED10[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000160) Slave Transmit Data Register                               */

    struct {
      __OM  uint32_t TXDATA     : 8;            /* [7..0] Slave Transmit Data                                                */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } STXDATA;
  __IM  uint32_t  RESERVED11[3];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000170) Slave Receive Data Register                                */

    struct {
      __IM  uint32_t RXDATA     : 8;            /* [7..0] Slave Received Data                                                */
      __IM  uint32_t RESERVED0  : 6;
      __IM  uint32_t RXDE       : 1;            /* [14..14] Receive Data Register Empty                                      */
      __IM  uint32_t FDW        : 1;            /* [15..15] First Data Word                                                  */
      __IM  uint32_t RESERVED1  : 16;
    } bit;
  } SRXDATA;
} LPI2C_T;                                   /* Size = 372 (0x174)                                                        */



/* =========================================================================================================================== */
/* ================                                          LPUART                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Low-power Universal asynchronous receiver/transmitters (LPUART)
  */

typedef struct {                                /*  LPUART Structure
                                                    (@ 0x4006A000)LPUART0 (@ 0x4006B000)LPUART1 (@ 0x4006C000)LPUART2        */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Number                                                    */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t TXFSSET    : 8;            /* [7..0] Transmit FIFO Size Set                                             */
      __IM  uint32_t RXFSSET    : 8;            /* [15..8] Receive FIFO Size Set                                             */
      __IM  uint32_t RESERVED0  : 16;
    } bit;
  } PARA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) LPUART Software Reset Register                             */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t SWRSTEN    : 1;            /* [1..1] Software Reset Enable                                              */
      __IM  uint32_t RESERVED1  : 30;
    } bit;
  } SWRST;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) LPUART Pin Configuration Register                          */

    struct {
      __IOM uint32_t ITRGCFG    : 2;            /* [1..0] Input Trigger Configure                                            */
      __IM  uint32_t RESERVED0  : 30;
    } bit;
  } PCFG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) LPUART Baud Rate Register                                  */

    struct {
      __IOM uint32_t BRMD       : 13;           /* [12..0] Baud Rate Modulo Divisor                                          */
      __IOM uint32_t STOPBSEL   : 1;            /* [13..13] Stop Bit Select                                                  */
      __IOM uint32_t RXIAEIEN   : 1;            /* [14..14] Receive Input Active Edge Interrupt Enable                       */
      __IOM uint32_t LBDFIEN    : 1;            /* [15..15] LIN Break Detect Flag Interrupt Enable                           */
      __IOM uint32_t RXDWRDIS   : 1;            /* [16..16] Received Data Word Resynchronization Disable                     */
      __IOM uint32_t BEDSMPSEL  : 1;            /* [17..17] Both Edge Sampling Mode Select                                   */
      __IOM uint32_t MADDRMCFG  : 2;            /* [19..18] Match Addressing Mode Configure                                  */
      __IOM uint32_t RXIDMAREN  : 1;            /* [20..20] Receiver Idle DMA Request Enable                                 */
      __IOM uint32_t RXFDMAREN  : 1;            /* [21..21] Receiver Full DMA Request Enable                                 */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t TXDMAREN   : 1;            /* [23..23] Transmitter DMA Request Enable                                   */
      __IOM uint32_t OSRCFG     : 5;            /* [28..24] Oversampling Ratio Configure                                     */
      __IOM uint32_t SELM10     : 1;            /* [29..29] 10-bit Mode Select                                               */
      __IOM uint32_t MADDREN2   : 1;            /* [30..30] Match Address 2 Mode Enable                                      */
      __IOM uint32_t MADDREN1   : 1;            /* [31..31] Match Address 1 Mode Enable                                      */
    } bit;
  } BR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) LPUART Status Register                                     */

    struct {
      __IM  uint32_t RESERVED0  : 14;
      __IOM uint32_t RXDMFLG2   : 1;            /* [14..14] Received Data Match 2 Flag                                       */
      __IOM uint32_t RXDMFLG1   : 1;            /* [15..15] Received Data Match 1 Flag                                       */
      __IOM uint32_t PEFLG      : 1;            /* [16..16] Parity Error Flag                                                */
      __IOM uint32_t FEFLG      : 1;            /* [17..17] Fram Error Flag                                                  */
      __IOM uint32_t NEFLG      : 1;            /* [18..18] Noise Flag                                                       */
      __IOM uint32_t OVREFLG    : 1;            /* [19..19] Overrun Error Flag                                               */
      __IOM uint32_t IDLEFLG    : 1;            /* [20..20] Idle Line Detected Flag                                          */
      __IM  uint32_t RXBFFLG    : 1;            /* [21..21] Receive Data Buffer full Flag                                    */
      __IM  uint32_t TXCFLG     : 1;            /* [22..22] Transmission data Complete Flag                                  */
      __IM  uint32_t TXBEFLG    : 1;            /* [23..23] Transmit Data Buffer Empty Flag                                  */
      __IM  uint32_t RXDINIFLG  : 1;            /* [24..24] RXD Input Not Idle Flag                                          */
      __IOM uint32_t LBDEN      : 1;            /* [25..25] LIN Break Detection Enable                                       */
      __IOM uint32_t BCTXLEN    : 1;            /* [26..26] Break Character Transmission Length                              */
      __IOM uint32_t RXWUPID    : 1;            /* [27..27] Receive Wake Up Idle Detect                                      */
      __IOM uint32_t RXDIPINV   : 1;            /* [28..28] Received Data Input Polarity Inversion                           */
      __IOM uint32_t MSBFSET    : 1;            /* [29..29] MSB First Set                                                    */
      __IOM uint32_t AERXPFLG   : 1;            /* [30..30] Active Edge on Receive Pin Flag                                  */
      __IOM uint32_t LBDFLG     : 1;            /* [31..31] LIN Break Detected Flag                                          */
    } bit;
  } STS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) LPUART Control Register                                    */

    struct {
      __IOM uint32_t PTCFG      : 1;            /* [0..0] Parity Type Configure                                              */
      __IOM uint32_t PENCFG      : 1;            /* [1..1] Parity Enable Configure                                            */
      __IOM uint32_t ITSEL      : 1;            /* [2..2] Idle Type Select                                                   */
      __IOM uint32_t RXWAKESEL  : 1;            /* [3..3] Receiver Wakeup Method Select                                      */
      __IOM uint32_t RXTXCSEL   : 1;            /* [4..4] Receiver and Transmit Character Select                             */
      __IOM uint32_t RXISRCSEL  : 1;            /* [5..5] Receiver Input Source Select                                       */
      __IOM uint32_t DOZEMODEEN : 1;            /* [6..6] Doze Mode Enable                                                   */
      __IOM uint32_t LSWSEL     : 1;            /* [7..7] Loop Mode or Single-wire Mode Select                               */
      __IOM uint32_t IDLECCFG   : 3;            /* [10..8] Idle Character Configure                                          */
      __IOM uint32_t RXTXSELM7  : 1;            /* [11..11] Receiver and Transmit Select 7-bit Mode                          */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t FIENM2     : 1;            /* [14..14] Match 2 Flag Interrupt Enable                                    */
      __IOM uint32_t FIENM1     : 1;            /* [15..15] Match 1 Flag Interrupt Enable                                    */
      __IOM uint32_t TXBK       : 1;            /* [16..16] Transmit Break                                                   */
      __IOM uint32_t RXWUPCTRL  : 1;            /* [17..17] Receiver Wakeup Control                                          */
      __IOM uint32_t RXEN       : 1;            /* [18..18] LPUART Receiver Enable                                           */
      __IOM uint32_t TXEN       : 1;            /* [19..19] LPUART Transmitter Enable                                        */
      __IOM uint32_t IDLEIEN    : 1;            /* [20..20] Idle Line Interrupt Enable                                       */
      __IOM uint32_t RXIEN      : 1;            /* [21..21] Receiver Interrupt Enable                                        */
      __IOM uint32_t TXCIEN     : 1;            /* [22..22] Transmission Complete Interrupt Enable                           */
      __IOM uint32_t TXIEN      : 1;            /* [23..23] Transmit Interrupt Enable                                        */
      __IOM uint32_t PEIEN      : 1;            /* [24..24] Parity Error Interrupt Enable                                    */
      __IOM uint32_t FEIEN      : 1;            /* [25..25] Framing Error Interrupt Enable                                   */
      __IOM uint32_t NEIEN      : 1;            /* [26..26] Noise Error Interrupt Enable                                     */
      __IOM uint32_t OVRIEN     : 1;            /* [27..27] Overrun Interrupt Enable                                         */
      __IOM uint32_t TXDOPINV   : 1;            /* [28..28] Transmit Data Output Polarity Inversion                          */
      __IOM uint32_t TXDPDIRSEL : 1;            /* [29..29] TXD Pin Direction in Single-Wire Mode Select                     */
      __IOM uint32_t RX9TX8     : 1;            /* [30..30] Receive Data Bit 9 / Transmit Data Bit 8                         */
      __IOM uint32_t RX8TX9     : 1;            /* [31..31] Receive Data Bit 8 / Transmit Data Bit 9                         */
    } bit;
  } CTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) LPUART Data Register                                       */

    struct {
      __IOM uint32_t RX0TX0     : 1;            /* [0..0] Rx Buffer 0 or Tx Buffer 0                                         */
      __IOM uint32_t RX1TX1     : 1;            /* [1..1] Rx Buffer 1 or Tx Buffer 1                                         */
      __IOM uint32_t RX2TX2     : 1;            /* [2..2] Rx Buffer 2 or Tx Buffer 2                                         */
      __IOM uint32_t RX3TX3     : 1;            /* [3..3] Rx Buffer 3 or Tx Buffer 3                                         */
      __IOM uint32_t RX4TX4     : 1;            /* [4..4] Rx Buffer 4 or Tx Buffer 4                                         */
      __IOM uint32_t RX5TX5     : 1;            /* [5..5] Rx Buffer 5 or Tx Buffer 5                                         */
      __IOM uint32_t RX6TX6     : 1;            /* [6..6] Rx Buffer 6 or Tx Buffer 6                                         */
      __IOM uint32_t RX7TX7     : 1;            /* [7..7] Rx Buffer 7 or Tx Buffer 7                                         */
      __IOM uint32_t RX8TX8     : 1;            /* [8..8] Rx Buffer 8 or Tx Buffer 8                                         */
      __IOM uint32_t RX9TX9     : 1;            /* [9..9] Rx Buffer 9 or Tx Buffer 9                                         */
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t RXIDLE     : 1;            /* [11..11] Receiver Idle Line                                               */
      __IM  uint32_t RXBE       : 1;            /* [12..12] Receive Buffer Empty                                             */
      __IOM uint32_t FETXSC     : 1;            /* [13..13] Frame Error or Transmit Special Character                        */
      __IM  uint32_t PE         : 1;            /* [14..14] Parity Error                                                     */
      __IM  uint32_t NE         : 1;            /* [15..15] Noise Error                                                      */
      __IM  uint32_t RESERVED1  : 16;
    } bit;
  } DATA;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) LPUART Match Address Register                              */

    struct {
      __IOM uint32_t MADDR1     : 10;           /* [9..0] Match Address 1                                                    */
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t MADDR2     : 10;           /* [25..16] Match Address 2                                                  */
      __IM  uint32_t RESERVED1  : 6;
    } bit;
  } MADDR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000024) LPUART Modem IrDA Register                                 */

    struct {
      __IOM uint32_t TXCSEN     : 1;            /* [0..0] Transmitter Clear-to-Send Enable                                   */
      __IOM uint32_t TXRSEN     : 1;            /* [1..1] Transmitter Request-to-Send Enable                                 */
      __IOM uint32_t TXRSPCFG   : 1;            /* [2..2] Transmitter Request-to-Send Polarity Configure                     */
      __IOM uint32_t RXRSEN     : 1;            /* [3..3] Receiver Request-to-Send Enable                                    */
      __IOM uint32_t TXCSCFG    : 1;            /* [4..4] Transmit CTS Sample Configure                                      */
      __IOM uint32_t TXCSRCSEL  : 1;            /* [5..5] Transmit CTS Source Select                                         */
      __IM  uint32_t RESERVED0  : 2;
      __IOM uint32_t RXROCFG    : 2;            /* [9..8] Receive RTS Output Configure                                       */
      __IM  uint32_t RESERVED1  : 6;
      __IOM uint32_t TXNPCFG    : 2;            /* [17..16] Transmitter Narrow Pulse Configure                               */
      __IOM uint32_t IRMODEEN   : 1;            /* [18..18] Infrared Modulation/Demodulation Enable                          */
      __IM  uint32_t RESERVED2  : 13;
    } bit;
  } MIR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000028) LPUART FIFO Register                                       */

    struct {
      __IM  uint32_t RXFBDCFG   : 3;            /* [2..0] Receive FIFO Buffer Depth Configure                                */
      __IOM uint32_t RXBFEN     : 1;            /* [3..3] Receive Buffer FIFO Enable                                         */
      __IM  uint32_t TXFBDCFG   : 3;            /* [6..4] Transmit FIFO Buffer Depth Configure                               */
      __IOM uint32_t TXBFEN     : 1;            /* [7..7] Transmit Buffer FIFO Enable                                        */
      __IOM uint32_t RXUFGINT   : 1;            /* [8..8] RX Buffer Underflow Flag Generate Interrupt                        */
      __IOM uint32_t TXOFGINT   : 1;            /* [9..9] TX Buffer Overflow Flag Generate Interrupt                         */
      __IOM uint32_t CFGRXIEEN  : 3;            /* [12..10] Configures when the Receiver is Idle Empty Enable                */
      __IM  uint32_t RESERVED0  : 1;
      __OM  uint32_t RXFBDFLU   : 1;            /* [14..14] Receive FIFO/Buffer Data Flush                                   */
      __OM  uint32_t TXFBDFLU   : 1;            /* [15..15] Transmit FIFO/Buffer Data Flush                                  */
      __IOM uint32_t RXBUFLG    : 1;            /* [16..16] Receiver Buffer Underflow Occured Flag                           */
      __IOM uint32_t TXBOFLG    : 1;            /* [17..17] Transmitter Buffer Overflow Occured Flag                         */
      __IM  uint32_t RESERVED1  : 4;
      __IM  uint32_t RXBE       : 1;            /* [22..22] Receive Buffer Empty                                             */
      __IM  uint32_t TXBE       : 1;            /* [23..23] Transmit Buffer Empty                                            */
      __IM  uint32_t RESERVED2  : 8;
    } bit;
  } FIFO;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000002C) LPUART Watermark Register                                  */

    struct {
      __IOM uint32_t TXWAT      : 2;            /* [1..0] Transmit Watermark                                                 */
      __IM  uint32_t RESERVED0  : 6;
      __IM  uint32_t TXFBUFCNT  : 3;            /* [10..8] Transmit FIFO/Buffer Counter                                      */
      __IM  uint32_t RESERVED1  : 5;
      __IOM uint32_t RXWAT      : 2;            /* [17..16] Receive Watermark                                                */
      __IM  uint32_t RESERVED2  : 6;
      __IM  uint32_t RXFBUFCNT  : 3;            /* [26..24] Receive FIFO/Buffer Counter                                      */
      __IM  uint32_t RESERVED3  : 5;
    } bit;
  } WMKR;
} LPUART_T;                                 /* Size = 48 (0x30)                                                              */



/* =========================================================================================================================== */
/* ================                                           COMP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog Comparators (COMP)
  */

typedef struct {                                /* (@ 0x40073000) COMP Structure                                             */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) COMP Control Register 0                                    */

    struct {
      __IOM uint32_t HBHLSEL    : 2;            /* [1..0] Hard Block Hysteresis Level Select                                 */
      __IOM uint32_t HBOLSEL    : 1;            /* [2..2] Hard Block Offset Level Select                                     */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t FOSMPCNT   : 3;            /* [6..4] Filter Output Sample Count                                         */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t ACEN       : 1;            /* [8..8] Analog Comparator Enable                                           */
      __IOM uint32_t COPCFG     : 1;            /* [9..9] Comparator Output Pin Configure                                    */
      __IOM uint32_t COCFG      : 1;            /* [10..10] Comparator Output Configure                                      */
      __IOM uint32_t INVEN      : 1;            /* [11..11] Invert Enable                                                    */
      __IOM uint32_t PMSEL      : 1;            /* [12..12] Power Mode Select                                                */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t WINMEN     : 1;            /* [14..14] Windowing Mode Enable                                            */
      __IOM uint32_t SMPMEN     : 1;            /* [15..15] Sample Mode Enable                                               */
      __IOM uint32_t FSMPPCFG   : 8;            /* [23..16] Filter Sample Period Configure                                   */
      __IM  uint32_t ACO        : 1;            /* [24..24] Analog Comparator Output                                         */
      __IOM uint32_t ACFFLG     : 1;            /* [25..25] Analog Comparator Falling Flag                                   */
      __IOM uint32_t ACRFLG     : 1;            /* [26..26] Analog Comparator Rising Flag                                    */
      __IOM uint32_t ACFIEN     : 1;            /* [27..27] Analog Comparator Falling Interrupt Enable                       */
      __IOM uint32_t ACRIEN     : 1;            /* [28..28] Analog Comparator Rising Interrupt Enable                        */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t DMAEN      : 1;            /* [30..30] DMA Enable                                                       */
      __IM  uint32_t RESERVED4  : 1;
    } bit;
  } CTRL0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) COMP Control Register 1                                    */

    struct {
      __IOM uint32_t DACOVCFG   : 8;            /* [7..0] DAC Output Voltage Configure                                       */
      __IOM uint32_t MUXMICSEL  : 3;            /* [10..8] Minus Input MUX Select                                            */
      __IOM uint32_t MUXPICSEL  : 3;            /* [13..11] Plus Input MUX Select                                            */
      __IOM uint32_t SVRSSEL    : 1;            /* [14..14] Supply Voltage Reference Source Select                           */
      __IOM uint32_t DACEN      : 1;            /* [15..15] DAC Enable                                                       */
      __IOM uint32_t INENCH0    : 1;            /* [16..16] Channel 0 input enable                                           */
      __IOM uint32_t INENCH1    : 1;            /* [17..17] Channel 1 input enable                                           */
      __IOM uint32_t INENCH2    : 1;            /* [18..18] Channel 2 input enable                                           */
      __IOM uint32_t INENCH3    : 1;            /* [19..19] Channel 3 input enable                                           */
      __IOM uint32_t INENCH4    : 1;            /* [20..20] Channel 4 input enable                                           */
      __IOM uint32_t INENCH5    : 1;            /* [21..21] Channel 5 input enable                                           */
      __IOM uint32_t INENCH6    : 1;            /* [22..22] Channel 6 input enable                                           */
      __IOM uint32_t INENCH7    : 1;            /* [23..23] Channel 7 input enable                                           */
      __IOM uint32_t CNISEL     : 2;            /* [25..24] Comparator Negative Input Select                                 */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t CPISEL     : 2;            /* [28..27] Comparator Positive Input Select                                 */
      __IM  uint32_t RESERVED1  : 3;
    } bit;
  } CTRL1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) COMP Control Register 2                                    */

    struct {
      __IOM uint32_t CRETCHn    : 8;            /* [7..0] Input Comparison Result of Channel n                               */
      __IOM uint32_t IDCLKCFG   : 6;            /* [13..8] Initialization Delay Clock Configure                              */
      __IOM uint32_t NSCFG      : 2;            /* [15..14] Number of Sample Clocks Configure                                */
      __IOM uint32_t ICFLGCH0   : 1;            /* [16..16] Channel 0 input changed flag                                     */
      __IOM uint32_t ICFLGCH1   : 1;            /* [17..17] Channel 1 input changed flag                                     */
      __IOM uint32_t ICFLGCH2   : 1;            /* [18..18] Channel 2 input changed flag                                     */
      __IOM uint32_t ICFLGCH3   : 1;            /* [19..19] Channel 3 input changed flag                                     */
      __IOM uint32_t ICFLGCH4   : 1;            /* [20..20] Channel 4 input changed flag                                     */
      __IOM uint32_t ICFLGCH5   : 1;            /* [21..21] Channel 5 input changed flag                                     */
      __IOM uint32_t ICFLGCH6   : 1;            /* [22..22] Channel 6 input changed flag                                     */
      __IOM uint32_t ICFLGCH7   : 1;            /* [23..23] Channel 7 input changed flag                                     */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t MUXFCHSEL  : 3;            /* [27..25] Fixed MUX Channel Select                                         */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t MUXFPSEL   : 1;            /* [29..29] Fixed MUX Port Select                                            */
      __IOM uint32_t RRIEN      : 1;            /* [30..30] Round-Robin Interrupt Enable                                     */
      __IOM uint32_t RRSEL      : 1;            /* [31..31] Round-Robin Select                                               */
    } bit;
  } CTRL2;
} COMP_T;                                    /* Size = 12 (0xc)                                                              */



/* =========================================================================================================================== */
/* ================                                            PMU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Power management unit (PMU)
  */

typedef struct {                                /* (@ 0x4007D000) PMU Structure                                              */

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000000) Low Voltage Detect Control and Status1 Register            */

    struct {
            uint8_t             : 4;
      __IOM uint8_t LVDEGSYSREN : 1;            /* [4..4] Low-Voltage Detect Event Generation System Reset Enable            */
      __OM  uint8_t LVDHWINTREN : 1;            /* [5..5] Low-Voltage Warning Error Acknowledge                              */
      __OM  uint8_t LVDERRACK   : 1;            /* [6..6] Low-Voltage Warning Error Acknowledge                              */
      __IM  uint8_t LVDEFLG     : 1;            /* [7..7] Low-Voltage Warning Event Flag                                     */
    } bit;
  } LVDCSTS1;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000001) Low Voltage Detect Control and Status2 Register            */

    struct {
            uint8_t             : 5;
      __IOM uint8_t LVWHWINTREN : 1;            /* [5..5] Low-Voltage Warning Hardware Interrupt Enable                      */
      __OM  uint8_t LVWERRACK   : 1;            /* [6..6] Low-Voltage Warning Error Acknowledge                              */
      __IM  uint8_t LVWEFLG     : 1;            /* [7..7] Low-Voltage Warning Event Flag                                     */
    } bit;
  } LVDCSTS2;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000002) Regulator Control and Status Register                      */

    struct {
      __IOM uint8_t BEN         : 1;            /* [0..0] Bias Enable                                                        */
      __IOM uint8_t CLKBDIS     : 1;            /* [1..1] Clock Bias Disable                                                 */
      __IM  uint8_t RFPMSTS     : 1;            /* [2..2] Regulator in Full Performance Mode Status                          */
            uint8_t             : 3;
      __IM  uint8_t LPOCLKSTS   : 1;            /* [6..6] LPO Clock Status                                                   */
      __IOM uint8_t LPODIS      : 1;            /* [7..7] LPO Disable                                                        */
    } bit;
  } REGCSTS;
  __IM  uint8_t   RESERVED;

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000004) Low Power Oscillator Trim Register                         */

    struct {
      __IOM uint8_t TLPOF     : 5;            /* [4..0] Trimming Low Power Oscillator Frequency                            */
            uint8_t             : 3;
    } bit;
  } LPOSCTRIM;
} PMU_T;                                     /* Size = 5 (0x5)                                                               */



/* =========================================================================================================================== */
/* ================                                           SYSMC                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief System Mode Controller (SYSMC)
  */

typedef struct {                                /* (@ 0x4007E000) SYSMC Structure                                            */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature Number                                                    */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version Number                                             */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version Number                                             */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Feature Register                                           */

    struct {
      __IM  uint32_t HSRUNAVA   : 1;            /* [0..0] HSRUN Feature Available                                            */
      __IM  uint32_t RESERVED0  : 2;
      __IM  uint32_t LLSAVA     : 1;            /* [3..3] LLS Feature Available                                              */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t LLS2AVA    : 1;            /* [5..5] LLS2 Feature Available                                             */
      __IM  uint32_t VLLS0AVA   : 1;            /* [6..6] VLLS0 Feature Available                                            */
      __IM  uint32_t RESERVED2  : 25;
    } bit;
  } FEATURE;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Power Mode Protection register                             */

    struct {
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t ALLOWLP    : 1;            /* [5..5] Allow MCU Enter Very Low Power Mode                                */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t ALLOWHS    : 1;            /* [7..7] Allow MCU Enter High-Speed Run Mode                                */
      __IM  uint32_t RESERVED2  : 24;
    } bit;
  } PMPRO;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Power Mode Control register                                */

    struct {
      __IOM uint32_t STOPCTRL   : 3;            /* [2..0] Stop Mode Control                                                  */
      __IM  uint32_t VLPSEA     : 1;            /* [3..3] Very Low Power Stop Mode Entry Aborted                             */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t RUNCTRL    : 2;            /* [6..5] Run Mode Control                                                   */
      __IM  uint32_t RESERVED1  : 25;
    } bit;
  } PMCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) Stop Operation Select Register                             */

    struct {
      __IM  uint32_t RESERVED0  : 6;
      __IOM uint32_t STOPOSEL   : 2;            /* [7..6] Stop Operation Select                                              */
      __IM  uint32_t RESERVED1  : 24;
    } bit;
  } STOPOSEL;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000014) Power Mode Status register                                 */

    struct {
      __IM  uint32_t PMSTS      : 8;            /* [7..0] Power Mode Status                                                  */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } PMSTS;
} SYSMC_T;                                   /* Size = 24 (0x18)                                                             */



/* =========================================================================================================================== */
/* ================                                            RMU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Reset Management unit (RMU)
  */

typedef struct {                                /* (@ 0x4007F000) RMU Structure                                              */

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000000) Version ID Register                                        */

    struct {
      __IM  uint32_t FEATURE    : 16;           /* [15..0] Feature ID                                                        */
      __IM  uint32_t MINOR      : 8;            /* [23..16] Minor Version ID                                                 */
      __IM  uint32_t MAJOR      : 8;            /* [31..24] Major Version ID                                                 */
    } bit;
  } VERID;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000004) Parameter Register                                         */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t LVDRSTSTS  : 1;            /* [1..1] Low Voltage Detection Reset Function Status                        */
      __IM  uint32_t CLKLRSTSTS : 1;            /* [2..2] Clock Loss Reset Function Status                                   */
      __IM  uint32_t LOCKLRSTSTS : 1;           /* [3..3] Lock Loss Reset Function Status                                    */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t WDTRSTSTS  : 1;            /* [5..5] Watchdog Timer Reset Function Status                               */
      __IM  uint32_t ERSTSTS    : 1;            /* [6..6] External Pin Reset Function Status                                 */
      __IM  uint32_t PORRSTSTS  : 1;            /* [7..7] POR Reset Function Status                                          */
      __IM  uint32_t JTAGRSTSTS : 1;            /* [8..8] JTAG Reset Function Status                                         */
      __IM  uint32_t CLOCKRSTSTS : 1;           /* [9..9] Core Lockup Reset Function Status                                  */
      __IM  uint32_t SWRSTSTS   : 1;            /* [10..10] Software Reset Function Status                                   */
      __IM  uint32_t SRSTSTS    : 1;            /* [11..11] System Reset Function Status                                     */
      __IM  uint32_t RESERVED2  : 1;
      __IM  uint32_t STOPACKERSTSTS : 1;        /* [13..13] Stop Acknowledge Error Reset Function Status                     */
      __IM  uint32_t RESERVED3  : 18;
    } bit;
  } PARA;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000008) Reset Status Register                                      */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t LVDRSTFLG  : 1;            /* [1..1] Low Voltage Detection Reset Flag                                   */
      __IM  uint32_t CLKLRSTFLG : 1;            /* [2..2] Clock Loss Reset Flag                                              */
      __IM  uint32_t LOCKLRSTFLG : 1;           /* [3..3] Lock Loss Reset Flag                                               */
      __IM  uint32_t RESERVED1  : 1;
      __IM  uint32_t WDTTOFFLG  : 1;            /* [5..5] Watchdog Timer Timeout Flag                                        */
      __IM  uint32_t ERSTPFLG   : 1;            /* [6..6] External Reset Pin Flag                                            */
      __IM  uint32_t PORFLG     : 1;            /* [7..7] POR Flag                                                           */
      __IM  uint32_t JTAGRSTFLG : 1;            /* [8..8] JTAG Reset Flag                                                    */
      __IM  uint32_t CLOCKEFLG  : 1;            /* [9..9] Core Lockup Event Flag                                             */
      __IM  uint32_t SWSETFLG   : 1;            /* [10..10] Software Set Flag                                                */
      __IM  uint32_t SRSTREQFLG : 1;            /* [11..11] System Reset Request Flag                                        */
      __IM  uint32_t RESERVED2  : 1;
      __IM  uint32_t STOPACKEFLG : 1;           /* [13..13] Stop Acknowledge Error Flag                                      */
      __IM  uint32_t RESERVED3  : 18;
    } bit;
  } RSTFLG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Reset Pin Control register                                 */

    struct {
      __IOM uint32_t RSTPFSEL   : 2;            /* [1..0] Reset Pin Filter Select in Run and Wait Modes                      */
      __IOM uint32_t RSTPFEN    : 1;            /* [2..2] Reset Pin Filter Enable in Stop Mode                               */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t RSTPBCLKWSEL : 5;          /* [12..8] Reset Pin Bus Clock Filter Width Select                           */
      __IM  uint32_t RESERVED1  : 19;
    } bit;
  } RSTPCTRL;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Sticky Reset Flag Register                                 */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t LVDRSTRCD  : 1;            /* [1..1] LVD Reset Record                                                   */
      __IOM uint32_t ECLKLRSTRCD : 1;           /* [2..2] Clock Loss Reset Record                                            */
      __IOM uint32_t LOCKLRSTRCD : 1;           /* [3..3] Lock Loss Reset Record                                             */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t WDTRSTRCD  : 1;            /* [5..5] Watchdog Timer Reset Record                                        */
      __IOM uint32_t EPRSTRCD   : 1;            /* [6..6] External Pin Reset Record                                          */
      __IOM uint32_t PORRCD     : 1;            /* [7..7] Power-On Reset Record                                              */
      __IOM uint32_t JTAGRSTRCD : 1;            /* [8..8] JTAG Reset Record                                                  */
      __IOM uint32_t CLOCKRCD   : 1;            /* [9..9] Core Lockup Reset Record                                           */
      __IOM uint32_t SWRSTRCD   : 1;            /* [10..10] Software Reset Record                                            */
      __IOM uint32_t SRSTREGRCD : 1;            /* [11..11] System Reset Request Record                                      */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t STOPACKERSTRCD : 1;        /* [13..13] Stop Acknowledge Error Reset Record                              */
      __IM  uint32_t RESERVED3  : 18;
    } bit;
  } SRSTFLG;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000001C) Reset Interrupt Enable Register                            */

    struct {
      __IOM uint32_t RSTDTIMCFG : 2;            /* [1..0] Reset Delay Time Configure                                         */
      __IOM uint32_t CLKLIEN    : 1;            /* [2..2] Clock Loss Interrupt Enable                                        */
      __IOM uint32_t LOCKLIEN   : 1;            /* [3..3] Lock Loss Interrupt Enable                                         */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t WDTIEN     : 1;            /* [5..5] Watchdog Timer Interrupt Enable                                    */
      __IOM uint32_t EXTPIEN    : 1;            /* [6..6] External Reset Pin Interrupt Enable                                */
      __IOM uint32_t GIEN       : 1;            /* [7..7] Global Interrupt Enable                                            */
      __IOM uint32_t JTAGIEN    : 1;            /* [8..8] JTAG Interrupt Enable                                              */
      __IOM uint32_t CLOCKIEN   : 1;            /* [9..9] Core Lockup Interrupt Enable                                       */
      __IOM uint32_t SWIEN      : 1;            /* [10..10] Software Interrupt Enable                                        */
      __IOM uint32_t SRSTREQEN  : 1;            /* [11..11] System Reset Request Enable                                      */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t SACKEIEN   : 1;            /* [13..13] Stop Acknowledge Error Interrupt Enable                          */
      __IM  uint32_t RESERVED2  : 18;
    } bit;
  } RSTIEN;
} RMU_T;                                     /* Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIO                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General Purpose Input/Output (GPIO)
  */

typedef struct {                                /*  GPIO Structure  (@ 0x400FF000)GPIOA (@ 0x400FF040)GPIOB (@ 0x400FF080)GPIOC (@ 0x400FF0C0)GPIOD (@ 0x400FF100)GPIOE */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Port Logic Level Output Register                           */

    struct {
      __IOM uint32_t PLLO       : 32;           /* [31..0] Port Logic Level Output                                           */
    } bit;
  } PLLO;

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000004) Port Logic Level Output Set Register                       */

    struct {
      __OM  uint32_t PLLOS      : 32;           /* [31..0] Port Logic Level Output Set                                       */
    } bit;
  } PLLOS;

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000008) Port Logic Level Output Clear Register                     */

    struct {
      __OM  uint32_t PLLOC      : 32;           /* [31..0] Port Logic Level Output Clear                                     */
    } bit;
  } PLLOC;

  union {
    __OM  uint32_t reg;                         /* (@ 0x0000000C) Port Logic Level Output Toggle Register                    */

    struct {
      __OM  uint32_t PLLOT      : 32;           /* [31..0] Port Logic Level Output Toggle                                    */
    } bit;
  } PLLOT;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000010) Port Logic Level Input Register                            */

    struct {
      __IM  uint32_t PLLI       : 32;           /* [31..0] Port Logic Level Input                                            */
    } bit;
  } PLLI;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000014) Port Logic Level Transfer Direction Select Register        */

    struct {
      __IOM uint32_t PLLTDS     : 32;           /* [31..0] Port Logic Level Transfer Direction Select                        */
    } bit;
  } PLLTDS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000018) Port Logic Level Input Disable Register                    */

    struct {
      __IOM uint32_t PLLID      : 32;           /* [31..0] Port Logic Level Input Disable                                    */
    } bit;
  } PLLID;
} GPIO_T;                                   /* Size = 28 (0x1c)                                                              */



/* =========================================================================================================================== */
/* ================                                          APM32_SCB                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief System Control Registers (APM32_SCB)
  */

typedef struct {                                /* (@ 0xE000E000) APM32_SCB Structure                                          */
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Auxiliary Control Register,                                */

    struct {
      __IOM uint32_t DISMCYCINT : 1;            /* [0..0] Disables interruption of multi-cycle instructions.                 */
      __IOM uint32_t DISDEFWBUF : 1;            /* [1..1] Disables write buffer use during default memory map accesses.      */
      __IOM uint32_t DISFOLD    : 1;            /* [2..2] Disables folding of IT instructions.                               */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t DISFPCA    : 1;            /* [8..8] SBZP / Disables automatic update of CONTROL.FPCA.                  */
      __IOM uint32_t DISOOFP    : 1;            /* [9..9] Disables floating point instructions completing out of
                                                     order with respect to integer instructions.                             */
      __IM  uint32_t RESERVED1  : 22;
    } bit;
  } ACTLR;
  __IM  uint32_t  RESERVED1[829];

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000D00) CPUID Base Register                                        */

    struct {
      __IM  uint32_t REVISION   : 4;            /* [3..0] Indicates patch release: 0x0 = Patch 0                             */
      __IM  uint32_t PARTNO     : 12;           /* [15..4] Indicates part number                                             */
      __IM  uint32_t RESERVED2  : 4;
      __IM  uint32_t VARIANT    : 4;            /* [23..20] Indicates processor revision: 0x2 = Revision 2                   */
      __IM  uint32_t IMPLEMENTER : 8;           /* [31..24] Implementer code                                                 */
    } bit;
  } CPUID;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D04) Interrupt Control and State Register                       */

    struct {
      __IM  uint32_t VECTACTIVE : 9;            /* [8..0] Active exception number                                            */
      __IM  uint32_t RESERVED0  : 2;
      __IM  uint32_t RETTOBASE  : 1;            /* [11..11] Indicates whether there are preempted active exceptions          */
      __IM  uint32_t VECTPENDING : 6;           /* [17..12] Exception number of the highest priority pending enabled
                                                     exception                                                               */
      __IM  uint32_t RESERVED1  : 4;
      __IM  uint32_t ISRPENDING : 1;            /* [22..22] Interrupt pending flag, excluding NMI and Faults                 */
      __IM  uint32_t ISRPREEMPT : 1;            /* [23..23] You must only use this at debug time. It indicates
                                                     that a pending interrupt becomes active in the next running
                                                     cycle. If C_MASKINTS is clear in the Debug Halting Control
                                                     and Status Register, the interrupt is serviced                          */
      __IM  uint32_t RESERVED2  : 1;
      __OM  uint32_t PENDSTCLR  : 1;            /* [25..25] SysTick exception clear-pending bit                              */
      __IOM uint32_t PENDSTSET  : 1;            /* [26..26] SysTick exception set-pending bit                                */
      __OM  uint32_t PENDSVCLR  : 1;            /* [27..27] PendSV clear-pending bit                                         */
      __IOM uint32_t PENDSVSET  : 1;            /* [28..28] PendSV set-pending bit                                           */
      __IM  uint32_t RESERVED3  : 2;
      __IOM uint32_t NMIPENDSET : 1;            /* [31..31] NMI set-pending bit                                              */
    } bit;
  } ICSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D08) Vector Table Offset Register                               */

    struct {
      __IM  uint32_t RESERVED0  : 7;
      __IOM uint32_t TBLOFF     : 25;           /* [31..7] Vector table base offset                                          */
    } bit;
  } VTOR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D0C) Application Interrupt and Reset Control Register           */

    struct {
      __OM  uint32_t VECTRESET  : 1;            /* [0..0] Reserved for Debug use. This bit reads as 0. When writing
                                                     to the register you must write 0 to this bit, otherwise
                                                     behavior is Unpredictable.                                              */
      __OM  uint32_t VECTCLRACTIVE : 1;         /* [1..1] Reserved for Debug use. This bit reads as 0. When writing
                                                     to the register you must write 0 to this bit, otherwise
                                                     behavior is Unpredictable.                                              */
      __OM  uint32_t SYSRESETREQ : 1;           /* [2..2] System reset request bit is implementation defined                 */
      __IM  uint32_t RESERVED0  : 5;
      __IOM uint32_t PRIGROUP   : 3;            /* [10..8] Interrupt priority grouping field. This field determines
                                                     the split of group priority from subpriority.                           */
      __IM  uint32_t RESERVED1  : 4;
      __IM  uint32_t ENDIANNESS : 1;            /* [15..15] Data endianness bit is implementation defined                    */
      __IOM uint32_t VECTKEY    : 16;           /* [31..16] Register key                                                     */
    } bit;
  } AIRCR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D10) System Control Register                                    */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t SLEEPONEXIT : 1;           /* [1..1] Indicates sleep-on-exit when returning from Handler mode
                                                     to Thread mode                                                          */
      __IOM uint32_t SLEEPDEEP  : 1;            /* [2..2] Controls whether the processor uses sleep or deep sleep
                                                     as its low power mode                                                   */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t SEVONPEND  : 1;            /* [4..4] Send Event on Pending bit                                          */
      __IM  uint32_t RESERVED2  : 27;
    } bit;
  } SCR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D14) Configuration and Control Register                         */

    struct {
      __IOM uint32_t NONBASETHRDENA : 1;        /* [0..0] Indicates how the processor enters Thread mode                     */
      __IOM uint32_t USERSETMPEND : 1;          /* [1..1] Enables unprivileged software access to the STIR                   */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t UNALIGN_TRP : 1;           /* [3..3] Enables unaligned access traps                                     */
      __IOM uint32_t DIV_0_TRP  : 1;            /* [4..4] Enables faulting or halting when the processor executes
                                                     an SDIV or UDIV instruction with a divisor of 0                         */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t BFHFNMIGN  : 1;            /* [8..8] Enables handlers with priority -1 or -2 to ignore data
                                                     BusFaults caused by load and store instructions.                        */
      __IOM uint32_t STKALIGN   : 1;            /* [9..9] Indicates stack alignment on exception entry                       */
      __IM  uint32_t RESERVED2  : 22;
    } bit;
  } CCR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D18) System Handler Priority Register 1                         */

    struct {
      __IOM uint32_t PRI_4      : 8;            /* [7..0] Priority of system handler 4, MemManage                            */
      __IOM uint32_t PRI_5      : 8;            /* [15..8] Priority of system handler 5, BusFault                            */
      __IOM uint32_t PRI_6      : 8;            /* [23..16] Priority of system handler 6, UsageFault                         */
      __IM  uint32_t RESERVED0  : 8;
    } bit;
  } SHPR1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D1C) System Handler Priority Register 2                         */

    struct {
      __IM  uint32_t RESERVED0  : 24;
      __IOM uint32_t PRI_11     : 8;            /* [31..24] Priority of system handler 11, SVCall                            */
    } bit;
  } SHPR2;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D20) System Handler Priority Register 3                         */

    struct {
      __IOM uint32_t PRI_12     : 8;            /* [7..0] Priority of system handler 12, DebugMonitor                        */
      __IM  uint32_t RESERVED0  : 8;
      __IOM uint32_t PRI_14     : 8;            /* [23..16] Priority of system handler 14, PendSV                            */
      __IOM uint32_t PRI_15     : 8;            /* [31..24] Priority of system handler 15, SysTick exception                 */
    } bit;
  } SHPR3;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D24) System Handler Control and State Register                  */

    struct {
      __IOM uint32_t MEMFAULTACT : 1;           /* [0..0] MemManage exception active bit, reads as 1 if exception
                                                     is active                                                               */
      __IOM uint32_t BUSFAULTACT : 1;           /* [1..1] BusFault exception active bit, reads as 1 if exception
                                                     is active                                                               */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t USGFAULTACT : 1;           /* [3..3] UsageFault exception active bit, reads as 1 if exception
                                                     is active                                                               */
      __IM  uint32_t RESERVED1  : 3;
      __IOM uint32_t SVCALLACT  : 1;            /* [7..7] SVCall active bit, reads as 1 if SVC call is active                */
      __IOM uint32_t MONITORACT : 1;            /* [8..8] Debug monitor active bit, reads as 1 if Debug monitor
                                                     is active                                                               */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t PENDSVACT  : 1;            /* [10..10] PendSV exception active bit, reads as 1 if exception
                                                     is active                                                               */
      __IOM uint32_t SYSTICKACT : 1;            /* [11..11] SysTick exception active bit, reads as 1 if exception
                                                     is active                                                               */
      __IOM uint32_t USGFAULTPENDED : 1;        /* [12..12] UsageFault exception pending bit, reads as 1 if exception
                                                     is pending                                                              */
      __IOM uint32_t MEMFAULTPENDED : 1;        /* [13..13] MemManage exception pending bit, reads as 1 if exception
                                                     is pending                                                              */
      __IOM uint32_t BUSFAULTPENDED : 1;        /* [14..14] BusFault exception pending bit, reads as 1 if exception
                                                     is pending                                                              */
      __IOM uint32_t SVCALLPENDED : 1;          /* [15..15] SVCall pending bit, reads as 1 if exception is pending           */
      __IOM uint32_t MEMFAULTENA : 1;           /* [16..16] MemManage enable bit, set to 1 to enable                         */
      __IOM uint32_t BUSFAULTENA : 1;           /* [17..17] BusFault enable bit, set to 1 to enable                          */
      __IOM uint32_t USGFAULTENA : 1;           /* [18..18] UsageFault enable bit, set to 1 to enable                        */
      __IM  uint32_t RESERVED3  : 13;
    } bit;
  } SHCSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D28) Configurable Fault Status Registers                        */

    struct {
      __IOM uint32_t IACCVIOL   : 1;            /* [0..0] Instruction access violation flag                                  */
      __IOM uint32_t DACCVIOL   : 1;            /* [1..1] Data access violation flag                                         */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t MUNSTKERR  : 1;            /* [3..3] MemManage fault on unstacking for a return from exception          */
      __IOM uint32_t MSTKERR    : 1;            /* [4..4] MemManage fault on stacking for exception entry                    */
      __IOM uint32_t MLSPERR    : 1;            /* [5..5] Indicates whether MemManage fault occured during floating-point
                                                     lazy state preservation                                                   */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t MMARVALID  : 1;            /* [7..7] MemManage Fault Address Register (MMFAR) valid flag                */
      __IOM uint32_t IBUSERR    : 1;            /* [8..8] Instruction bus error                                              */
      __IOM uint32_t PRECISERR  : 1;            /* [9..9] Precise data bus error                                             */
      __IOM uint32_t IMPRECISERR : 1;           /* [10..10] Imprecise data bus error                                         */
      __IOM uint32_t UNSTKERR   : 1;            /* [11..11] BusFault on unstacking for a return from exception               */
      __IOM uint32_t STKERR     : 1;            /* [12..12] BusFault on stacking for exception entry                         */
      __IOM uint32_t LSPERR     : 1;            /* [13..13] Indicates whether bus fault fault occured during floating-point
                                                     lazy state preservation                                                   */
      __IM  uint32_t RESERVED2  : 1;
      __IOM uint32_t BFARVALID  : 1;            /* [15..15] BusFault Address Register (BFAR) valid flag                      */
      __IOM uint32_t UNDEFINSTR : 1;            /* [16..16] Undefined instruction UsageFault                                 */
      __IOM uint32_t INVSTATE   : 1;            /* [17..17] Invalid state UsageFault                                         */
      __IOM uint32_t INVPC      : 1;            /* [18..18] Invalid PC load UsageFault, caused by an invalid PC
                                                     load by EXC_RETURN                                                        */
      __IOM uint32_t NOCP       : 1;            /* [19..19] No coprocessor UsageFault. The processor does not support
                                                     coprocessor instructions                                                  */
      __IM  uint32_t RESERVED3  : 4;
      __IOM uint32_t UNALIGNED  : 1;            /* [24..24] Unaligned access UsageFault                                      */
      __IOM uint32_t DIVBYZERO  : 1;            /* [25..25] Divide by zero UsageFault                                        */
      __IM  uint32_t RESERVED4  : 6;
    } bit;
  } CFSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D2C) HardFault Status register                                  */

    struct {
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t VECTTBL    : 1;            /* [1..1] Indicates a BusFault on a vector table read during exception
                                                     processing                                                              */
      __IM  uint32_t RESERVED1  : 28;
      __IOM uint32_t FORCED     : 1;            /* [30..30] Indicates a forced hard fault, generated by escalation
                                                     of a fault with configurable priority that cannot be handles,
                                                     either because of priority or because it is disabled                    */
      __IOM uint32_t DEBUGEVT   : 1;            /* [31..31] Reserved for Debug use. When writing to the register
                                                     you must write 0 to this bit, otherwise behavior is Unpredictable.      */
    } bit;
  } HFSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D30) Debug Fault Status Register                                */

    struct {
      __IOM uint32_t HALTED     : 1;            /* [0..0] HALTED                                                             */
      __IOM uint32_t BKPT       : 1;            /* [1..1] BKPT                                                               */
      __IOM uint32_t DWTTRAP    : 1;            /* [2..2] DWTTRAP                                                            */
      __IOM uint32_t VCATCH     : 1;            /* [3..3] VCATCH                                                             */
      __IOM uint32_t EXTERNAL   : 1;            /* [4..4] EXTERNAL                                                           */
      __IM  uint32_t RESERVED0  : 27;
    } bit;
  } DFSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D34) MemManage Address Register                                 */

    struct {
      __IOM uint32_t ADDRESS    : 32;           /* [31..0] Address of MemManage fault location                               */
    } bit;
  } MMFAR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D38) BusFault Address Register                                  */

    struct {
      __IOM uint32_t ADDRESS    : 32;           /* [31..0] Address of the BusFault location                                  */
    } bit;
  } BFAR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D3C) Auxiliary Fault Status Register                            */

    struct {
      __IOM uint32_t AUXFAULT   : 32;           /* [31..0] Latched version of the AUXFAULT inputs                            */
    } bit;
  } AFSR;
  __IM  uint32_t  RESERVED2[18];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000D88) Coprocessor Access Control Register                        */

    struct {
      __IM  uint32_t RESERVED0  : 20;
      __IOM uint32_t CP10       : 2;            /* [21..20] Access privileges for coprocessor 10.                            */
      __IOM uint32_t CP11       : 2;            /* [23..22] Access privileges for coprocessor 11.                            */
      __IM  uint32_t RESERVED1  : 8;
    } bit;
  } CPACR;
  __IM  uint32_t  RESERVED3[106];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000F34) Floating-point Context Control Register                    */

    struct {
      __IOM uint32_t LSPACT     : 1;            /* [0..0] Lazy state preservation.                                           */
      __IOM uint32_t USER       : 1;            /* [1..1] Privilege level when the floating-point stack frame was
                                                     allocated.                                                              */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t THREAD     : 1;            /* [3..3] Mode when the floating-point stack frame was allocated.            */
      __IOM uint32_t HFRDY      : 1;            /* [4..4] Permission to set the HardFault handler to the pending
                                                     state when the floating-point stack frame was allocated.                */
      __IOM uint32_t MMRDY      : 1;            /* [5..5] Permission to set the MemManage handler to the pending
                                                     state when the floating-point stack frame was allocated.                */
      __IOM uint32_t BFRDY      : 1;            /* [6..6] Permission to set the BusFault handler to the pending
                                                     state when the floating-point stack frame was allocated.                */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t MONRDY     : 1;            /* [8..8] Permission to set the MON_PEND when the floating-point
                                                     stack frame was allocated.                                              */
      __IM  uint32_t RESERVED2  : 21;
      __IOM uint32_t LSPEN      : 1;            /* [30..30] Lazy state preservation for floating-point context.              */
      __IOM uint32_t ASPEN      : 1;            /* [31..31] Enables CONTROL2 setting on execution of a floating-point
                                                     instruction. This results in automatic hardware state preservation
                                                     and restoration, for floating-point context, on exception
                                                     entry and exit.                                                         */
    } bit;
  } FPCCR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000F38) Floating-point Context Address Register                    */

    struct {
      __IM  uint32_t RESERVED0  : 3;
      __IOM uint32_t ADDRESS    : 29;           /* [31..3] The location of the unpopulated floating-point register
                                                     space allocated on an exception stack frame.                            */
    } bit;
  } FPCAR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000F3C) Floating-point Default Status Control Register             */

    struct {
      __IM  uint32_t RESERVED0  : 22;
      __IOM uint32_t RMode      : 2;            /* [23..22] Default value for FPSCR.RMode (Rounding Mode control
                                                     field).                                                                 */
      __IOM uint32_t FZ         : 1;            /* [24..24] Default value for FPSCR.FZ (Flush-to-zero mode control
                                                     bit).                                                                   */
      __IOM uint32_t DN         : 1;            /* [25..25] Default value for FPSCR.DN (Default NaN mode control
                                                     bit).                                                                   */
      __IOM uint32_t AHP        : 1;            /* [26..26] Default value for FPSCR.AHP (Alternative half-precision
                                                     control bit).                                                           */
      __IM  uint32_t RESERVED1  : 5;
    } bit;
  } FPDSCR;
} APM32_SCB_T;                                 /* Size = 3904 (0xf40)                                                          */



/* =========================================================================================================================== */
/* ================                                        APM32_SysTick                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief System timer (APM32_SysTick)
  */

typedef struct {                                /* (@ 0xE000E010) APM32_SysTick Structure                                      */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) SysTick Control and Status Register                        */

    struct {
      __IOM uint32_t ENABLE     : 1;            /* [0..0] Enables the counter                                                */
      __IOM uint32_t TICKINT    : 1;            /* [1..1] Enables SysTick exception request                                  */
      __IOM uint32_t CLKSOURCE  : 1;            /* [2..2] Indicates the clock source                                         */
      __IM  uint32_t RESERVED0  : 13;
      __IOM uint32_t COUNTFLAG  : 1;            /* [16..16] Returns 1 if timer counted to 0 since last time this
                                                     was read                                                                */
      __IM  uint32_t RESERVED1  : 15;
    } bit;
  } CSR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) SysTick Reload Value Register                              */

    struct {
      __IOM uint32_t RELOAD     : 24;           /* [23..0] Value to load into the SysTick Current Value Register
                                                     when the counter reaches 0                                              */
      __IM  uint32_t RESERVED0  : 8;
    } bit;
  } RVR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) SysTick Current Value Register                             */

    struct {
      __IOM uint32_t CURRENT    : 24;           /* [23..0] Current value at the time the register is accessed                */
      __IM  uint32_t RESERVED0  : 8;
    } bit;
  } CVR;

  union {
    __IM  uint32_t reg;                         /* (@ 0x0000000C) SysTick Calibration Value Register                         */

    struct {
      __IM  uint32_t TENMS      : 24;           /* [23..0] Reload value to use for 10ms timing                               */
      __IM  uint32_t RESERVED0  : 6;
      __IM  uint32_t SKEW       : 1;            /* [30..30] Indicates whether the TENMS value is exact                       */
      __IM  uint32_t NOREF      : 1;            /* [31..31] Indicates whether the device provides a reference clock
                                                     to the processor                                                        */
    } bit;
  } CALIB;
} APM32_SysTick_T;                             /* Size = 16 (0x10)                                                             */



/* =========================================================================================================================== */
/* ================                                         APM32_NVIC                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Nested Vectored Interrupt Controller (APM32_NVIC)
  */

typedef struct {                                /* (@ 0xE000E100) APM32_NVIC Structure                                         */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Interrupt Set Enable Register n                            */

    struct {
      __IOM uint32_t SETENA     : 32;           /* [31..0] Interrupt set enable bits                                         */
    } bit;
  } NVICISER[8];

  __IM  uint32_t  RESERVED[24];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000080) Interrupt Clear Enable Register n                          */

    struct {
      __IOM uint32_t CLRENA     : 32;           /* [31..0] Interrupt clear-enable bits                                       */
    } bit;
  } NVICICER[8];

  __IM  uint32_t  RESERVED1[24];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000100) Interrupt Set Pending Register n                           */

    struct {
      __IOM uint32_t SETPEND    : 32;           /* [31..0] Interrupt set-pending bits                                        */
    } bit;
  } NVICISPR[8];

  __IM  uint32_t  RESERVED2[24];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000180) Interrupt Clear Pending Register n                         */

    struct {
      __IOM uint32_t CLRPEND    : 32;           /* [31..0] Interrupt clear-pending bits                                      */
    } bit;
  } NVICICPR[8];

  __IM  uint32_t  RESERVED3[24];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000200) Interrupt Active bit Register n                            */

    struct {
      __IOM uint32_t ACTIVE     : 32;           /* [31..0] Interrupt active flags                                            */
    } bit;
  } NVICIABR[8];

  __IM  uint32_t  RESERVED4[56];

  union {
    __IOM uint8_t reg;                          /* (@ 0x00000300) Interrupt Priority Register n                              */

    struct {
      __IOM uint8_t PRI        : 8;            /* [7..0] Priority of interrupt 0                                             */
    } bit;
  } NVICIP[240];

  __IM  uint32_t  RESERVED5[644];

  union {
    __OM  uint32_t reg;                         /* (@ 0x00000E00) Software Trigger Interrupt Register                        */

    struct {
      __OM  uint32_t INTID      : 9;            /* [8..0] Interrupt ID of the interrupt to trigger, in the range
                                                     0-239. For example, a value of 0x03 specifies interrupt
                                                     IRQ3.                                                                   */
      __IM  uint32_t RESERVED0  : 23;
    } bit;
  } NVICSTIR;
} APM32_NVIC_T;                                /* Size = 3588 (0xe04)                                                          */



/* =========================================================================================================================== */
/* ================                                            MC                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Core Platform Miscellaneous Control Module (MC)
  */

typedef struct {                                /* (@ 0xE0080000) MC Structure                                               */
  __IM  uint32_t  RESERVED[2];

  union {
    __IM  uint16_t reg;                         /* (@ 0x00000008) XBARSW Slave Input Port Connection Status                  */

    struct {
      __IM  uint16_t SINCFLG    : 8;            /* [7..0] XBARSW Slave Input Port Connection Flag                            */
            uint16_t            : 8;
    } bit;
  } SINCSTS;

  union {
    __IM  uint16_t reg;                         /* (@ 0x0000000A) XBARSW Master Input Port Connection Status                 */

    struct {
      __IM  uint16_t MINCFLG    : 8;            /* [7..0] XBARSW Master Input Port Connection Flag                           */
            uint16_t            : 8;
    } bit;
  } MINCSTS;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Core Platform Control Register                             */

    struct {
      __IM  uint32_t HMSTS      : 2;            /* [1..0] XBARSW Halt Machine Status                                         */
      __IM  uint32_t RXHREQFLG  : 1;            /* [2..2] XBARSW Receive Halt Request Flag                                   */
      __IM  uint32_t HSTS       : 1;            /* [3..3] XBARSW Halt Status                                                 */
      __IM  uint32_t FMCPGISTS  : 1;            /* [4..4] Flash Memory Controller Program Idle Status                        */
      __IM  uint32_t RESERVED0  : 1;
      __IM  uint32_t ACISTS     : 1;            /* [6..6] AC Idle Status                                                     */
      __IM  uint32_t RESERVED1  : 2;
      __IOM uint32_t CASEL      : 1;            /* [9..9] Crossbar Arbitration Select                                        */
      __IM  uint32_t RESERVED2  : 14;
      __IOM uint32_t SHAPCFG    : 2;            /* [25..24] SRAM_H Arbitration Priority Configure                            */
      __IOM uint32_t SHWPRO     : 1;            /* [26..26] SRAM_H Write Protect                                             */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t SLAPCFG    : 2;            /* [29..28] SRAM_L Arbitration Priority Configure                            */
      __IOM uint32_t SLWPRO     : 1;            /* [30..30] SRAM_L Write Protect                                             */
      __IM  uint32_t RESERVED4  : 1;
    } bit;
  } CPCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000010) FPU Interrupt Control and Status Register                  */

    struct {
      __IM  uint32_t RESERVED0  : 8;
      __IM  uint32_t INVALIDIFLG : 1;           /* [8..8] FPU Invalid Operation Interrupt Flag                               */
      __IM  uint32_t ZEROIFLG   : 1;            /* [9..9] FPU Divide-by-Zero Interrupt Flag                                  */
      __IM  uint32_t OVRIFLG    : 1;            /* [10..10] FPU Overflow Interrupt Flag                                      */
      __IM  uint32_t UDRIFLG    : 1;            /* [11..11] FPU Underflow Interrupt Flag                                     */
      __IM  uint32_t INEXACTIFLG : 1;           /* [12..12] FPU Inexact Interrupt Flag                                       */
      __IM  uint32_t RESERVED1  : 2;
      __IM  uint32_t INDIFLG    : 1;            /* [15..15] FPU Input Denormal Interrupt Flag                                */
      __IM  uint32_t RESERVED2  : 8;
      __IOM uint32_t INVALIDEN  : 1;            /* [24..24] FPU Invalid Operation Enable                                     */
      __IOM uint32_t ZEROEN     : 1;            /* [25..25] FPU Divide-by-Zero Enable                                        */
      __IOM uint32_t OVRIEN     : 1;            /* [26..26] FPU Overflow Enable                                              */
      __IOM uint32_t UDRIEN     : 1;            /* [27..27] FPU Underflow Enable                                             */
      __IOM uint32_t INEXACTIEN : 1;            /* [28..28] FPU Inexact Enable                                               */
      __IM  uint32_t RESERVED3  : 2;
      __IOM uint32_t INDIEN     : 1;            /* [31..31] FPU Input Denormal Enable                                        */
    } bit;
  } FPU_INTCSTS;
  __IM  uint32_t  RESERVED1[7];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000030) Process ID Register                                        */

    struct {
      __IOM uint32_t PID        : 8;            /* [7..0] M0_PID and M1_PID Values in the MPU Drive                          */
      __IM  uint32_t RESERVED0  : 24;
    } bit;
  } PID;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000040) Compute Operation Control Register                         */

    struct {
      __IOM uint32_t COREQ      : 1;            /* [0..0] Compute Operation Request                                          */
      __IM  uint32_t COACK      : 1;            /* [1..1] Compute Operation Acknowledge                                      */
      __IOM uint32_t COWBI      : 1;            /* [2..2] Compute Operation Wakeup By Interrupt                              */
      __IM  uint32_t RESERVED0  : 29;
    } bit;
  } COCTRL;
  __IM  uint32_t  RESERVED3[239];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000400) Local Memory Descriptor Register0                          */

    struct {
      __IOM uint32_t ECCCTRL    : 4;            /* [3..0] TCM ECC Control                                                    */
      __IM  uint32_t RESERVED0  : 9;
      __IM  uint32_t TSEL       : 3;            /* [15..13] Local Memory Type Select                                         */
      __IOM uint32_t LOCK       : 1;            /* [16..16] LOCK                                                             */
      __IM  uint32_t DPWSEL     : 3;            /* [19..17] LMC Data Path Width Select                                       */
      __IM  uint32_t CWCFG      : 4;            /* [23..20] Level 1 Cache Ways Configure                                     */
      __IM  uint32_t SIZE       : 4;            /* [27..24] LMC Size                                                         */
      __IM  uint32_t SIZEH      : 1;            /* [28..28] LMC Size Hole                                                    */
      __IM  uint32_t RESERVED1  : 2;
      __IM  uint32_t VALID      : 1;            /* [31..31] Local Memory Valid                                               */
    } bit;
  } LMDES0;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000404) Local Memory Descriptor Register1                          */

    struct {
      __IOM uint32_t ECCCTRL    : 4;            /* [3..0] TCM ECC Control                                                    */
      __IM  uint32_t RESERVED0  : 9;
      __IM  uint32_t TSEL       : 3;            /* [15..13] Local Memory Type Select                                         */
      __IOM uint32_t LOCK       : 1;            /* [16..16] LOCK                                                             */
      __IM  uint32_t DPWSEL     : 3;            /* [19..17] LMC Data Path Width Select                                       */
      __IM  uint32_t CWCFG      : 4;            /* [23..20] Level 1 Cache Ways Configure                                     */
      __IM  uint32_t SIZE       : 4;            /* [27..24] LMC Size                                                         */
      __IM  uint32_t SIZEH      : 1;            /* [28..28] LMC Size Hole                                                    */
      __IM  uint32_t RESERVED1  : 2;
      __IM  uint32_t VALID      : 1;            /* [31..31] Local Memory Valid                                               */
    } bit;
  } LMDES1;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000408) Local Memory Descriptor Register2                          */

    struct {
      __IM  uint32_t RESERVED0  : 4;
      __IOM uint32_t CPFCTRL    : 4;            /* [7..4] Cache Parity Functions Control                                     */
      __IM  uint32_t RESERVED1  : 5;
      __IM  uint32_t TSEL       : 3;            /* [15..13] Local Memory Type Select                                         */
      __IOM uint32_t LOCK       : 1;            /* [16..16] LOCK                                                             */
      __IM  uint32_t DPWSEL     : 3;            /* [19..17] LMC Data Path Width Select                                       */
      __IM  uint32_t CWCFG      : 4;            /* [23..20] Level 1 Cache Ways Configure                                     */
      __IM  uint32_t SIZE       : 4;            /* [27..24] LMC Size                                                         */
      __IM  uint32_t SIZEH      : 1;            /* [28..28] LMC Size Hole                                                    */
      __IM  uint32_t RESERVED2  : 2;
      __IM  uint32_t VALID      : 1;            /* [31..31] Local Memory Valid                                               */
    } bit;
  } LMDES2;
  __IM  uint32_t  RESERVED4[29];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000480) LMC Parity and ECC Control Register                        */

    struct {
      __IOM uint32_t NCREN      : 1;            /* [0..0] RAM ECC Noncorrectable Reporting Enable                            */
      __IM  uint32_t RESERVED0  : 7;
      __IOM uint32_t R1BREN     : 1;            /* [8..8] RAM ECC 1 Bit Reporting Enable                                     */
      __IM  uint32_t RESERVED1  : 11;
      __IOM uint32_t CPREN      : 1;            /* [20..20] Cache Parity Reporting Enable                                    */
      __IM  uint32_t RESERVED2  : 11;
    } bit;
  } LMPECTRL;
  __IM  uint32_t  RESERVED5;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000488) LMC Parity and ECC Interrupt Register                      */

    struct {
      __IOM uint32_t NCERRFLG   : 8;            /* [7..0] ECC Noncorrectable Error Flag                                      */
      __IOM uint32_t E1BERRFLG  : 8;            /* [15..8] ECC 1-bit Error Flag                                              */
      __IOM uint32_t CPERR      : 8;            /* [23..16] Cache Parity Error                                               */
      __IM  uint32_t PEERRL     : 5;            /* [28..24] Parity or ECC Error Location                                     */
      __IM  uint32_t RESERVED0  : 2;
      __IM  uint32_t VALID      : 1;            /* [31..31] Valid                                                            */
    } bit;
  } LMPEINT;
  __IM  uint32_t  RESERVED6;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000490) LMC Fault Address Register                                 */

    struct {
      __IM  uint32_t EFADDR     : 32;           /* [31..0] ECC Fault Address                                                 */
    } bit;
  } LMFADDR;

  union {
    __IM  uint32_t reg;                         /* (@ 0x00000494) LMC Fault Attribute Register                               */

    struct {
      __IM  uint32_t PEFPRO     : 4;            /* [3..0] Parity/ECC Fault Master Size                                        */
      __IM  uint32_t PEFMSIZE   : 3;            /* [6..4] Parity/ECC Fault Protection                                        */
      __IM  uint32_t PEFW       : 1;            /* [7..7] Parity/ECC Fault Write                                             */
      __IM  uint32_t PEFMNUM    : 8;            /* [15..8] Parity/ECC Fault Master Number                                    */
      __IM  uint32_t RESERVED0  : 15;
      __IM  uint32_t OVR        : 1;            /* [31..31] Overrun                                                          */
    } bit;
  } LMFAT;
  __IM  uint32_t  RESERVED7[2];

  union {
    __IM  uint32_t reg;                         /* (@ 0x000004A0) LMC Fault Data High Register                               */

    struct {
      __IM  uint32_t PEFH       : 32;           /* [31..0] Parity/ ECC Fault Data High                                       */
    } bit;
  } LMFDATAH;

  union {
    __IM  uint32_t reg;                         /* (@ 0x000004A4) LMC Fault Data Low Register                                */

    struct {
      __IM  uint32_t PEFL       : 32;           /* [31..0] Parity/ ECC Fault Data Low                                        */
    } bit;
  } LMFDATAL;
} MC_T;                                      /* Size = 1192 (0x4a8)                                                       */



/* =========================================================================================================================== */
/* ================                                            LMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Local Memory Controller (LMC)
  */

typedef struct {                                /* (@ 0xE0082000) LMC Structure                                              */

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000000) Cache Control Register                                     */

    struct {
      __IOM uint32_t CEN        : 1;            /* [0..0] Cache Enable                                                       */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t FWCS       : 1;            /* [2..2] Force Write to Cacheable Space                                     */
      __IOM uint32_t FCHA       : 1;            /* [3..3] Force Cache Hit Allocation                                         */
      __IM  uint32_t RESERVED1  : 20;
      __IOM uint32_t IW0        : 1;            /* [24..24] Invalidate Way 0                                                 */
      __IOM uint32_t PW0        : 1;            /* [25..25] Push Way 0                                                       */
      __IOM uint32_t IW1        : 1;            /* [26..26] Invalidate Way 1                                                 */
      __IOM uint32_t PW1        : 1;            /* [27..27] Push Way 1                                                       */
      __IM  uint32_t RESERVED2  : 3;
      __IOM uint32_t ICCMD      : 1;            /* [31..31] Initiate Cache Command                                           */
    } bit;
  } CCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000004) Cache Line Control Register                                */

    struct {
      __IOM uint32_t ICLCMD     : 1;            /* [0..0] Initiate Cache Line Command                                        */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t CADDR      : 12;           /* [13..2] Cache Address                                                     */
      __IOM uint32_t LCMDWSEL   : 1;            /* [14..14] Line Command Way Select                                          */
      __IM  uint32_t RESERVED1  : 1;
      __IOM uint32_t TAG_DATASEL : 1;           /* [16..16] Tag/Data Select                                                  */
      __IM  uint32_t RESERVED2  : 3;
      __IOM uint32_t LCMDVISTS  : 1;            /* [20..20] Line Command Valid Bit Initial State                             */
      __IOM uint32_t LCMDMISTS  : 1;            /* [21..21] Line Command Modified Bit Initial State                          */
      __IOM uint32_t LCWSTS     : 1;            /* [22..22] Line Command Way Statue                                          */
      __IM  uint32_t RESERVED3  : 1;
      __IOM uint32_t LCMDCFG    : 2;            /* [25..24] Line Command Configure                                           */
      __IOM uint32_t LADDRSEL   : 1;            /* [26..26] Line Address Select                                              */
      __IOM uint32_t LACCTSEL   : 1;            /* [27..27] Line Access Type Select                                          */
      __IM  uint32_t RESERVED4  : 4;
    } bit;
  } CLCTRL;

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000008) Cache Search Address Register                              */

    struct {
      __IOM uint32_t CLCMDI     : 1;            /* [0..0] Cache Line Command Initiate                                        */
      __IM  uint32_t RESERVED0  : 1;
      __IOM uint32_t PHYADDR    : 30;           /* [31..2] Physical Address                                                  */
    } bit;
  } CSADDR;

  union {
    __IOM uint32_t reg;                         /* (@ 0x0000000C) Cache Data Register                                        */

    struct {
      __IOM uint32_t CDATA      : 32;           /* [31..0] Cache Data                                                        */
    } bit;
  } CDATA;
  __IM  uint32_t  RESERVED[4];

  union {
    __IOM uint32_t reg;                         /* (@ 0x00000020) Region Cache Mode Configure Register                       */

    struct {
      __IOM uint32_t CMCFGR15   : 2;            /* [1..0] Region 0-15 mode                                                   */
      __IOM uint32_t CMCFGR14   : 2;            /* [3..2] Region 0-15 mode                                                   */
      __IOM uint32_t CMCFGR13   : 2;            /* [5..4] Region 0-15 mode                                                   */
      __IOM uint32_t CMCFGR12   : 2;            /* [7..6] Region 0-15 mode                                                   */
      __IOM uint32_t CMCFGR11   : 2;            /* [9..8] Region 0-15 mode                                                   */
      __IOM uint32_t CMCFGR10   : 2;            /* [11..10] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR9    : 2;            /* [13..12] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR8    : 2;            /* [15..14] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR7    : 2;            /* [17..16] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR6    : 2;            /* [19..18] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR5    : 2;            /* [21..20] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR4    : 2;            /* [23..22] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR3    : 2;            /* [25..24] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR2    : 2;            /* [27..26] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR1    : 2;            /* [29..28] Region 0-15 mode                                                 */
      __IOM uint32_t CMCFGR0    : 2;            /* [31..30] Region 0-15 mode                                                 */
    } bit;
  } RCMCFG;
} LMC_T;                                     /* Size = 36 (0x24)                                                             */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define CSE_PRAM_BASE               0x14001000UL
#define AC_BASE                     0x40000000UL
#define MSC_BASE                    0x40001000UL
#define DMA_BASE                    0x40008000UL
#define MPU_BASE                    0x4000D000UL
#define EREP_BASE                   0x40018000UL
#define EINJ_BASE                   0x40019000UL
#define FLASH_BASE                  0x40020000UL
#define DMACHM_BASE                 0x40021000UL
#define CAN0_BASE               0x40024000UL
#define CAN1_BASE               0x40025000UL
#define CAN2_BASE               0x4002B000UL
#define CFGTMR0_BASE                  0x40038000UL
#define CFGTMR1_BASE                  0x40039000UL
#define CFGTMR2_BASE                  0x4003A000UL
#define CFGTMR3_BASE                  0x40026000UL
#define CFGTMR4_BASE                  0x4006E000UL
#define CFGTMR5_BASE                  0x4006F000UL
#define ADC0_BASE                   0x4003B000UL
#define ADC1_BASE                   0x40027000UL
#define LPSPI0_BASE                 0x4002C000UL
#define LPSPI1_BASE                 0x4002D000UL
#define LPSPI2_BASE                 0x4002E000UL
#define PDU0_BASE                   0x40036000UL
#define PDU1_BASE                   0x40031000UL
#define CRC_BASE                    0x40032000UL
#define LPITMR_BASE                 0x40037000UL
#define RTC_BASE                    0x4003D000UL
#define LPTMR_BASE                  0x40040000UL
#define SIM_BASE                    0x40048000UL
#define PMA_BASE                    0x40049000UL
#define PMB_BASE                    0x4004A000UL
#define PMC_BASE                    0x4004B000UL
#define PMD_BASE                    0x4004C000UL
#define PME_BASE                    0x4004D000UL
#define WDT_BASE                    0x40052000UL
#define CFGIO_BASE                0x4005A000UL
#define EWDT_BASE                   0x40061000UL
#define TMC_BASE                    0x40063000UL
#define SCG_BASE                    0x40064000UL
#define PCM_BASE                    0x40065000UL
#define LPI2C_BASE                  0x40066000UL
#define LPUART0_BASE                0x4006A000UL
#define LPUART1_BASE                0x4006B000UL
#define LPUART2_BASE                0x4006C000UL
#define COMP_BASE                   0x40073000UL
#define PMU_BASE                    0x4007D000UL
#define SYSMC_BASE                  0x4007E000UL
#define RMU_BASE                    0x4007F000UL
#define GPIOA_BASE                  0x400FF000UL
#define GPIOB_BASE                  0x400FF040UL
#define GPIOC_BASE                  0x400FF080UL
#define GPIOD_BASE                  0x400FF0C0UL
#define GPIOE_BASE                  0x400FF100UL
#define APM32_SCB_BASE                0xE000E000UL
#define APM32_SysTick_BASE            0xE000E010UL
#define APM32_NVIC_BASE               0xE000E100UL
#define MC_BASE                     0xE0080000UL
#define LMC_BASE                    0xE0082000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define CSE_PRAM                    ((CSE_PRAM_T*)          CSE_PRAM_BASE)
#define AC                          ((AC_T*)                AC_BASE)
#define MSC                         ((MSC_T*)               MSC_BASE)
#define DMA                         ((DMA_T*)               DMA_BASE)
#define MPU                         ((MPU_T*)               MPU_BASE)
#define EREP                        ((EREP_T*)              EREP_BASE)
#define EINJ                        ((EINJ_T*)              EINJ_BASE)
#define FLASH                       ((FLASH_T*)             FLASH_BASE)
#define DMACHM                      ((DMACHM_T*)            DMACHM_BASE)
#define CAN0                    ((CAN_T*)           CAN0_BASE)
#define CAN1                    ((CAN_T*)           CAN1_BASE)
#define CAN2                    ((CAN_T*)           CAN2_BASE)
#define CFGTMR0                       ((CFGTMR_T*)              CFGTMR0_BASE)
#define CFGTMR1                       ((CFGTMR_T*)              CFGTMR1_BASE)
#define CFGTMR2                       ((CFGTMR_T*)              CFGTMR2_BASE)
#define CFGTMR3                       ((CFGTMR_T*)              CFGTMR3_BASE)
#define CFGTMR4                       ((CFGTMR_T*)              CFGTMR4_BASE)
#define CFGTMR5                       ((CFGTMR_T*)              CFGTMR5_BASE)
#define ADC0                        ((ADC_T*)               ADC0_BASE)
#define ADC1                        ((ADC_T*)               ADC1_BASE)
#define LPSPI0                      ((LPSPI_T*)             LPSPI0_BASE)
#define LPSPI1                      ((LPSPI_T*)             LPSPI1_BASE)
#define LPSPI2                      ((LPSPI_T*)             LPSPI2_BASE)
#define PDU0                        ((PDU_T*)               PDU0_BASE)
#define PDU1                        ((PDU_T*)               PDU1_BASE)
#define CRC                         ((CRC_T*)               CRC_BASE)
#define LPITMR                      ((LPITMR_T*)            LPITMR_BASE)
#define RTC                         ((RTC_T*)               RTC_BASE)
#define LPTMR                       ((LPTMR_T*)             LPTMR_BASE)
#define SIM                         ((SIM_T*)               SIM_BASE)
#define PMA                         ((PM_T*)                PMA_BASE)
#define PMB                         ((PM_T*)                PMB_BASE)
#define PMC                         ((PM_T*)                PMC_BASE)
#define PMD                         ((PM_T*)                PMD_BASE)
#define PME                         ((PM_T*)                PME_BASE)
#define WDT                         ((WDT_T*)               WDT_BASE)
#define CFGIO                       ((CFGIO_T*)             CFGIO_BASE)
#define EWDT                        ((EWDT_T*)              EWDT_BASE)
#define TMC                         ((TMC_T*)               TMC_BASE)
#define SCG                         ((SCG_T*)               SCG_BASE)
#define PCM                         ((PCM_T*)               PCM_BASE)
#define LPI2C                       ((LPI2C_T*)             LPI2C_BASE)
#define LPUART0                     ((LPUART_T*)            LPUART0_BASE)
#define LPUART1                     ((LPUART_T*)            LPUART1_BASE)
#define LPUART2                     ((LPUART_T*)            LPUART2_BASE)
#define COMP                        ((COMP_T*)              COMP_BASE)
#define PMU                         ((PMU_T*)               PMU_BASE)
#define SYSMC                       ((SYSMC_T*)             SYSMC_BASE)
#define RMU                         ((RMU_T*)               RMU_BASE)
#define GPIOA                       ((GPIO_T*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_T*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_T*)              GPIOC_BASE)
#define GPIOD                       ((GPIO_T*)              GPIOD_BASE)
#define GPIOE                       ((GPIO_T*)              GPIOE_BASE)
#define APM32_SCB                     ((APM32_SCB_T*)           APM32_SCB_BASE)
#define APM32_SysTick                 ((APM32_SysTick_T*)       APM32_SysTick_BASE)
#define APM32_NVIC                    ((APM32_NVIC_T*)          APM32_NVIC_BASE)
#define MC                          ((MC_T*)                MC_BASE)
#define LMC                         ((LMC_T*)               LMC_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                           defined Values Peripheral Section                            ================ */
/* =========================================================================================================================== */


/** @addtogroup Macros_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                         CSE_PRAM                                          ================ */
/* =========================================================================================================================== */



/* =========================================================================================================================== */
/* ================                                            AC                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  MPRIA  ========================================================= */
/* ===============================================  AC MPRIA MPLCFG3 [16..16]  =============================================== */
/* AC_MPRIA_MPLCFG2 */
  #define    AC_MPRIA_MPLCFG3_0                     0U      /* 0 : Accesses from this master are forced to user-mode.          */
  #define    AC_MPRIA_MPLCFG3_1                     1U      /* 1 : Accesses from this master are not forced to user-mode.      */


/* ================================================  AC MPRIA MTWA3 [17..17]  ================================================ */
/* AC_MPRIA_MTWA2 */
 #define    AC_MPRIA_MTWA3_0                       0U    /* 0 : This master is not trusted for write accesses.                 */
 #define    AC_MPRIA_MTWA3_1                       1U     /* 1 : This master is trusted for write accesses.                    */


/* ================================================  AC MPRIA MTRA3 [18..18]  ================================================ */
/* AC_MPRIA_MTRA2 */
#define  AC_MPRIA_MTRA3_0                            0U      /* 0 : This master is not trusted for read accesses.              */
#define  AC_MPRIA_MTRA3_1                            1U      /* 1 : This master is trusted for read accesses.                  */


/* ===============================================  AC MPRIA MPLCFG2 [20..20]  =============================================== */
/* AC_MPRIA_MPLCFG2 */
  #define    AC_MPRIA_MPLCFG2_0                     0U      /* 0 : Accesses from this master are forced to user-mode.          */
  #define    AC_MPRIA_MPLCFG2_1                     1U      /* 1 : Accesses from this master are not forced to user-mode.      */


/* ================================================  AC MPRIA MTWA2 [21..21]  ================================================ */
/* AC_MPRIA_MTWA2 */
 #define    AC_MPRIA_MTWA2_0                       0U    /* 0 : This master is not trusted for write accesses.                 */
 #define    AC_MPRIA_MTWA2_1                       1U     /* 1 : This master is trusted for write accesses.                    */


/* ================================================  AC MPRIA MTRA2 [22..22]  ================================================ */
/* AC_MPRIA_MTRA2 */
#define  AC_MPRIA_MTRA2_0                            0U      /* 0 : This master is not trusted for read accesses.              */
#define  AC_MPRIA_MTRA2_1                            1U      /* 1 : This master is trusted for read accesses.                  */


/* ===============================================  AC MPRIA MPLCFG1 [24..24]  =============================================== */
/* AC_MPRIA_MPLCFG1 */
#define  AC_MPRIA_MPLCFG1_0                            0U     /* 0 : Accesses from this master are forced to user-mode.        */
#define  AC_MPRIA_MPLCFG1_1                            1U     /* 1 : Accesses from this master are not forced to user-mode.    */


/* ================================================  AC MPRIA MTWA1 [25..25]  ================================================ */
/* AC_MPRIA_MTWA1 */
#define  AC_MPRIA_MTWA1_0                            0U      /* 0 : This master is not trusted for write accesses.             */
#define  AC_MPRIA_MTWA1_1                            1U      /* 1 : This master is trusted for write accesses.                 */


/* ================================================  AC MPRIA MTRA1 [26..26]  ================================================ */
/* AC_MPRIA_MTRA1 */
#define  AC_MPRIA_MTRA1_0                            0U     /* 0 : This master is not trusted for read accesses.                */
#define  AC_MPRIA_MTRA1_1                            1U     /* 1 : This master is trusted for read accesses.                    */


/*                                                  AC MPRIA MPLCFG0 [28..28]                                                  */
/* AC_MPRIA_MPLCFG0 */
#define  AC_MPRIA_MPLCFG0_0                            0U     /* 0 : Accesses from this master are forced to user-mode.         */
#define  AC_MPRIA_MPLCFG0_1                            1U     /* 1 : Accesses from this master are not forced to user-mode.     */


/*                                                   AC MPRIA MTWA0 [29..29]                                                   */
                                /* AC_MPRIA_MTWA0                                                            */
#define  AC_MPRIA_MTWA0_0                            0U     /* 0 : This master is not trusted for write accesses.             */
#define  AC_MPRIA_MTWA0_1                            1U     /* 1 : This master is trusted for write accesses.                 */


/*                                                   AC MPRIA MTRA0 [30..30]                                                   */
/* AC_MPRIA_MTRA0  */
#define  AC_MPRIA_MTRA0_0                            0U     /* 0 : This master is not trusted for read accesses.               */
#define  AC_MPRIA_MTRA0_1                            1U     /* 1 : This master is trusted for read accesses.                   */


/*                                                          PACCTRLA                                                           */
/*                                                 AC PACCTRLA TPCFG1 [24..24]                                                 */
/* AC_PACCTRLA_TPCFG1 */
#define  AC_PACCTRLA_TPCFG1_0                        0U     /* 0 : Accesses from an untrusted master are allowed.             */
#define  AC_PACCTRLA_TPCFG1_1                        1U     /* 1 : Accesses from an untrusted master are not allowed.         */


/*                                                 AC PACCTRLA WPCFG1 [25..25]                                                 */
/* AC_PACCTRLA_WPCFG1 */
 #define AC_PACCTRLA_WPCFG1_0                        0U     /* 0 : This peripheral allows write accesses.                     */
 #define AC_PACCTRLA_WPCFG1_1                        1U     /* 1 : This peripheral is write protected.                        */


/*                                                 AC PACCTRLA SPCFG1 [26..26]                                                 */
/* AC_PACCTRLA_SPCFG1 */
 #define AC_PACCTRLA_SPCFG1_0                        0U     /* 0 : This peripheral does not require supervisor privilege level
                                                                 for accesses.                                              */
 #define AC_PACCTRLA_SPCFG1_1                        1U     /* 1 : This peripheral requires supervisor privilege level for
                                                                 accesses.                                                   */


/*                                                 AC PACCTRLA TPCFG0 [28..28]                                                 */
/* AC_PACCTRLA_TPCFG0*/
#define  AC_PACCTRLA_TPCFG0_0                        0U     /* 0 : Accesses from an untrusted master are allowed.               */
#define  AC_PACCTRLA_TPCFG0_1                        1U     /* 1 : Accesses from an untrusted master are not allowed.           */


/*                                                 AC PACCTRLA WPCFG0 [29..29]                                                 */
/* AC_PACCTRLA_WPCFG0 */
#define  AC_PACCTRLA_WPCFG0_0                        0U     /* 0 : This peripheral allows write accesses.                      */
#define  AC_PACCTRLA_WPCFG0_1                        1U     /* 1 : This peripheral is write protected.                         */


/*                                                 AC PACCTRLA SPCFG0 [30..30]                                                 */
/* AC_PACCTRLA_SPCFG0*/
#define  AC_PACCTRLA_SPCFG0_0                        0U     /* 0 : This peripheral does not require supervisor privilege level
                                                            for accesses.                                                      */
#define AC_PACCTRLA_SPCFG0_1                        1U     /* 1 : This peripheral requires supervisor privilege level for
                                                            accesses.                                                          */


/*                                                          PACCTRLB                                                           */
/*                                                  AC PACCTRLB TPCFG5 [8..8]                                                  */
/* AC_PACCTRLB_TPCFG5*/
#define  AC_PACCTRLB_TPCFG5_0                        0U     /* 0 : Accesses from an untrusted master are allowed.               */
#define  AC_PACCTRLB_TPCFG5_1                        1U     /* 1 : Accesses from an untrusted master are not allowed.          */


/*                                                  AC PACCTRLB WPCFG5 [9..9]                                                  */
/* AC_PACCTRLB_WPCFG5*/
#define  AC_PACCTRLB_WPCFG5_0                        0U     /* 0 : This peripheral allows write accesses.                      */
#define  AC_PACCTRLB_WPCFG5_1                        1U     /* 1 : This peripheral is write protected.                         */


/*                                                 AC PACCTRLB SPCFG5 [10..10]                                                 */
/* AC_PACCTRLB_SPCFG5  */
#define  AC_PACCTRLB_SPCFG5_0                        0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_PACCTRLB_SPCFG5_1                        1U     /* 1 : This peripheral requires supervisor privilege level for
                                                     accesses.           */


/*                                                 AC PACCTRLB TPCFG1 [24..24]                                                 */
/* AC_PACCTRLB_TPCFG1  */
#define  AC_PACCTRLB_TPCFG1_0                        0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_PACCTRLB_TPCFG1_1                        1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC PACCTRLB WPCFG1 [25..25]                                                 */
/* AC_PACCTRLB_WPCFG1  */
#define  AC_PACCTRLB_WPCFG1_0                        0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_PACCTRLB_WPCFG1_1                        1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC PACCTRLB SPCFG1 [26..26]                                                 */
 /* AC_PACCTRLB_SPCFG1  */
#define  AC_PACCTRLB_SPCFG1_0                        0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_PACCTRLB_SPCFG1_1                        1U     /* 1 : This peripheral requires supervisor privilege level for
                                                     accesses.           */


/*                                                 AC PACCTRLB TPCFG0 [28..28]                                                 */
/* AC_PACCTRLB_TPCFG0  */
#define  AC_PACCTRLB_TPCFG0_0                        0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_PACCTRLB_TPCFG0_1                        1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC PACCTRLB WPCFG0 [29..29]                                                 */
/* AC_PACCTRLB_WPCFG0  */
#define  AC_PACCTRLB_WPCFG0_0                        0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_PACCTRLB_WPCFG0_1                        1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC PACCTRLB SPCFG0 [30..30]                                                 */
/* AC_PACCTRLB_SPCFG0  */
#define  AC_PACCTRLB_SPCFG0_0                        0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_PACCTRLB_SPCFG0_1                        1U     /* 1 : This peripheral requires supervisor privilege level for
                                                         accesses.           */


/*                                                          PACCTRLD     */
/*                                                 AC PACCTRLD TPCFG1 [24..24]                                                 */
 /* AC_PACCTRLD_TPCFG1  */
#define  AC_PACCTRLD_TPCFG1_0                   0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_PACCTRLD_TPCFG1_1                   1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC PACCTRLD WPCFG1 [25..25]                                                 */
/* AC_PACCTRLD_WPCFG1  */
#define  AC_PACCTRLD_WPCFG1_0                   0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_PACCTRLD_WPCFG1_1                   1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC PACCTRLD SPCFG1 [26..26]                                                 */
/* AC_PACCTRLD_SPCFG1  */
#define  AC_PACCTRLD_SPCFG1_0                   0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_PACCTRLD_SPCFG1_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                         accesses.           */


/*                                                 AC PACCTRLD TPCFG0 [28..28]                                                 */
/* AC_PACCTRLD_TPCFG0  */
#define  AC_PACCTRLD_TPCFG0_0                   0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_PACCTRLD_TPCFG0_1                   1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC PACCTRLD WPCFG0 [29..29]                                                 */
/* AC_PACCTRLD_WPCFG0  */
#define  AC_PACCTRLD_WPCFG0_0                   0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_PACCTRLD_WPCFG0_1                   1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC PACCTRLD SPCFG0 [30..30]                                                 */
/* AC_PACCTRLD_SPCFG0  */
 #define AC_PACCTRLD_SPCFG0_0                   0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
 #define AC_PACCTRLD_SPCFG0_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                          OPACCTRLA    */
/*                                                 AC OPACCTRLA TPCFG7 [0..0]                                                  */
/* AC_OPACCTRLA_TPCFG7 */
#define  AC_OPACCTRLA_TPCFG7_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLA_TPCFG7_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLA WPCFG7 [1..1]                                                  */
/* AC_OPACCTRLA_WPCFG7 */
#define  AC_OPACCTRLA_WPCFG7_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLA_WPCFG7_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC OPACCTRLA SPCFG7 [2..2]                                                  */
/* AC_OPACCTRLA_SPCFG7 */
 #define AC_OPACCTRLA_SPCFG7_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
 #define AC_OPACCTRLA_SPCFG7_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                 AC OPACCTRLA TPCFG6 [4..4]                                                  */
/* AC_OPACCTRLA_TPCFG6 */
#define  AC_OPACCTRLA_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLA_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLA WPCFG6 [5..5]                                                  */
/* AC_OPACCTRLA_WPCFG6 */
#define  AC_OPACCTRLA_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLA_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC OPACCTRLA SPCFG6 [6..6]                                                  */
/* AC_OPACCTRLA_SPCFG6 */
 #define AC_OPACCTRLA_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
 #define AC_OPACCTRLA_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                 AC OPACCTRLA TPCFG5 [8..8]                                                  */
 /* AC_OPACCTRLA_TPCFG5 */
 #define AC_OPACCTRLA_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
 #define AC_OPACCTRLA_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLA WPCFG5 [9..9]                                                  */
/* AC_OPACCTRLA_WPCFG5 */
 #define AC_OPACCTRLA_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                                */
 #define AC_OPACCTRLA_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLA SPCFG5 [10..10]                                                 */
/* AC_OPACCTRLA_SPCFG5 */
 #define AC_OPACCTRLA_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
 #define AC_OPACCTRLA_SPCFG5_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLA TPCFG4 [12..12]                                                 */
   /* AC_OPACCTRLA_TPCFG4 */
#define  AC_OPACCTRLA_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLA_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLA WPCFG4 [13..13]                                                 */
 /* AC_OPACCTRLA_WPCFG4 */
#define  AC_OPACCTRLA_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLA_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLA SPCFG4 [14..14]                                                 */
   /* AC_OPACCTRLA_SPCFG4 */
 #define AC_OPACCTRLA_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
 #define AC_OPACCTRLA_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLA TPCFG1 [24..24]                                                 */
/* AC_OPACCTRLA_TPCFG1 */
 #define AC_OPACCTRLA_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
 #define AC_OPACCTRLA_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLA WPCFG1 [25..25]                                                 */
   /* AC_OPACCTRLA_WPCFG1 */
 #define AC_OPACCTRLA_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                                */
 #define AC_OPACCTRLA_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLA SPCFG1 [26..26]                                                 */
  /* AC_OPACCTRLA_SPCFG1 */
 #define AC_OPACCTRLA_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLA_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
#define                                                     accesses.           */


/*                                                AC OPACCTRLA TPCFG0 [28..28]                                                 */
   /* AC_OPACCTRLA_TPCFG0 */
#define  AC_OPACCTRLA_TPCFG0_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLA_TPCFG0_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLA WPCFG0 [29..29]                                                 */
  /* AC_OPACCTRLA_WPCFG0 */
#define  AC_OPACCTRLA_WPCFG0_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLA_WPCFG0_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLA SPCFG0 [30..30]                                                 */
/* AC_OPACCTRLA_SPCFG0 */
 #define AC_OPACCTRLA_SPCFG0_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLA_SPCFG0_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLB    */
/*                                                 AC OPACCTRLB TPCFG6 [4..4]                                                  */
 /* AC_OPACCTRLB_TPCFG6 */
#define  AC_OPACCTRLB_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLB_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLB WPCFG6 [5..5]                                                  */
/* AC_OPACCTRLB_WPCFG6 */
#define  AC_OPACCTRLB_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLB_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC OPACCTRLB SPCFG6 [6..6]                                                  */
/* AC_OPACCTRLB_SPCFG6 */
 #define AC_OPACCTRLB_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
 #define AC_OPACCTRLB_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                 AC OPACCTRLB TPCFG5 [8..8]                                                  */
  /* AC_OPACCTRLB_TPCFG5 */
 #define AC_OPACCTRLB_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
 #define AC_OPACCTRLB_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLB WPCFG5 [9..9]                                                  */
 /* AC_OPACCTRLB_WPCFG5 */
 #define AC_OPACCTRLB_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                                */
 #define AC_OPACCTRLB_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLB SPCFG5 [10..10]                                                 */
/* AC_OPACCTRLB_SPCFG5 */
#define  AC_OPACCTRLB_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define AC_OPACCTRLB_SPCFG5_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLB TPCFG4 [12..12]                                                 */
   /* AC_OPACCTRLB_TPCFG4 */
#define  AC_OPACCTRLB_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLB_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLB WPCFG4 [13..13]                                                 */
 /* AC_OPACCTRLB_WPCFG4 */
#define  AC_OPACCTRLB_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLB_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLB SPCFG4 [14..14]                                                 */
 /* AC_OPACCTRLB_SPCFG4 */
#define  AC_OPACCTRLB_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLB_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLB TPCFG3 [16..16]                                                 */
   /* AC_OPACCTRLB_TPCFG3 */
#define  AC_OPACCTRLB_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLB_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLB WPCFG3 [17..17]                                                 */
/* AC_OPACCTRLB_WPCFG3 */
#define  AC_OPACCTRLB_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLB_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLB SPCFG3 [18..18]                                                 */
 /* AC_OPACCTRLB_SPCFG3 */
#define  AC_OPACCTRLB_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLB_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLC    */
/*                                                 AC OPACCTRLC TPCFG7 [0..0]                                                  */
/* AC_OPACCTRLC_TPCFG7 */
#define  AC_OPACCTRLC_TPCFG7_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLC_TPCFG7_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLC WPCFG7 [1..1]                                                  */
 /* AC_OPACCTRLC_WPCFG7 */
 #define AC_OPACCTRLC_WPCFG7_0                  0U     /* 0 : This peripheral allows write accesses.                                */
 #define AC_OPACCTRLC_WPCFG7_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC OPACCTRLC SPCFG7 [2..2]                                                  */
 /* AC_OPACCTRLC_SPCFG7 */
#define  AC_OPACCTRLC_SPCFG7_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define AC_OPACCTRLC_SPCFG7_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                 AC OPACCTRLC TPCFG6 [4..4]                                                  */
/* AC_OPACCTRLC_TPCFG6 */
#define  AC_OPACCTRLC_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLC_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLC WPCFG6 [5..5]                                                  */
 /* AC_OPACCTRLC_WPCFG6 */
#define  AC_OPACCTRLC_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLC_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                 AC OPACCTRLC SPCFG6 [6..6]                                                  */
 /* AC_OPACCTRLC_SPCFG6 */
#define  AC_OPACCTRLC_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                         for accesses.       */
#define  AC_OPACCTRLC_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLC TPCFG2 [20..20]                                                 */
  /* AC_OPACCTRLC_TPCFG2 */
#define  AC_OPACCTRLC_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLC_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLC WPCFG2 [21..21]                                                 */
   /* AC_OPACCTRLC_WPCFG2 */
#define  AC_OPACCTRLC_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLC_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLC SPCFG2 [22..22]                                                 */
   /* AC_OPACCTRLC_SPCFG2 */
 #define AC_OPACCTRLC_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
 #define AC_OPACCTRLC_SPCFG2_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                AC OPACCTRLC TPCFG1 [24..24]                                                 */
   /* AC_OPACCTRLC_TPCFG1 */
#define  AC_OPACCTRLC_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLC_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLC WPCFG1 [25..25]                                                 */
   /* AC_OPACCTRLC_WPCFG1 */
#define  AC_OPACCTRLC_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLC_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLC SPCFG1 [26..26]                                                 */
  /* AC_OPACCTRLC_SPCFG1 */
#define  AC_OPACCTRLC_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                         for accesses.       */
#define  AC_OPACCTRLC_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                          OPACCTRLD    */
/*                                                 AC OPACCTRLD TPCFG5 [8..8]                                                  */
  /* AC_OPACCTRLD_TPCFG5 */
 #define AC_OPACCTRLD_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
 #define AC_OPACCTRLD_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                 AC OPACCTRLD WPCFG5 [9..9]                                                  */
  /* AC_OPACCTRLD_WPCFG5 */
#define  AC_OPACCTRLD_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLD_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLD SPCFG5 [10..10]                                                 */
  /* AC_OPACCTRLD_SPCFG5 */
#define  AC_OPACCTRLD_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
#define  AC_OPACCTRLD_SPCFG5_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLD TPCFG3 [16..16]                                                 */
  /* AC_OPACCTRLD_TPCFG3 */
 #define AC_OPACCTRLD_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
 #define AC_OPACCTRLD_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLD WPCFG3 [17..17]                                                 */
 /* AC_OPACCTRLD_WPCFG3 */
#define  AC_OPACCTRLD_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLD_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLD SPCFG3 [18..18]                                                 */
 /* AC_OPACCTRLD_SPCFG3 */
#define  AC_OPACCTRLD_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define  AC_OPACCTRLD_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLD TPCFG2 [20..20]                                                 */
   /* AC_OPACCTRLD_TPCFG2 */
#define  AC_OPACCTRLD_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLD_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLD WPCFG2 [21..21]                                                 */
   /* AC_OPACCTRLD_WPCFG2 */
#define  AC_OPACCTRLD_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLD_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLD SPCFG2 [22..22]                                                 */
   /* AC_OPACCTRLD_SPCFG2 */
#define  AC_OPACCTRLD_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                         for accesses.       */
#define  AC_OPACCTRLD_SPCFG2_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLD TPCFG1 [24..24]                                                 */
   /* AC_OPACCTRLD_TPCFG1 */
#define  AC_OPACCTRLD_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                        */
#define  AC_OPACCTRLD_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                    */


/*                                                AC OPACCTRLD WPCFG1 [25..25]                                                 */
   /* AC_OPACCTRLD_WPCFG1 */
#define  AC_OPACCTRLD_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                                */
#define  AC_OPACCTRLD_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                                   */


/*                                                AC OPACCTRLD SPCFG1 [26..26]                                                 */
  /* AC_OPACCTRLD_SPCFG1 */
#define  AC_OPACCTRLD_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLD_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                AC OPACCTRLD TPCFG0 [28..28]                                                 */
  /* AC_OPACCTRLD_TPCFG0 */
#define  AC_OPACCTRLD_TPCFG0_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLD_TPCFG0_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.              */


/*                                                AC OPACCTRLD WPCFG0 [29..29]                                                 */
/* AC_OPACCTRLD_WPCFG0 */
#define  AC_OPACCTRLD_WPCFG0_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLD_WPCFG0_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLD SPCFG0 [30..30]                                                 */
  /* AC_OPACCTRLD_SPCFG0 */
 #define AC_OPACCTRLD_SPCFG0_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
 #define AC_OPACCTRLD_SPCFG0_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLE    */
/*                                                 AC OPACCTRLE TPCFG6 [4..4]                                                  */
 /* AC_OPACCTRLE_TPCFG6 */
#define  AC_OPACCTRLE_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLE_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLE WPCFG6 [5..5]                                                  */
  /* AC_OPACCTRLE_WPCFG6 */
#define  AC_OPACCTRLE_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLE_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                 AC OPACCTRLE SPCFG6 [6..6]                                                  */
 /* AC_OPACCTRLE_SPCFG6 */
#define  AC_OPACCTRLE_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLE_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLE TPCFG0 [28..28]                                                 */
  /* AC_OPACCTRLE_TPCFG0 */
#define  AC_OPACCTRLE_TPCFG0_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLE_TPCFG0_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLE WPCFG0 [29..29]                                                 */
  /* AC_OPACCTRLE_WPCFG0 */
#define  AC_OPACCTRLE_WPCFG0_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLE_WPCFG0_1                  1U     /* 1 : This peripheral is write protected.                               */


/*                                                AC OPACCTRLE SPCFG0 [30..30]                                                 */
 /* AC_OPACCTRLE_SPCFG0 */
 #define AC_OPACCTRLE_SPCFG0_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
 #define AC_OPACCTRLE_SPCFG0_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                          OPACCTRLF    */
/*                                                 AC OPACCTRLF TPCFG5 [8..8]                                                  */
  /* AC_OPACCTRLF_TPCFG5 */
#define  AC_OPACCTRLF_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLF_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLF WPCFG5 [9..9]                                                  */
  /* AC_OPACCTRLF_WPCFG5 */
#define  AC_OPACCTRLF_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLF_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                             */


/*                                                AC OPACCTRLF SPCFG5 [10..10]                                                 */
/* AC_OPACCTRLF_SPCFG5 */
#define  AC_OPACCTRLF_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define AC_OPACCTRLF_SPCFG5_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLF TPCFG4 [12..12]                                                 */
   /* AC_OPACCTRLF_TPCFG4 */
#define  AC_OPACCTRLF_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                    */
#define  AC_OPACCTRLF_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                */


/*                                                AC OPACCTRLF WPCFG4 [13..13]                                                 */
/* AC_OPACCTRLF_WPCFG4 */
#define  AC_OPACCTRLF_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLF_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLF SPCFG4 [14..14]                                                 */
  /* AC_OPACCTRLF_SPCFG4 */
#define  AC_OPACCTRLF_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define  AC_OPACCTRLF_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLF TPCFG3 [16..16]                                                 */
 /* AC_OPACCTRLF_TPCFG3 */
#define  AC_OPACCTRLF_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLF_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLF WPCFG3 [17..17]                                                 */
  /* AC_OPACCTRLF_WPCFG3 */
#define  AC_OPACCTRLF_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLF_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLF SPCFG3 [18..18]                                                 */
 /* AC_OPACCTRLF_SPCFG3 */
#define  AC_OPACCTRLF_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
#define  AC_OPACCTRLF_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLF TPCFG2 [20..20]                                                 */
 /* AC_OPACCTRLF_TPCFG2 */
#define  AC_OPACCTRLF_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLF_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLF WPCFG2 [21..21]                                                 */
 /* AC_OPACCTRLF_WPCFG2 */
#define  AC_OPACCTRLF_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLF_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLF SPCFG2 [22..22]                                                 */
  /* AC_OPACCTRLF_SPCFG2 */
#define  AC_OPACCTRLF_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                               for accesses.       */
#define AC_OPACCTRLF_SPCFG2_1                   1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLF TPCFG1 [24..24]                                                 */
/* AC_OPACCTRLF_TPCFG1 */
#define  AC_OPACCTRLF_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                    */
#define  AC_OPACCTRLF_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.                */


/*                                                AC OPACCTRLF WPCFG1 [25..25]                                                 */
 /* AC_OPACCTRLF_WPCFG1 */
 #define AC_OPACCTRLF_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                             */
 #define AC_OPACCTRLF_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                                */


/*                                                AC OPACCTRLF SPCFG1 [26..26]                                                 */
 /* AC_OPACCTRLF_SPCFG1 */
#define  AC_OPACCTRLF_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLF_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                     accesses.           */


/*                                                AC OPACCTRLF TPCFG0 [28..28]                                                 */
/* AC_OPACCTRLF_TPCFG0 */
#define  AC_OPACCTRLF_TPCFG0_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                  */
#define  AC_OPACCTRLF_TPCFG0_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.              */


/*                                                AC OPACCTRLF WPCFG0 [29..29]                                                 */
 /* AC_OPACCTRLF_WPCFG0 */
#define  AC_OPACCTRLF_WPCFG0_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLF_WPCFG0_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLF SPCFG0 [30..30]                                                 */
  /* AC_OPACCTRLF_SPCFG0 */
#define AC_OPACCTRLF_SPCFG0_0                   0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define AC_OPACCTRLF_SPCFG0_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLG    */
/*                                                AC OPACCTRLG TPCFG5 [8..8]                                                 */
  /* AC_OPACCTRLG_TPCFG5 */
#define  AC_OPACCTRLG_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                  */
#define  AC_OPACCTRLG_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.              */


/*                                                AAC OPACCTRLG TPCFG5 [9..9]                                                 */
   /* AC_OPACCTRLG_WPCFG5 */
#define  AC_OPACCTRLG_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                          */
#define  AC_OPACCTRLG_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                             */


/*                                                AC OPACCTRLG TPCFG5 [10..10]                                                 */
  /* AC_OPACCTRLG_SPCFG5 */
#define  AC_OPACCTRLG_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLG_SPCFG5_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */

/*                                                AC OPACCTRLG TPCFG4 [12..12]                                                 */
  /* AC_OPACCTRLG_TPCFG4 */
#define  AC_OPACCTRLG_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLG_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLG WPCFG2 [13..13]                                                 */
   /* AC_OPACCTRLG_WPCFG4 */
#define  AC_OPACCTRLG_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLG_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLG SPCFG4 [14..14]                                                 */
  /* AC_OPACCTRLG_SPCFG4 */
#define  AC_OPACCTRLG_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLG_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */

/*                                                AC OPACCTRLG TPCFG2 [20..20]                                                 */
  /* AC_OPACCTRLG_TPCFG2 */
#define  AC_OPACCTRLG_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLG_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLG WPCFG2 [21..21]                                                 */
   /* AC_OPACCTRLG_WPCFG2 */
#define  AC_OPACCTRLG_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLG_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLG SPCFG2 [22..22]                                                 */
  /* AC_OPACCTRLG_SPCFG2 */
#define  AC_OPACCTRLG_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLG_SPCFG2_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLH    */
/*                                                AC OPACCTRLH TPCFG2 [20..20]                                                 */
  /* AC_OPACCTRLH_TPCFG2 */
#define  AC_OPACCTRLH_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLH_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLH WPCFG2 [21..21]                                                 */
 /* AC_OPACCTRLH_WPCFG2 */
#define  AC_OPACCTRLH_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLH_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLH SPCFG2 [22..22]                                                 */
 /* AC_OPACCTRLH_SPCFG2 */
#define  AC_OPACCTRLH_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                         for accesses.       */
#define  AC_OPACCTRLH_SPCFG2_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                          OPACCTRLI    */
/*                                                 AC OPACCTRLI TPCFG7 [0..0]                                                  */
 /* AC_OPACCTRLI_TPCFG7 */
#define  AC_OPACCTRLI_TPCFG7_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLI_TPCFG7_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLI WPCFG6 [1..1]                                                  */
/* AC_OPACCTRLI_WPCFG7 */
#define  AC_OPACCTRLI_WPCFG7_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLI_WPCFG7_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                 AC OPACCTRLI SPCFG6 [2..2]                                                  */
/* AC_OPACCTRLI_SPCFG7 */
#define  AC_OPACCTRLI_SPCFG7_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define  AC_OPACCTRLI_SPCFG7_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */

/*                                                 AC OPACCTRLI TPCFG6 [4..4]                                                  */
 /* AC_OPACCTRLI_TPCFG6 */
#define  AC_OPACCTRLI_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLI_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLI WPCFG6 [5..5]                                                  */
/* AC_OPACCTRLI_WPCFG6 */
#define  AC_OPACCTRLI_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLI_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                               */


/*                                                 AC OPACCTRLI SPCFG6 [6..6]                                                  */
/* AC_OPACCTRLI_SPCFG6 */
#define  AC_OPACCTRLI_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.       */
#define  AC_OPACCTRLI_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.           */


/*                                                 AC OPACCTRLI TPCFG5 [8..8]                                                  */
/* AC_OPACCTRLI_TPCFG5 */
#define  AC_OPACCTRLI_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLI_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLI WPCFG5 [9..9]                                                  */
 /* AC_OPACCTRLI_WPCFG5 */
#define  AC_OPACCTRLI_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                          */
#define  AC_OPACCTRLI_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLI SPCFG5 [10..10]                                                 */
/* AC_OPACCTRLI_SPCFG5 */
#define  AC_OPACCTRLI_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
#define  AC_OPACCTRLI_SPCFG5_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLI TPCFG4 [12..12]                                                 */
 /* AC_OPACCTRLI_TPCFG4 */
#define  AC_OPACCTRLI_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLI_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLI WPCFG4 [13..13]                                                 */
 /* AC_OPACCTRLI_WPCFG4 */
#define  AC_OPACCTRLI_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLI_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLI SPCFG4 [14..14]                                                 */
   /* AC_OPACCTRLI_SPCFG4 */
#define  AC_OPACCTRLI_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.       */
#define  AC_OPACCTRLI_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                AC OPACCTRLI TPCFG3 [16..16]                                                 */
   /* AC_OPACCTRLI_TPCFG3 */
#define  AC_OPACCTRLI_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLI_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLI WPCFG3 [17..17]                                                 */
  /* AC_OPACCTRLI_WPCFG3 */
#define  AC_OPACCTRLI_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLI_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLI SPCFG3 [18..18]                                                 */
  /* AC_OPACCTRLI_SPCFG3 */
#define  AC_OPACCTRLI_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.       */
#define  AC_OPACCTRLI_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */


/*                                                AC OPACCTRLI TPCFG1 [24..24]                                                 */
 /* AC_OPACCTRLI_TPCFG1 */
#define  AC_OPACCTRLI_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                  */
#define  AC_OPACCTRLI_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.              */


/*                                                AC OPACCTRLI WPCFG1 [25..25]                                                 */
  /* AC_OPACCTRLI_WPCFG1 */
#define  AC_OPACCTRLI_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLI_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLI SPCFG1 [26..26]                                                 */
   /* AC_OPACCTRLI_SPCFG1 */
#define  AC_OPACCTRLI_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_OPACCTRLI_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.           */


/*                                                          OPACCTRLJ    */
/*                                                AC OPACCTRLJ TPCFG7 [0..0]                                                 */
 /* AC_OPACCTRLJ_TPCFG7 */
#define  AC_OPACCTRLJ_TPCFG7_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                 */
#define  AC_OPACCTRLJ_TPCFG7_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.             */


/*                                                AC OPACCTRLJ WPCFG7 [1..1]                                                 */
 /* AC_OPACCTRLJ_WPCFG7 */
#define  AC_OPACCTRLJ_WPCFG7_0                  0U     /* 0 : This peripheral allows write accesses.                         */
#define  AC_OPACCTRLJ_WPCFG7_1                  1U     /* 1 : This peripheral is write protected.                            */


/*                                                AC OPACCTRLJ SPCFG7 [2..2]                                                 */
/* AC_OPACCTRLJ_SPCFG7 */
#define  AC_OPACCTRLJ_SPCFG7_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_OPACCTRLJ_SPCFG7_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */

/*                                                AC OPACCTRLJ TPCFG6 [4..4]                                                 */
 /* AC_OPACCTRLJ_TPCFG6 */
#define  AC_OPACCTRLJ_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                 */
#define  AC_OPACCTRLJ_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.             */


/*                                                AC OPACCTRLJ WPCFG6 [5..5]                                                 */
 /* AC_OPACCTRLJ_WPCFG6 */
#define  AC_OPACCTRLJ_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                         */
#define  AC_OPACCTRLJ_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                            */


/*                                                AC OPACCTRLJ SPCFG6 [6..6]                                                 */
/* AC_OPACCTRLJ_SPCFG6 */
#define  AC_OPACCTRLJ_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_OPACCTRLJ_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */

/*                                                AC OPACCTRLJ TPCFG4 [12..12]                                                 */
 /* AC_OPACCTRLJ_TPCFG4 */
#define  AC_OPACCTRLJ_TPCFG4_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLJ_TPCFG4_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLJ WPCFG4 [13..13]                                                 */
 /* AC_OPACCTRLJ_WPCFG4 */
#define  AC_OPACCTRLJ_WPCFG4_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLJ_WPCFG4_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLJ SPCFG4 [14..14]                                                 */
/* AC_OPACCTRLJ_SPCFG4 */
#define  AC_OPACCTRLJ_SPCFG4_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                    for accesses.       */
#define  AC_OPACCTRLJ_SPCFG4_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                       accesses.           */

/*                                                AC OPACCTRLJ TPCFG3 [16..16]                                                 */
/* AC_OPACCTRLJ_TPCFG3 */
#define  AC_OPACCTRLJ_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLJ_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLJ WPCFG3 [17..17]                                                 */
  /* AC_OPACCTRLJ_WPCFG3 */
#define  AC_OPACCTRLJ_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                            */
#define  AC_OPACCTRLJ_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                               */


/*                                                AC OPACCTRLJ SPCFG3 [18..18]                                                 */
/* AC_OPACCTRLJ_SPCFG3 */
 #define AC_OPACCTRLJ_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.     */
 #define AC_OPACCTRLJ_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.          */


/*                                                AC OPACCTRLJ TPCFG2 [20..20]                                                 */
  /* AC_OPACCTRLJ_TPCFG2 */
#define  AC_OPACCTRLJ_TPCFG2_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLJ_TPCFG2_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLJ WPCFG2 [21..21]                                                 */
  /* AC_OPACCTRLJ_WPCFG2 */
#define  AC_OPACCTRLJ_WPCFG2_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLJ_WPCFG2_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLJ SPCFG2 [22..22]                                                 */
  /* AC_OPACCTRLJ_SPCFG2 */
#define  AC_OPACCTRLJ_SPCFG2_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.    */
#define  AC_OPACCTRLJ_SPCFG2_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.        */


/*                                                AC OPACCTRLK TPCFG6 [4..4]                                                 */
/* AC_OPACCTRLK_TPCFG3 */
#define  AC_OPACCTRLK_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                 */
#define  AC_OPACCTRLK_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.             */

/*                                                AC OPACCTRLK WPCFG6 [5..5]                                                 */
/* AC_OPACCTRLK_WPCFG3 */
 #define AC_OPACCTRLK_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                         */
 #define AC_OPACCTRLK_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                            */

/*                                                AC OPACCTRLK SPCFG6 [6..6]                                                 */
/* AC_OPACCTRLK_SPCFG6 */
 #define AC_OPACCTRLK_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.     */
 #define AC_OPACCTRLK_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.         */


/*                                                AC OPACCTRLK TPCFG3 [16..16]                                                 */
/* AC_OPACCTRLK_TPCFG3  */
#define  AC_OPACCTRLK_TPCFG3_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLK_TPCFG3_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLK WPCFG3 [17..17]                                                 */
/* AC_OPACCTRLK_WPCFG3 */
 #define AC_OPACCTRLK_WPCFG3_0                  0U     /* 0 : This peripheral allows write accesses.                           */
 #define AC_OPACCTRLK_WPCFG3_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLK SPCFG3 [18..18]                                                 */
 /* AC_OPACCTRLK_SPCFG3 */
 #define AC_OPACCTRLK_SPCFG3_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.      */
 #define AC_OPACCTRLK_SPCFG3_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.          */


/*                                                AC OPACCTRLK TPCFG1 [24..24]                                                 */
/* AC_OPACCTRLK_TPCFG1 */
#define  AC_OPACCTRLK_TPCFG1_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLK_TPCFG1_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                AC OPACCTRLK WPCFG1 [25..25]                                                 */
/* AC_OPACCTRLK_WPCFG1 */
 #define AC_OPACCTRLK_WPCFG1_0                  0U     /* 0 : This peripheral allows write accesses.                           */
 #define AC_OPACCTRLK_WPCFG1_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLK SPCFG1 [26..26]                                               */
/* AC_OPACCTRLK_SPCFG1 */
 #define AC_OPACCTRLK_SPCFG1_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.    */
 #define AC_OPACCTRLK_SPCFG1_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.        */

/*                                                AC OPACCTRLK TPCFG0 [28..28]                                               */
/* AC_OPACCTRLK_TPCFG0 */
#define  AC_OPACCTRLK_TPCFG0_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                 */
#define  AC_OPACCTRLK_TPCFG0_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.             */


/*                                                AC OPACCTRLK WPCFG0 [29..29]                                               */
/* AC_OPACCTRLK_WPCFG0 */
 #define AC_OPACCTRLK_WPCFG0_0                  0U     /* 0 : This peripheral allows write accesses.                          */
 #define AC_OPACCTRLK_WPCFG0_1                  1U     /* 1 : This peripheral is write protected.                             */


/*                                                AC OPACCTRLK SPCFG0 [30..30]                                                */
 /* AC_OPACCTRLK_SPCFG0 */
 #define AC_OPACCTRLK_SPCFG0_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                      for accesses.     */
 #define AC_OPACCTRLK_SPCFG0_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.         */


/*                                                          OPACCTRLL    */
/*                                                 AC OPACCTRLL TPCFG7 [0..0]                                                  */
/* AC_OPACCTRLL_TPCFG7 */
#define  AC_OPACCTRLL_TPCFG7_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                   */
#define  AC_OPACCTRLL_TPCFG7_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.               */


/*                                                 AC OPACCTRLL WPCFG7 [1..1]                                                  */
/* AC_OPACCTRLL_WPCFG7 */
#define  AC_OPACCTRLL_WPCFG7_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLL_WPCFG7_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                 AC OPACCTRLL SPCFG7 [2..2]                                               */
/* AC_OPACCTRLL_SPCFG7 */
 #define AC_OPACCTRLL_SPCFG7_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                       for accesses.  */
 #define AC_OPACCTRLL_SPCFG7_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                      accesses.       */


/*                                                 AC OPACCTRLL TPCFG6 [4..4]                                              */
/* AC_OPACCTRLL_TPCFG6 */
 #define AC_OPACCTRLL_TPCFG6_0                  0U     /* 0 : Accesses from an untrusted master are allowed.               */
 #define AC_OPACCTRLL_TPCFG6_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.           */


/*                                                 AC OPACCTRLL WPCFG6 [5..5]                                               */
/* AC_OPACCTRLL_WPCFG6 */
#define  AC_OPACCTRLL_WPCFG6_0                  0U     /* 0 : This peripheral allows write accesses.                        */
#define  AC_OPACCTRLL_WPCFG6_1                  1U     /* 1 : This peripheral is write protected.                           */


/*                                                 AC OPACCTRLL SPCFG6 [6..6]                                               */
/* AC_OPACCTRLL_SPCFG6 */
 #define AC_OPACCTRLL_SPCFG6_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                        for accesses.  */
 #define AC_OPACCTRLL_SPCFG6_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.      */


/*                                                 AC OPACCTRLL TPCFG5 [8..8]                                                 */
/* AC_OPACCTRLL_TPCFG5*/
#define  AC_OPACCTRLL_TPCFG5_0                  0U     /* 0 : Accesses from an untrusted master are allowed.                  */
#define  AC_OPACCTRLL_TPCFG5_1                  1U     /* 1 : Accesses from an untrusted master are not allowed.              */


/*                                                 AC OPACCTRLL WPCFG5 [9..9]                                                  */
/* AC_OPACCTRLL_WPCFG5 */
#define  AC_OPACCTRLL_WPCFG5_0                  0U     /* 0 : This peripheral allows write accesses.                           */
#define  AC_OPACCTRLL_WPCFG5_1                  1U     /* 1 : This peripheral is write protected.                              */


/*                                                AC OPACCTRLL SPCFG5 [10..10]                                                 */
/* AC_OPACCTRLL_SPCFG5 */
#define  AC_OPACCTRLL_SPCFG5_0                  0U     /* 0 : This peripheral does not require supervisor privilege level
                                                         for accesses.    */
#define  AC_OPACCTRLL_SPCFG5_1                  1U     /* 1 : This peripheral requires supervisor privilege level for
                                                        accesses.         */




/* =========================================================================================================================== */
/* ================                                            MSC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  PCxTYPE  ======================================================== */
/* =======================================================  CPUxLPNUM  ======================================================= */
/* ======================================================  CPUxPBMNUM  ======================================================= */
/* ========================================================  CPUxCNT  ======================================================== */
/* ========================================================  PCxINF0  ======================================================== */
/* ========================================================  PCxINF1  ======================================================== */
/* ========================================================  PCxINF2  ======================================================== */
/* ========================================================  PCxINF3  ======================================================== */
/* ===============================================  MSC PCxINF3 FPUFLG [0..0]  =============================================== */
                                   /* MSC_PCxINF3_FPUFLG                                                        */
#define  MSC_PCxINF3_FPUFLG_0                   0U     /* 0 : FPU support is not included.                                          */
#define  MSC_PCxINF3_FPUFLG_1                   1U     /* 1 : FPU support is included.                                              */


/*                                                  MSC PCxINF3 ISEFLG [1..1]                                                  */
                                      /* MSC_PCxINF3_ISEFLG                                                        */
#define  MSC_PCxINF3_ISEFLG_0                   0U     /* 0 : SIMD/NEON support is not included.                                    */
#define  MSC_PCxINF3_ISEFLG_1                   1U     /* 1 : SIMD/NEON support is included.                                        */


/*                                                  MSC PCxINF3 JHWFLG [2..2]                                                  */
                                    /* MSC_PCxINF3_JHWFLG                                                        */
#define  MSC_PCxINF3_JHWFLG_0                   0U     /* 0 : Jazelle support is not included.                                      */
#define  MSC_PCxINF3_JHWFLG_1                   1U     /* 1 : Jazelle support is included.                                          */


/*                                                  MSC PCxINF3 MMFLG [3..3]                                                   */
                                    /* MSC_PCxINF3_MMFLG                                                         */
#define  MSC_PCxINF3_MMFLG_0                    0U     /* 0 : MMU support is not included.                                          */
#define  MSC_PCxINF3_MMFLG_1                    1U     /* 1 : MMU support is included.                                              */


/*                                                  MSC PCxINF3 TZFFLG [4..4]                                                  */
                                    /* MSC_PCxINF3_TZFFLG                                                        */
#define  MSC_PCxINF3_TZFFLG_0                   0U     /* 0 : Trust Zone support is not included.                                   */
#define  MSC_PCxINF3_TZFFLG_1                   1U     /* 1 : Trust Zone support is included.                                       */


/*                                                 MSC PCxINF3 CMPHWFLG [5..5]                                                 */
                                      /* MSC_PCxINF3_CMPHWFLG                                                      */
#define  MSC_PCxINF3_CMPHWFLG_0                 0U     /* 0 : Core Memory Protection is not included.                               */
#define  MSC_PCxINF3_CMPHWFLG_1                 1U     /* 1 : Core Memory Protection is included.                                   */


/*                                                  MSC PCxINF3 BBFLG [6..6]                                                   */
                                   /* MSC_PCxINF3_BBFLG                                                         */
#define  MSC_PCxINF3_BBFLG_0                    0U     /* 0 : Bit Banding is not supported.                                         */
#define  MSC_PCxINF3_BBFLG_1                    1U     /* 1 : Bit Banding is supported.                                             */


/* ========================================================  PC0TYPE  ======================================================== */
/* =======================================================  CPU0LPNUM  ======================================================= */
/* =======================================================  CPU0PBNUM  ======================================================= */
/* ========================================================  CPU0CNT  ======================================================== */
/* ========================================================  PC0INF0  ======================================================== */
/* ========================================================  PC0INF1  ======================================================== */
/* ========================================================  PC0INF2  ======================================================== */
/* ========================================================  PC0INF3  ======================================================== */
/* ===============================================  MSC PC0INF3 FPUFLG [0..0]  =============================================== */
                                   /* MSC_PC0INF3_FPUFLG                                                        */
#define  MSC_PC0INF3_FPUFLG_0                   0U     /* 0 : FPU support is not included.                                          */
#define  MSC_PC0INF3_FPUFLG_1                   1U     /* 1 : FPU support is included.                                              */


/*                                                  MSC PC0INF3 ISEFLG [1..1]                                                  */
                                      /* MSC_PC0INF3_ISEFLG                                                        */
#define  MSC_PC0INF3_ISEFLG_0                   0U     /* 0 : SIMD/NEON support is not included.                                    */
#define  MSC_PC0INF3_ISEFLG_1                   1U     /* 1 : SIMD/NEON support is included.                                        */


/*                                                  MSC PC0INF3 JHWFLG [2..2]                                                  */
                                   /* MSC_PC0INF3_JHWFLG                                                        */
 #define MSC_PC0INF3_JHWFLG_0                   0U     /* 0 : Jazelle support is not included.                                      */
 #define MSC_PC0INF3_JHWFLG_1                   1U     /* 1 : Jazelle support is included.                                          */


/*                                                  MSC PC0INF3 MMFLG [3..3]                                                   */
                                     /* MSC_PC0INF3_MMFLG                                                         */
#define  MSC_PC0INF3_MMFLG_0                    0U     /* 0 : MMU support is not included.                                          */
#define  MSC_PC0INF3_MMFLG_1                    1U     /* 1 : MMU support is included.                                              */


/*                                                  MSC PC0INF3 TZFFLG [4..4]                                                  */
                                    /* MSC_PC0INF3_TZFFLG                                                        */
#define  MSC_PC0INF3_TZFFLG_0                   0U     /* 0 : Trust Zone support is not included.                                   */
#define  MSC_PC0INF3_TZFFLG_1                   1U     /* 1 : Trust Zone support is included.                                       */


/*                                                 MSC PC0INF3 CMPHWFLG [5..5]                                                 */
                                    /* MSC_PC0INF3_CMPHWFLG                                                      */
#define  MSC_PC0INF3_CMPHWFLG_0                 0U     /* 0 : Core Memory Protection is not included.                               */
#define  MSC_PC0INF3_CMPHWFLG_1                 1U     /* 1 : Core Memory Protection is included.                                   */


/*                                                  MSC PC0INF3 BBFLG [6..6]                                                   */
                                     /* MSC_PC0INF3_BBFLG                                                         */
#define  MSC_PC0INF3_BBFLG_0                    0U     /* 0 : Bit Banding is not supported.                                         */
#define  MSC_PC0INF3_BBFLG_1                    1U     /* 1 : Bit Banding is supported.                                             */


/*                                                            OCMD0                                                            */
/*                                                 MSC OCMD0 OCMTYPE [13..15]                                                  */
                                    /* MSC_OCMD0_OCMTYPE                                                         */
#define  MSC_OCMD0_OCMTYPE_100                  4U     /* 100 : OCMEMn is a Program Flash.                                          */
#define  MSC_OCMD0_OCMTYPE_101                  5U     /* 101 : OCMEMn is a Data Flash.                                             */
#define  MSC_OCMD0_OCMTYPE_110                  6U     /* 110 : OCMEMn is an EEE.                                                   */


/*                                                  MSC OCMD0 RONLY [16..16]                                                   */
                                     /* MSC_OCMD0_RONLY                                                           */
#define  MSC_OCMD0_RONLY_0                      0U     /* 0 : Writes to the OCMDRn[11:0] are allowed                                */
#define  MSC_OCMD0_RONLY_1                      1U     /* 1 : Writes to the OCMDRn[11:0] are ignored                                */


/*                                                 MSC OCMD0 OCMDPWID [17..19]                                                 */
                                  /* MSC_OCMD0_OCMDPWID                                                        */
#define  MSC_OCMD0_OCMDPWID_010                 2U     /* 010 : OCMEMn 32-bits wide                                                 */
#define  MSC_OCMD0_OCMDPWID_011                 3U     /* 011 : OCMEMn 64-bits wide                                                 */
#define  MSC_OCMD0_OCMDPWID_100                 4U     /* 100 : OCMEMn 128-bits wide                                                */
#define  MSC_OCMD0_OCMDPWID_101                 5U     /* 101 : OCMEMn 256-bits wide                                                */


/*                                                 MSC OCMD0 OCMSIZE [24..27]                                                  */
                                  /* MSC_OCMD0_OCMSIZE                                                         */
#define  MSC_OCMD0_OCMSIZE_0000                 0U     /* 0000 : no OCMEMn                                                          */
#define  MSC_OCMD0_OCMSIZE_0001                 1U     /* 0001 : 1KB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_0010                 2U     /* 0010 : 2KB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_0011                 3U     /* 0011 : 4KB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_0100                 4U     /* 0100 : 8KB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_0101                 5U     /* 0101 : 16KB OCMEMn                                                        */
#define  MSC_OCMD0_OCMSIZE_0110                 6U     /* 0110 : 32KB OCMEMn                                                        */
#define  MSC_OCMD0_OCMSIZE_0111                 7U     /* 0111 : 64KB OCMEMn                                                        */
#define  MSC_OCMD0_OCMSIZE_1000                 8U     /* 1000 : 128KB OCMEMn                                                       */
#define  MSC_OCMD0_OCMSIZE_1001                 9U     /* 1001 : 256KB OCMEMn                                                       */
#define  MSC_OCMD0_OCMSIZE_1010                 10U    /* 1010 : 512KB OCMEMn                                                       */
#define  MSC_OCMD0_OCMSIZE_1011                 11U    /* 1011 : 1MB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_1100                 12U    /* 1100 : 2MB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_1101                 13U    /* 1101 : 4MB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_1110                 14U    /* 1110 : 8MB OCMEMn                                                         */
#define  MSC_OCMD0_OCMSIZE_1111                 15U    /* 1111 : 16MB OCMEMn                                                        */


/*                                                  MSC OCMD0 IFOCM [28..28]                                                   */
                                /* MSC_OCMD0_IFOCM                                                           */
#define  MSC_OCMD0_IFOCM_0                      0U     /* 0 : OCMEMn is a power-of-2 capacity.                                      */
#define  MSC_OCMD0_IFOCM_1                      1U     /* 1 : OCMEMn is not a power-of-2U with a capacity is 0.75 * OCMSZ.          */


/*                                                MSC OCMD0 OCMVLDFLG [31..31]                                                 */
                                   /* MSC_OCMD0_OCMVLDFLG                                                       */
#define  MSC_OCMD0_OCMVLDFLG_0                  0U     /* 0 : OCMEMn is not present.                                                */
#define  MSC_OCMD0_OCMVLDFLG_1                  1U     /* 1 : OCMEMn is present.                                                    */


/*                                                            OCMD1                                                            */
/*                                                 MSC OCMD1 OCMTYPE [13..15]                                                  */
                                    /* MSC_OCMD1_OCMTYPE                                                         */
#define  MSC_OCMD1_OCMTYPE_100                  4U     /* 100 : OCMEMn is a Program Flash.                                          */
#define  MSC_OCMD1_OCMTYPE_101                  5U     /* 101 : OCMEMn is a Data Flash.                                             */
#define  MSC_OCMD1_OCMTYPE_110                  6U     /* 110 : OCMEMn is an EEE.                                                   */


/*                                                  MSC OCMD1 RONLY [16..16]                                                   */
                                    /* MSC_OCMD1_RONLY                                                           */
#define  MSC_OCMD1_RONLY_0                      0U     /* 0 : Writes to the OCMDRn[11:0] are allowed                                */
#define  MSC_OCMD1_RONLY_1                      1U     /* 1 : Writes to the OCMDRn[11:0] are ignored                                */


/*                                                 MSC OCMD1 OCMDPWID [17..19]                                                 */
                                  /* MSC_OCMD1_OCMDPWID                                                        */
#define  MSC_OCMD1_OCMDPWID_010                 2U     /* 010 : OCMEMn 32-bits wide                                                 */
#define  MSC_OCMD1_OCMDPWID_011                 3U     /* 011 : OCMEMn 64-bits wide                                                 */
#define  MSC_OCMD1_OCMDPWID_100                 4U     /* 100 : OCMEMn 128-bits wide                                                */
#define  MSC_OCMD1_OCMDPWID_101                 5U     /* 101 : OCMEMn 256-bits wide                                                */


/*                                                 MSC OCMD1 OCMSIZE [24..27]                                                  */
                                   /* MSC_OCMD1_OCMSIZE                                                         */
#define  MSC_OCMD1_OCMSIZE_0000                 0U     /* 0000 : no OCMEMn                                                          */
#define  MSC_OCMD1_OCMSIZE_0001                 1U     /* 0001 : 1KB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_0010                 2U     /* 0010 : 2KB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_0011                 3U     /* 0011 : 4KB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_0100                 4U     /* 0100 : 8KB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_0101                 5U     /* 0101 : 16KB OCMEMn                                                        */
#define  MSC_OCMD1_OCMSIZE_0110                 6U     /* 0110 : 32KB OCMEMn                                                        */
#define  MSC_OCMD1_OCMSIZE_0111                 7U     /* 0111 : 64KB OCMEMn                                                        */
#define  MSC_OCMD1_OCMSIZE_1000                 8U     /* 1000 : 128KB OCMEMn                                                       */
#define  MSC_OCMD1_OCMSIZE_1001                 9U     /* 1001 : 256KB OCMEMn                                                       */
#define  MSC_OCMD1_OCMSIZE_1010                 10U    /* 1010 : 512KB OCMEMn                                                       */
#define  MSC_OCMD1_OCMSIZE_1011                 11U    /* 1011 : 1MB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_1100                 12U    /* 1100 : 2MB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_1101                 13U    /* 1101 : 4MB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_1110                 14U    /* 1110 : 8MB OCMEMn                                                         */
#define  MSC_OCMD1_OCMSIZE_1111                 15U    /* 1111 : 16MB OCMEMn                                                        */


/*                                                  MSC OCMD1 IFOCM [28..28]                                                   */
                                 /* MSC_OCMD1_IFOCM                                                           */
#define  MSC_OCMD1_IFOCM_0                      0U     /* 0 : OCMEMn is a power-of-2 capacity.                                      */
#define  MSC_OCMD1_IFOCM_1                      1U     /* 1 : OCMEMn is not a power-of-2U with a capacity is 0.75 * OCMSZ.          */


/*                                                MSC OCMD1 OCMVLDFLG [31..31]                                                 */
                                  /* MSC_OCMD1_OCMVLDFLG                                                       */
#define  MSC_OCMD1_OCMVLDFLG_0                  0U     /* 0 : OCMEMn is not present.                                                */
#define  MSC_OCMD1_OCMVLDFLG_1                  1U     /* 1 : OCMEMn is present.                                                    */


/*                                                            OCMD2                                                            */
/*                                                 MSC OCMD2 OCMTYPE [13..15]                                                  */
                                     /* MSC_OCMD2_OCMTYPE                                                         */
#define  MSC_OCMD2_OCMTYPE_100                  4U     /* 100 : OCMEMn is a Program Flash.                                          */
#define  MSC_OCMD2_OCMTYPE_101                  5U     /* 101 : OCMEMn is a Data Flash.                                             */
#define  MSC_OCMD2_OCMTYPE_110                  6U     /* 110 : OCMEMn is an EEE.                                                   */


/*                                                  MSC OCMD2 RONLY [16..16]                                                   */
                                   /* MSC_OCMD2_RONLY                                                           */
#define  MSC_OCMD2_RONLY_0                      0U     /* 0 : Writes to the OCMDRn[11:0] are allowed                                */
#define  MSC_OCMD2_RONLY_1                      1U     /* 1 : Writes to the OCMDRn[11:0] are ignored                                */


/*                                                 MSC OCMD2 OCMDPWID [17..19]                                                 */
                                   /* MSC_OCMD2_OCMDPWID                                                        */
#define  MSC_OCMD2_OCMDPWID_010                 2U     /* 010 : OCMEMn 32-bits wide                                                 */
#define  MSC_OCMD2_OCMDPWID_011                 3U     /* 011 : OCMEMn 64-bits wide                                                 */
#define  MSC_OCMD2_OCMDPWID_100                 4U     /* 100 : OCMEMn 128-bits wide                                                */
#define  MSC_OCMD2_OCMDPWID_101                 5U     /* 101 : OCMEMn 256-bits wide                                                */


/*                                                 MSC OCMD2 OCMSIZE [24..27]                                                  */
                                    /* MSC_OCMD2_OCMSIZE                                                         */
#define  MSC_OCMD2_OCMSIZE_0000                 0U     /* 0000 : no OCMEMn                                                          */
#define  MSC_OCMD2_OCMSIZE_0001                 1U     /* 0001 : 1KB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_0010                 2U     /* 0010 : 2KB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_0011                 3U     /* 0011 : 4KB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_0100                 4U     /* 0100 : 8KB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_0101                 5U     /* 0101 : 16KB OCMEMn                                                        */
#define  MSC_OCMD2_OCMSIZE_0110                 6U     /* 0110 : 32KB OCMEMn                                                        */
#define  MSC_OCMD2_OCMSIZE_0111                 7U     /* 0111 : 64KB OCMEMn                                                        */
#define  MSC_OCMD2_OCMSIZE_1000                 8U     /* 1000 : 128KB OCMEMn                                                       */
#define  MSC_OCMD2_OCMSIZE_1001                 9U     /* 1001 : 256KB OCMEMn                                                       */
#define  MSC_OCMD2_OCMSIZE_1010                 10U    /* 1010 : 512KB OCMEMn                                                       */
#define  MSC_OCMD2_OCMSIZE_1011                 11U    /* 1011 : 1MB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_1100                 12U    /* 1100 : 2MB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_1101                 13U    /* 1101 : 4MB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_1110                 14U    /* 1110 : 8MB OCMEMn                                                         */
#define  MSC_OCMD2_OCMSIZE_1111                 15U    /* 1111 : 16MB OCMEMn                                                        */


/*                                                  MSC OCMD2 IFOCM [28..28]                                                   */
                                  /* MSC_OCMD2_IFOCM                                                           */
#define  MSC_OCMD2_IFOCM_0                      0U     /* 0 : OCMEMn is a power-of-2 capacity.                                      */
#define  MSC_OCMD2_IFOCM_1                      1U     /* 1 : OCMEMn is not a power-of-2U with a capacity is 0.75 * OCMSZ.          */


/*                                                MSC OCMD2 OCMVLDFLG [31..31]                                                 */
                                  /* MSC_OCMD2_OCMVLDFLG                                                       */
 #define MSC_OCMD2_OCMVLDFLG_0                  0U     /* 0 : OCMEMn is not present.                                                */
 #define MSC_OCMD2_OCMVLDFLG_1                  1U     /* 1 : OCMEMn is present.                                                    */




/*                                                                                                                             */
/*                                                             DMA                                                             */
/*                                                                                                                             */

/*                                                            CTRL                                                             */
/*                                                  DMA CTRL HALTEFLG [4..4]                                                   */
                                /* DMA_CTRL_HALTEFLG                                                         */
#define  DMA_CTRL_HALTEFLG_0                    0U     /* 0 : Normal operation                                                      */
#define  DMA_CTRL_HALTEFLG_1                    1U     /* 1 : Any error causes the HALT bit to set. SubsequentlyU all
                                                     service requests are ignored until the HALT bit is cleared.               */


/*                                                    DMA CTRL HALT [5..5]                                                     */
                                 /* DMA_CTRL_HALT                                                             */
#define  DMA_CTRL_HALT_0                        0U     /* 0 : Normal operation                                                      */
#define  DMA_CTRL_HALT_1                        1U     /* 1 : Stall the start of any new channels. Executing channels
                                                     are allowed to complete. Channel execution resumes when
                                                     this bit is cleared.                                                      */


/*                                                    DMA CTRL CLMEN [6..6]                                                    */
                               /* DMA_CTRL_CLMEN                                                            */
#define  DMA_CTRL_CLMEN_0                       0U     /* 0 : A minor loop channel link made to itself goes through channel
                                                      arbitration before being activated again.                                 */
#define  DMA_CTRL_CLMEN_1                       1U     /* 1 : A minor loop channel link made to itself does not go through
                                                       channel arbitration before being activated again. Upon
                                                     minor loop completionU the channel activates again if that
                                                     channel has a minor loop channel link enabled and the link
                                                     channel is itself. This effectively applies the minor loop
                                                     offsets and restarts the next minor loop.                                 */


/*                                                   DMA CTRL MINLMEN [7..7]                                                   */
                                    /* DMA_CTRL_MINLMEN                                                          */
#define  DMA_CTRL_MINLMEN_0                     0U     /* 0 : Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.             */
#define  DMA_CTRL_MINLMEN_1                     1U     /* 1 : Enabled. TCDn.word2 is redefined to include individual enable
                                                     fieldsU an offset fieldU and the NBYTES field. The individual
                                                     enable fields allow the minor loop offset to be applied
                                                     to the source addressU the destination addressU or both.
                                                     The NBYTES field is reduced when either offset is enabled.                */


/*                                                 DMA CTRL TXCNLERR [16..16]                                                  */
                                   /* DMA_CTRL_TXCNLERR                                                         */
#define  DMA_CTRL_TXCNLERR_0                    0U     /* 0 : Normal operation                                                      */
#define  DMA_CTRL_TXCNLERR_1                    1U     /* 1 : Cancel the remaining data transfer in the same fashion as
                                                     the CX bit. Stop the executing channel and force the minor
                                                     loop to finish. The cancel takes effect after the last
                                                     write of the current read/write sequence. The ECX bit clears
                                                     itself after the cancel is honored. In addition to cancelling
                                                     the transferU ECX treats the cancel as an error conditionU
                                                     thus updating the Error Status register (DMAx_ES) and generating
                                                     an optional error interrupt.                                              */


/*                                                   DMA CTRL TXCNL [17..17]                                                   */
                                     /* DMA_CTRL_TXCNL                                                            */
#define  DMA_CTRL_TXCNL_0                       0U     /* 0 : Normal operation                                                      */
#define  DMA_CTRL_TXCNL_1                       1U     /* 1 : Cancel the remaining data transfer. Stop the executing channel
                                                     and force the minor loop to finish. The cancel takes effect
                                                     after the last write of the current read/write sequence.
                                                     The CX bit clears itself after the cancel has been honored.
                                                     This cancel retires the channel normally as if the minor
                                                     loop was completed.                                                       */


/*                                                  DMA CTRL ACTFLG [31..31]                                                   */
                                     /* DMA_CTRL_ACTFLG                                                           */
#define  DMA_CTRL_ACTFLG_0                      0U     /* 0 : eDMA is idle.                                                         */
#define  DMA_CTRL_ACTFLG_1                      1U     /* 1 : eDMA is executing a channel.                                          */


/*                                                            ESTS                                                             */
/*                                                   DMA ESTS DBEFLG [0..0]                                                    */
                                   /* DMA_ESTS_DBEFLG                                                           */
#define  DMA_ESTS_DBEFLG_0                      0U     /* 0 : No destination bus error                                              */
#define  DMA_ESTS_DBEFLG_1                      1U     /* 1 : The last recorded error was a bus error on a destination
                                                     write                                                                     */


/*                                                   DMA ESTS SBEFLG [1..1]                                                    */
                                    /* DMA_ESTS_SBEFLG                                                           */
#define  DMA_ESTS_SBEFLG_0                      0U     /* 0 : No source bus error                                                   */
#define  DMA_ESTS_SBEFLG_1                      1U     /* 1 : The last recorded error was a bus error on a source read              */


/*                                                  DMA ESTS SGCFGEFLG [2..2]                                                  */
                                   /* DMA_ESTS_SGCFGEFLG                                                        */
#define  DMA_ESTS_SGCFGEFLG_0                   0U     /* 0 : No scatter/gather configuration error                                 */
#define  DMA_ESTS_SGCFGEFLG_1                   1U     /* 1 : The last recorded error was a configuration error detected
                                                     in the TCDn_DLASTSGA field. This field is checked at the
                                                     beginning of a scatter/gather operation after major loop
                                                     completion if TCDn_CSTS[SGFEN] is enabled. TCDn_DLASTSGA
                                                     is not on a 32 byte boundary.                                             */


/*                                                  DMA ESTS MCCFGEFLG [3..3]                                                  */
                                     /* DMA_ESTS_NCCFGEFLG                                                        */
#define  DMA_ESTS_NCCFGEFLG_0                   0U     /* 0 : No NBYTES/CITER configuration error                                   */


/*                                                 DMA ESTS DOFCFGEFLG [4..4]                                                  */
                                    /* DMA_ESTS_DOFCFGEFLG                                                       */
#define  DMA_ESTS_DOFCFGEFLG_0                  0U     /* 0 : No destination offset configuration error                             */
#define  DMA_ESTS_DOFCFGEFLG_1                  1U     /* 1 : The last recorded error was a configuration error detected
                                                     in the TCDn_DOFF field. TCDn_DOFF is inconsistent with
                                                     TCDn_ATTR[DSIZE].                                                         */


/*                                                DMA ESTS DADDRCFGEFLG [5..5]                                                 */
                               /* DMA_ESTS_DADDRCFGEFLG                                                     */
#define  DMA_ESTS_DADDRCFGEFLG_0                0U     /* 0 : No destination address configuration error                            */
#define  DMA_ESTS_DADDRCFGEFLG_1                1U     /* 1 : The last recorded error was a configuration error detected
                                                     in the TCDn_DADDR field. TCDn_DADDR is inconsistent with
                                                     TCDn_ATTR[DSIZE].                                                         */


/*                                                 DMA ESTS SOFCFGEFLG [6..6]                                                  */
                                   /* DMA_ESTS_SOFCFGEFLG                                                       */
#define  DMA_ESTS_SOFCFGEFLG_0                  0U     /* 0 : No source offset configuration error                                  */
#define  DMA_ESTS_SOFCFGEFLG_1                  1U     /* 1 : The last recorded error was a configuration error detected
                                                     in the TCDn_SOFF field. TCDn_SOFF is inconsistent with
                                                     TCDn_ATTR[SSIZE].                                                         */


/*                                                DMA ESTS SADDRCFGEFLG [7..7]                                                 */
                              /* DMA_ESTS_SADDRCFGEFLG                                                     */
#define  DMA_ESTS_SADDRCFGEFLG_0                0U     /* 0 : No source address configuration error.                                */
#define  DMA_ESTS_SADDRCFGEFLG_1                1U     /* 1 : The last recorded error was a configuration error detected
                                                     in the TCDn_SADDR field. TCDn_SADDR is inconsistent with
                                                     TCDn_ATTR[SSIZE].                                                         */


/*                                                 DMA ESTS CPCFGEFLG [14..14]                                                 */
                                   /* DMA_ESTS_CPCFGEFLG                                                        */
#define  DMA_ESTS_CPCFGEFLG_0                   0U     /* 0 : No channel priority error                                             */


/*                                                   DMA ESTS TCFLG [16..16]                                                   */
                                  /* DMA_ESTS_TCFLG                                                            */
#define  DMA_ESTS_TCFLG_0                       0U     /* 0 : No canceled transfers                                                 */
#define  DMA_ESTS_TCFLG_1                       1U     /* 1 : The last recorded entry was a canceled transfer by the error
                                                     cancel transfer input                                                     */


/*                                                  DMA ESTS EEFLG [31..31]                                                   */
                                     /* DMA_ESTS_EEFLG                                                           */
#define  DMA_ESTS_EEFLG_0                      0U     /* 0 : No ERR bits are set.                                                  */
#define  DMA_ESTS_EEFLG_1                      1U     /* 1 : At least one ERR bit is set indicating a valid error exists
                                                     that has not been cleared.                                                */


/*                                                            REQEN                                                            */
/*                                                   DMA REQEN REQEN0 [0..0]                                                   */
                                     /* DMA_REQEN_REQEN0                                                          */
#define  DMA_REQEN_REQEN0_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                      disabled                                                                  */
#define  DMA_REQEN_REQEN0_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                      enabled                                                                   */


/*                                                   DMA REQEN REQEN1 [1..1]                                                   */
                                    /* DMA_REQEN_REQEN1                                                          */
 #define DMA_REQEN_REQEN1_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                      disabled                                                                  */
 #define DMA_REQEN_REQEN1_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                       enabled                                                                   */


/*                                                   DMA REQEN REQEN2 [2..2]                                                   */
                                  /* DMA_REQEN_REQEN2                                                          */
#define  DMA_REQEN_REQEN2_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                             disabled                                                                  */
#define  DMA_REQEN_REQEN2_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                        enabled                                                                   */


/*                                                   DMA REQEN REQEN3 [3..3]                                                   */
                                     /* DMA_REQEN_REQEN3                                                          */
#define  DMA_REQEN_REQEN3_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                      disabled                                                                  */
#define  DMA_REQEN_REQEN3_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                        enabled                                                                   */


/*                                                   DMA REQEN REQEN4 [4..4]                                                   */
                                     /* DMA_REQEN_REQEN4                                                          */
#define  DMA_REQEN_REQEN4_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                       disabled                                                                  */
#define  DMA_REQEN_REQEN4_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                      enabled                                                                   */


/*                                                   DMA REQEN REQEN5 [5..5]                                                   */
                                   /* DMA_REQEN_REQEN5                                                          */
#define  DMA_REQEN_REQEN5_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                         disabled                                                                  */
#define  DMA_REQEN_REQEN5_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                       enabled                                                                   */


/*                                                   DMA REQEN REQEN6 [6..6]                                                   */
                                   /* DMA_REQEN_REQEN6                                                          */
#define  DMA_REQEN_REQEN6_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                        disabled                                                                  */
#define  DMA_REQEN_REQEN6_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                       enabled                                                                   */


/*                                                   DMA REQEN REQEN7 [7..7]                                                   */
                                   /* DMA_REQEN_REQEN7                                                          */
#define  DMA_REQEN_REQEN7_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                        disabled                                                                  */
#define  DMA_REQEN_REQEN7_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                        enabled                                                                   */


/*                                                   DMA REQEN REQEN8 [8..8]                                                   */
                                    /* DMA_REQEN_REQEN8                                                          */
#define  DMA_REQEN_REQEN8_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                        disabled                                                                  */
#define  DMA_REQEN_REQEN8_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                       enabled                                                                   */


/*                                                   DMA REQEN REQEN9 [9..9]                                                   */
                                 /* DMA_REQEN_REQEN9                                                          */
 #define DMA_REQEN_REQEN9_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                    disabled                                                                  */
 #define DMA_REQEN_REQEN9_1                     1U     /* 1 : The DMA request signal for the corresponding channel is
                                                     enabled                                                                   */


/*                                                 DMA REQEN REQEN10 [10..10]                                                  */
                                    /* DMA_REQEN_REQEN10                                                         */
#define  DMA_REQEN_REQEN10_0                    0U     /* 0 : The DMA request signal for the corresponding channel is
                                                        disabled                                                                  */
#define  DMA_REQEN_REQEN10_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                     enabled                                                                   */


/*                                                 DMA REQEN REQEN11 [11..11]                                                  */
                                   /* DMA_REQEN_REQEN11                                                         */
#define  DMA_REQEN_REQEN11_0                    0U     /* 0 : The DMA request signal for the corresponding channel is
                                                        disabled                                                                  */
#define  DMA_REQEN_REQEN11_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                    enabled                                                                   */


/*                                                 DMA REQEN REQEN12 [12..12]                                                  */
                                     /* DMA_REQEN_REQEN12                                                         */
#define  DMA_REQEN_REQEN12_0                    0U     /* 0 : The DMA request signal for the corresponding channel is
                                                      disabled                                                                  */
#define  DMA_REQEN_REQEN12_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                     enabled                                                                   */


/*                                                 DMA REQEN REQEN13 [13..13]                                                  */
                                    /* DMA_REQEN_REQEN13                                                         */
 #define DMA_REQEN_REQEN13_0                    0U     /* 0 : The DMA request signal for the corresponding channel is
                                                    disabled                                                                  */
 #define DMA_REQEN_REQEN13_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                      enabled                                                                   */


/*                                                 DMA REQEN REQEN14 [14..14]                                                  */
                                    /* DMA_REQEN_REQEN14                                                         */
#define DMA_REQEN_REQEN14_0                     0U     /* 0 : The DMA request signal for the corresponding channel is
                                                      disabled                                                                  */
#define  DMA_REQEN_REQEN14_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                     enabled                                                                   */


/*                                                 DMA REQEN REQEN15 [15..15]                                                  */
                                   /* DMA_REQEN_REQEN15                                                         */
 #define DMA_REQEN_REQEN15_0                    0U     /* 0 : The DMA request signal for the corresponding channel is
                                                       disabled                                                                  */
 #define DMA_REQEN_REQEN15_1                    1U     /* 1 : The DMA request signal for the corresponding channel is
                                                     enabled                                                                   */


/*                                                            EIEN                                                             */
/*                                                    DMA EIEN EIEN0 [0..0]                                                    */
                                   /* DMA_EIEN_EIEN0                                                            */
 #define DMA_EIEN_EIEN0_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
 #define DMA_EIEN_EIEN0_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN1 [1..1]                                                    */
                                   /* DMA_EIEN_EIEN1                                                            */
#define  DMA_EIEN_EIEN1_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                        an error interrupt                                                        */
#define  DMA_EIEN_EIEN1_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN2 [2..2]                                                    */
                                    /* DMA_EIEN_EIEN2                                                            */
 #define DMA_EIEN_EIEN2_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
 #define DMA_EIEN_EIEN2_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN3 [3..3]                                                    */
                                     /* DMA_EIEN_EIEN3                                                            */
#define  DMA_EIEN_EIEN3_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                        an error interrupt                                                        */
#define  DMA_EIEN_EIEN3_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN4 [4..4]                                                    */
                                     /* DMA_EIEN_EIEN4                                                            */
#define  DMA_EIEN_EIEN4_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN4_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                       generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN5 [5..5]                                                    */
                                     /* DMA_EIEN_EIEN5                                                            */
#define  DMA_EIEN_EIEN5_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                        an error interrupt                                                        */
#define  DMA_EIEN_EIEN5_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                        generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN6 [6..6]                                                    */
                                     /* DMA_EIEN_EIEN6                                                            */
#define  DMA_EIEN_EIEN6_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN6_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
#define                                                     generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN7 [7..7]                                                    */
                                 /* DMA_EIEN_EIEN7                                                            */
#define  DMA_EIEN_EIEN7_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                        an error interrupt                                                        */
#define  DMA_EIEN_EIEN7_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN8 [8..8]                                                    */
                                     /* DMA_EIEN_EIEN8                                                            */
 #define DMA_EIEN_EIEN8_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
 #define DMA_EIEN_EIEN8_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                    generates an error interrupt request                                      */


/*                                                    DMA EIEN EIEN9 [9..9]                                                    */
                                     /* DMA_EIEN_EIEN9                                                            */
#define  DMA_EIEN_EIEN9_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN9_1                       1U     /* 1 : The assertion of the error signal for corresponding channel
                                                        generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN10 [10..10]                                                   */
                                    /* DMA_EIEN_EIEN10                                                           */
#define DMA_EIEN_EIEN10_0                       0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN10_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                       generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN11 [11..11]                                                   */
                                 /* DMA_EIEN_EIEN11                                                           */
#define  DMA_EIEN_EIEN11_0                      0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN11_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                      generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN12 [12..12]                                                   */
                                     /* DMA_EIEN_EIEN12                                                           */
 #define DMA_EIEN_EIEN12_0                      0U     /* 0 : The error signal for corresponding channel does not generate
                                                    an error interrupt                                                        */
 #define DMA_EIEN_EIEN12_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                       generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN13 [13..13]                                                   */
                                   /* DMA_EIEN_EIEN13                                                           */
#define  DMA_EIEN_EIEN13_0                      0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN13_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                 generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN14 [14..14]                                                   */
                                  /* DMA_EIEN_EIEN14                                                           */
#define  DMA_EIEN_EIEN14_0                      0U     /* 0 : The error signal for corresponding channel does not generate
                                                       an error interrupt                                                        */
#define  DMA_EIEN_EIEN14_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                     generates an error interrupt request                                      */


/*                                                  DMA EIEN EIEN15 [15..15]                                                   */
                                     /* DMA_EIEN_EIEN15                                                           */
#define  DMA_EIEN_EIEN15_0                      0U     /* 0 : The error signal for corresponding channel does not generate
                                                        an error interrupt                                                        */
#define  DMA_EIEN_EIEN15_1                      1U     /* 1 : The assertion of the error signal for corresponding channel
                                                    generates an error interrupt request                                      */


/*                                                           EIENCLR                                                           */
/*                                                   DMA EIENCLR NOOP [7..7]                                                   */
                                    /* DMA_EIENCLR_NOOP                                                          */
#define  DMA_EIENCLR_NOOP_0                     0U     /* 0 : Normal operation                                                      */
#define  DMA_EIENCLR_NOOP_1                     1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                           EIENSET                                                           */
/*                                                   DMA EIENSET NOOP [7..7]                                                   */
                                  /* DMA_EIENSET_NOOP                                                          */
#define  DMA_EIENSET_NOOP_0                     0U     /* 0 : Normal operation                                                      */
#define  DMA_EIENSET_NOOP_1                     1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                          REQENCLR                                                           */
/*                                                  DMA REQENCLR NOOP [7..7]                                                   */
                                 /* DMA_REQENCLR_NOOP                                                         */
#define  DMA_REQENCLR_NOOP_0                    0U     /* 0 : Normal operation                                                      */
#define  DMA_REQENCLR_NOOP_1                    1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                          REQENSET                                                           */
/*                                                  DMA REQENSET NOOP [7..7]                                                   */
                                 /* DMA_REQENSET_NOOP                                                         */
#define  DMA_REQENSET_NOOP_0                    0U     /* 0 : Normal operation                                                      */
#define  DMA_REQENSET_NOOP_1                    1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                          DNESTSCLR                                                          */
/*                                                DMA DNESTSCLR ADNECLR [6..6]                                                 */
                                      /* DMA_DNESTSCLR_ADNECLR                                                     */
#define  DMA_DNESTSCLR_ADNECLR_0                0U     /* 0 : Clears only the TCDn_CSTS[DONE] bit specified in the CDNE
                                                       field                                                                     */
#define  DMA_DNESTSCLR_ADNECLR_1                1U     /* 1 : Clears all bits in TCDn_CSTS[DONE]                                    */


/*                                                  DMA DNESTSCLR NOOP [7..7]                                                  */
                                  /* DMA_DNESTSCLR_NOOP                                                        */
#define  DMA_DNESTSCLR_NOOP_0                   0U     /* 0 : Normal operation                                                      */
#define  DMA_DNESTSCLR_NOOP_1                   1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                           STATSET                                                            */
/*                                                 DMA STATSET ASTATSET [6..6]                                                 */
                                      /* DMA_SRTSET_ASTATSET                                                      */
 #define DMA_STATSET_ASTATSET_0                 0U     /* 0 : Set only the TCDn_CSTS[START] bit specified in the SSRT
                                                        field                                                                     */
 #define DMA_STATSET_ASTATSET_1                 1U     /* 1 : Set all bits in TCDn_CSTS[START]                                      */


/*                                                   DMA STATSET NOOP [7..7]                                                    */
                                     /* DMA_SRTSET_NOOP                                                           */
#define  DMA_STATSET_NOOP_0                      0U     /* 0 : Normal operation                                                      */
#define  DMA_STATSET_NOOP_1                      1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                            ESTSCLR                                                             */
/*                                                    DMA ESTSCLR NOOP [7..7]                                                     */
                                    /* DMA_ESTSCLR_NOOP                                                             */
#define  DMA_ESTSCLR_NOOP_0                        0U     /* 0 : Normal operation                                                      */
#define  DMA_ESTSCLR_NOOP_1                        1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                          INTREQCLR                                                          */
/*                                                  DMA INTREQCLR NOOP [7..7]                                                  */
                                /* DMA_INTREQCLR_NOOP                                                        */
#define  DMA_INTREQCLR_NOOP_0                   0U     /* 0 : Normal operation                                                      */
#define  DMA_INTREQCLR_NOOP_1                   1U     /* 1 : No operationU ignore the other bits in this register                  */


/*                                                           INTREQ                                                            */
/*                                                DMA INTREQ INTREQSTS0 [0..0]                                                 */
                                   /* DMA_INTREQ_INTREQSTS0                                                     */
#define  DMA_INTREQ_INTREQSTS0_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS0_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS1 [1..1]                                                 */
                                    /* DMA_INTREQ_INTREQSTS1                                                     */
#define  DMA_INTREQ_INTREQSTS1_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS1_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS2 [2..2]                                                 */
                                    /* DMA_INTREQ_INTREQSTS2                                                     */
#define  DMA_INTREQ_INTREQSTS2_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS2_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS3 [3..3]                                                 */
                                    /* DMA_INTREQ_INTREQSTS3                                                     */
#define  DMA_INTREQ_INTREQSTS3_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS3_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS4 [4..4]                                                 */
                                    /* DMA_INTREQ_INTREQSTS4                                                     */
#define  DMA_INTREQ_INTREQSTS4_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS4_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS5 [5..5]                                                 */
                                     /* DMA_INTREQ_INTREQSTS5                                                     */
#define  DMA_INTREQ_INTREQSTS5_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS5_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS6 [6..6]                                                 */
                                    /* DMA_INTREQ_INTREQSTS6                                                     */
#define  DMA_INTREQ_INTREQSTS6_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS6_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS7 [7..7]                                                 */
                                     /* DMA_INTREQ_INTREQSTS7                                                     */
#define  DMA_INTREQ_INTREQSTS7_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS7_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS8 [8..8]                                                 */
                                    /* DMA_INTREQ_INTREQSTS8                                                     */
#define  DMA_INTREQ_INTREQSTS8_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS8_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                DMA INTREQ INTREQSTS9 [9..9]                                                 */
                                    /* DMA_INTREQ_INTREQSTS9                                                     */
#define  DMA_INTREQ_INTREQSTS9_0                0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS9_1                1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS10 [10..10]                                               */
                                    /* DMA_INTREQ_INTREQSTS10                                                    */
#define  DMA_INTREQ_INTREQSTS10_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS10_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS11 [11..11]                                               */
                                    /* DMA_INTREQ_INTREQSTS11                                                    */
#define  DMA_INTREQ_INTREQSTS11_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS11_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS12 [12..12]                                               */
                                    /* DMA_INTREQ_INTREQSTS12                                                    */
#define  DMA_INTREQ_INTREQSTS12_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS12_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS13 [13..13]                                               */
                                    /* DMA_INTREQ_INTREQSTS13                                                    */
#define  DMA_INTREQ_INTREQSTS13_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS13_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS14 [14..14]                                               */
                                    /* DMA_INTREQ_INTREQSTS14                                                    */
#define  DMA_INTREQ_INTREQSTS14_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS14_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                               DMA INTREQ INTREQSTS15 [15..15]                                               */
                                     /* DMA_INTREQ_INTREQSTS15                                                    */
#define  DMA_INTREQ_INTREQSTS15_0               0U     /* 0 : The interrupt request for corresponding channel is cleared            */
#define  DMA_INTREQ_INTREQSTS15_1               1U     /* 1 : The interrupt request for corresponding channel is active             */


/*                                                            CHESTS                                                             */
/*                                                    DMA CHESTS EFLG0 [0..0]                                                    */
                                     /* DMA_CHESTS_EFLG0                                                            */
#define  DMA_CHESTS_EFLG0_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG0_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG1 [1..1]                                                    */
                                     /* DMA_CHESTS_EFLG1                                                            */
#define  DMA_CHESTS_EFLG1_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG1_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG2 [2..2]                                                    */
                                    /* DMA_CHESTS_EFLG2                                                            */
#define  DMA_CHESTS_EFLG2_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG2_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG3 [3..3]                                                    */
                                    /* DMA_CHESTS_EFLG3                                                            */
#define  DMA_CHESTS_EFLG3_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG3_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG4 [4..4]                                                    */
                                     /* DMA_CHESTS_EFLG4                                                            */
#define  DMA_CHESTS_EFLG4_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG4_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG5 [5..5]                                                    */
                                     /* DMA_CHESTS_EFLG5                                                            */
#define  DMA_CHESTS_EFLG5_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG5_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG6 [6..6]                                                    */
                                        /* DMA_CHESTS_EFLG6                                                            */
#define  DMA_CHESTS_EFLG6_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG6_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG7 [7..7]                                                    */
                                         /* DMA_CHESTS_EFLG7                                                            */
#define  DMA_CHESTS_EFLG7_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG7_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG8 [8..8]                                                    */
                                        /* DMA_CHESTS_EFLG8                                                            */
#define  DMA_CHESTS_EFLG8_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG8_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                    DMA CHESTS EFLG9 [9..9]                                                    */
                                        /* DMA_CHESTS_EFLG9                                                            */
#define  DMA_CHESTS_EFLG9_0                       0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG9_1                       1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG10 [10..10]                                                   */
                                        /* DMA_CHESTS_EFLG10                                                           */
#define  DMA_CHESTS_EFLG10_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG10_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG11 [11..11]                                                   */
                                        /* DMA_CHESTS_EFLG11                                                           */
#define  DMA_CHESTS_EFLG11_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG11_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG12 [12..12]                                                   */
                                        /* DMA_CHESTS_EFLG12                                                           */
#define  DMA_CHESTS_EFLG12_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG12_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG13 [13..13]                                                   */
                                        /* DMA_CHESTS_EFLG13                                                           */
#define  DMA_CHESTS_EFLG13_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG13_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG14 [14..14]                                                   */
                                        /* DMA_CHESTS_EFLG14                                                           */
#define  DMA_CHESTS_EFLG14_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG14_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                  DMA CHESTS EFLG15 [15..15]                                                   */
                                        /* DMA_CHESTS_EFLG15                                                           */
#define  DMA_CHESTS_EFLG15_0                      0U     /* 0 : An error in this channel has not occurred                             */
#define  DMA_CHESTS_EFLG15_1                      1U     /* 1 : An error in this channel has occurred                                 */


/*                                                           HWREQSTS                                                           */
/*                                                 DMA HWREQSTS HREQSTS0 [0..0]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS0                                                      */
#define  DMA_HWREQSTS_HREQSTS0_0                 0U     /* 0 : A hardware service request for channel 0 is not present               */
#define  DMA_HWREQSTS_HREQSTS0_1                 1U     /* 1 : A hardware service request for channel 0 is present                   */


/*                                                 DMA HWREQSTS HREQSTS1 [1..1]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS1                                                      */
#define  DMA_HWREQSTS_HREQSTS1_0                 0U     /* 0 : A hardware service request for channel 1 is not present               */
#define  DMA_HWREQSTS_HREQSTS1_1                 1U     /* 1 : A hardware service request for channel 1 is present                   */


/*                                                 DMA HWREQSTS HREQSTS2 [2..2]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS2                                                      */
#define  DMA_HWREQSTS_HREQSTS2_0                 0U     /* 0 : A hardware service request for channel 2 is not present               */
#define  DMA_HWREQSTS_HREQSTS2_1                 1U     /* 1 : A hardware service request for channel 2 is present                   */


/*                                                 DMA HWREQSTS HREQSTS3 [3..3]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS3                                                      */
#define  DMA_HWREQSTS_HREQSTS3_0                 0U     /* 0 : A hardware service request for channel 3 is not present               */
#define  DMA_HWREQSTS_HREQSTS3_1                 1U     /* 1 : A hardware service request for channel 3 is present                   */


/*                                                 DMA HWREQSTS HREQSTS4 [4..4]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS4                                                      */
#define  DMA_HWREQSTS_HREQSTS4_0                 0U     /* 0 : A hardware service request for channel 4 is not present               */
#define  DMA_HWREQSTS_HREQSTS4_1                 1U     /* 1 : A hardware service request for channel 4 is present                   */


/*                                                 DMA HWREQSTS HREQSTS5 [5..5]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS5                                                      */
#define  DMA_HWREQSTS_HREQSTS5_0                 0U     /* 0 : A hardware service request for channel 5 is not present               */
#define  DMA_HWREQSTS_HREQSTS5_1                 1U     /* 1 : A hardware service request for channel 5 is present                   */


/*                                                 DMA HWREQSTS HREQSTS6 [6..6]                                                 */
                                        /* DMA_HWREQSTS_HREQSTS6                                                      */
#define  DMA_HWREQSTS_HREQSTS6_0                 0U     /* 0 : A hardware service request for channel 6 is not present               */
#define  DMA_HWREQSTS_HREQSTS6_1                 1U     /* 1 : A hardware service request for channel 6 is present                   */


/*                                                 DMA HWREQSTS HREQSTS7 [7..7]                                                 */
                                    /* DMA_HWREQSTS_HREQSTS7                                                      */
#define  DMA_HWREQSTS_HREQSTS7_0                 0U     /* 0 : A hardware service request for channel 7 is not present               */
#define  DMA_HWREQSTS_HREQSTS7_1                 1U     /* 1 : A hardware service request for channel 7 is present                   */


/*                                                 DMA HWREQSTS HREQSTS8 [8..8]                                                 */
                                    /* DMA_HWREQSTS_HREQSTS8                                                      */
#define  DMA_HWREQSTS_HREQSTS8_0                 0U     /* 0 : A hardware service request for channel 8 is not present               */
#define  DMA_HWREQSTS_HREQSTS8_1                 1U     /* 1 : A hardware service request for channel 8 is present                   */


/*                                                 DMA HWREQSTS HREQSTS9 [9..9]                                                 */
                                    /* DMA_HWREQSTS_HREQSTS9                                                      */
#define  DMA_HWREQSTS_HREQSTS9_0                 0U     /* 0 : A hardware service request for channel 9 is not present               */
#define  DMA_HWREQSTS_HREQSTS9_1                 1U     /* 1 : A hardware service request for channel 9 is present                   */


/*                                               DMA HWREQSTS HREQSTS10 [10..10]                                                */
                                   /* DMA_HWREQSTS_HREQSTS10                                                     */
#define  DMA_HWREQSTS_HREQSTS10_0                0U     /* 0 : A hardware service request for channel 10 is not present              */
#define  DMA_HWREQSTS_HREQSTS10_1                1U     /* 1 : A hardware service request for channel 10 is present                  */


/*                                               DMA HWREQSTS HREQSTS11 [11..11]                                                */
                                     /* DMA_HWREQSTS_HREQSTS11                                                     */
#define  DMA_HWREQSTS_HREQSTS11_0                0U     /* 0 : A hardware service request for channel 11 is not present              */
#define  DMA_HWREQSTS_HREQSTS11_1                1U     /* 1 : A hardware service request for channel 11 is present                  */


/*                                               DMA HWREQSTS HREQSTS12 [12..12]                                                */
                                 /* DMA_HWREQSTS_HREQSTS12                                                     */
#define  DMA_HWREQSTS_HREQSTS12_0                0U     /* 0 : A hardware service request for channel 12 is not present              */
#define  DMA_HWREQSTS_HREQSTS12_1                1U     /* 1 : A hardware service request for channel 12 is present                  */


/*                                               DMA HWREQSTS HREQSTS13 [13..13]                                                */
                                     /* DMA_HWREQSTS_HREQSTS13                                                     */
#define  DMA_HWREQSTS_HREQSTS13_0                0U     /* 0 : A hardware service request for channel 13 is not present              */
#define  DMA_HWREQSTS_HREQSTS13_1                1U     /* 1 : A hardware service request for channel 13 is present                  */


/*                                               DMA HWREQSTS HREQSTS14 [14..14]                                                */
                                    /* DMA_HWREQSTS_HREQSTS14                                                     */
#define  DMA_HWREQSTS_HREQSTS14_0                0U     /* 0 : A hardware service request for channel 14 is not present              */
#define  DMA_HWREQSTS_HREQSTS14_1                1U     /* 1 : A hardware service request for channel 14 is present                  */


/*                                               DMA HWREQSTS HREQSTS15 [15..15]                                                */
                                    /* DMA_HWREQSTS_HREQSTS15                                                     */
#define  DMA_HWREQSTS_HREQSTS15_0                0U     /* 0 : A hardware service request for channel 15 is not present              */
#define  DMA_HWREQSTS_HREQSTS15_1                1U     /* 1 : A hardware service request for channel 15 is present                  */


/*                                                           AREQSEN                                                            */
/*                                                 DMA AREQSEN AREQSEN0 [0..0]                                                  */
                                    /* DMA_AREQSEN_AREQSEN0                                                       */
#define  DMA_AREQSEN_AREQSEN0_0                  0U     /* 0 : Disable asynchronous DMA request for channel 0.                       */
#define  DMA_AREQSEN_AREQSEN0_1                  1U     /* 1 : Enable asynchronous DMA request for channel 0.                        */


/*                                                 DMA AREQSEN AREQSEN1 [1..1]                                                  */
                                     /* DMA_AREQSEN_AREQSEN1                                                       */
#define  DMA_AREQSEN_AREQSEN1_0                  0U     /* 0 : Disable asynchronous DMA request for channel 1                        */
#define  DMA_AREQSEN_AREQSEN1_1                  1U     /* 1 : Enable asynchronous DMA request for channel 1.                        */


/*                                                 DMA AREQSEN AREQSEN2 [2..2]                                                  */
                                    /* DMA_AREQSEN_AREQSEN2                                                       */
#define  DMA_AREQSEN_AREQSEN2_0                  0U     /* 0 : Disable asynchronous DMA request for channel 2.                       */
#define  DMA_AREQSEN_AREQSEN2_1                  1U     /* 1 : Enable asynchronous DMA request for channel 2.                        */


/*                                                 DMA AREQSEN AREQSEN3 [3..3]                                                  */
                            /* DMA_AREQSEN_AREQSEN3                                                       */
#define  DMA_AREQSEN_AREQSEN3_0                  0U     /* 0 : Disable asynchronous DMA request for channel 3.                       */
#define  DMA_AREQSEN_AREQSEN3_1                  1U     /* 1 : Enable asynchronous DMA request for channel 3.                        */


/*                                                 DMA AREQSEN AREQSEN4 [4..4]                                                  */
                              /* DMA_AREQSEN_AREQSEN4                                                       */
#define  DMA_AREQSEN_AREQSEN4_0                  0U     /* 0 : Disable asynchronous DMA request for channel 4.                       */
#define  DMA_AREQSEN_AREQSEN4_1                  1U     /* 1 : Enable asynchronous DMA request for channel 4.                        */


/*                                                 DMA AREQSEN AREQSEN5 [5..5]                                                  */
                              /* DMA_AREQSEN_AREQSEN5                                                       */
#define  DMA_AREQSEN_AREQSEN5_0                  0U     /* 0 : Disable asynchronous DMA request for channel 5.                       */
#define  DMA_AREQSEN_AREQSEN5_1                  1U     /* 1 : Enable asynchronous DMA request for channel 5.                        */


/*                                                 DMA AREQSEN AREQSEN6 [6..6]                                                  */
                            /* DMA_AREQSEN_AREQSEN6                                                       */
#define  DMA_AREQSEN_AREQSEN6_0                  0U     /* 0 : Disable asynchronous DMA request for channel 6.                       */
#define  DMA_AREQSEN_AREQSEN6_1                  1U     /* 1 : Enable asynchronous DMA request for channel 6.                        */


/*                                                 DMA AREQSEN AREQSEN7 [7..7]                                                  */
                            /* DMA_AREQSEN_AREQSEN7                                                       */
#define  DMA_AREQSEN_AREQSEN7_0                  0U     /* 0 : Disable asynchronous DMA request for channel 7.                       */
#define  DMA_AREQSEN_AREQSEN7_1                  1U     /* 1 : Enable asynchronous DMA request for channel 7.                        */


/*                                                 DMA AREQSEN AREQSEN8 [8..8]                                                  */
                            /* DMA_AREQSEN_AREQSEN8                                                       */
#define  DMA_AREQSEN_AREQSEN8_0                  0U     /* 0 : Disable asynchronous DMA request for channel 8.                       */
#define  DMA_AREQSEN_AREQSEN8_1                  1U     /* 1 : Enable asynchronous DMA request for channel 8.                        */


/*                                                 DMA AREQSEN AREQSEN9 [9..9]                                                  */
                                   /* DMA_AREQSEN_AREQSEN9                                                       */
#define  DMA_AREQSEN_AREQSEN9_0                  0U     /* 0 : Disable asynchronous DMA request for channel 9.                       */
#define  DMA_AREQSEN_AREQSEN9_1                  1U     /* 1 : Enable asynchronous DMA request for channel 9.                        */


/*                                                DMA AREQSEN AREQSEN10 [10..10]                                                */
                                 /* DMA_AREQSEN_AREQSEN10                                                      */
#define  DMA_AREQSEN_AREQSEN10_0                 0U     /* 0 : Disable asynchronous DMA request for channel 10.                      */
#define  DMA_AREQSEN_AREQSEN10_1                 1U     /* 1 : Enable asynchronous DMA request for channel 10.                       */


/*                                                DMA AREQSEN AREQSEN11 [11..11]                                                */
                                /* DMA_AREQSEN_AREQSEN11                                                      */
#define  DMA_AREQSEN_AREQSEN11_0                 0U     /* 0 : Disable asynchronous DMA request for channel 11.                      */
#define  DMA_AREQSEN_AREQSEN11_1                 1U     /* 1 : Enable asynchronous DMA request for channel 11.                       */


/*                                                DMA AREQSEN AREQSEN12 [12..12]                                                */
                                   /* DMA_AREQSEN_AREQSEN12                                                      */
#define  DMA_AREQSEN_AREQSEN12_0                 0U     /* 0 : Disable asynchronous DMA request for channel 12.                      */
#define  DMA_AREQSEN_AREQSEN12_1                 1U     /* 1 : Enable asynchronous DMA request for channel 12.                       */


/*                                                DMA AREQSEN AREQSEN13 [13..13]                                                */
                              /* DMA_AREQSEN_AREQSEN13                                                      */
#define  DMA_AREQSEN_AREQSEN13_0                 0U     /* 0 : Disable asynchronous DMA request for channel 13.                      */
#define  DMA_AREQSEN_AREQSEN13_1                 1U     /* 1 : Enable asynchronous DMA request for channel 13.                       */


/*                                                DMA AREQSEN AREQSEN14 [14..14]                                                */
                               /* DMA_AREQSEN_AREQSEN14                                                      */
#define  DMA_AREQSEN_AREQSEN14_0                 0U     /* 0 : Disable asynchronous DMA request for channel 14.                      */
#define  DMA_AREQSEN_AREQSEN14_1                 1U     /* 1 : Enable asynchronous DMA request for channel 14.                       */


/*                                               DMA EAREQS AREQSEN15 [15..15]                                                */
                                    /* DMA_EAREQS_EAREQSEN15                                                     */
#define  DMA_EAREQS_EAREQSEN15_0                0U     /* 0 : Disable asynchronous DMA request for channel 15.                      */
#define  DMA_EAREQS_EAREQSEN15_1                1U     /* 1 : Enable asynchronous DMA request for channel 15.                       */


/*                                                           CHPRI3                                                            */
/*                                                 DMA CHPRI3 PLPRICHD [6..6]                                                  */
                                 /* DMA_CHPRI3_PLPRICHD                                                       */
#define  DMA_CHPRI3_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI3_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI3 BPHPRICHEN [7..7]                                                 */
                                      /* DMA_CHPRI3_BPHPRICHEN                                                     */
#define  DMA_CHPRI3_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                      service request.                                                          */
#define  DMA_CHPRI3_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                    of a higher priority channel.                                             */


/*                                                           CHPRI2                                                            */
/*                                                 DMA CHPRI2 PLPRICHD [6..6]                                                  */
                                    /* DMA_CHPRI2_PLPRICHD                                                       */
#define  DMA_CHPRI2_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI2_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI2 BPHPRICHEN [7..7]                                                 */
    /* DMA_CHPRI2_BPHPRICHEN                                                     */
 #define DMA_CHPRI2_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                     service request.                                                          */
 #define DMA_CHPRI2_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                     of a higher priority channel.                                             */


/*                                                           CHPRI1                                                            */
/*                                                 DMA CHPRI1 PLPRICHD [6..6]                                                  */
                                    /* DMA_CHPRI1_PLPRICHD                                                       */
#define  DMA_CHPRI1_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI1_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI1 BPHPRICHEN [7..7]                                                 */
                                    /* DMA_CHPRI1_BPHPRICHEN                                                     */
 #define DMA_CHPRI1_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                      service request.                                                          */
 #define DMA_CHPRI1_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                       of a higher priority channel.                                             */


/*                                                           CHPRI0                                                            */
/*                                                 DMA CHPRI0 PLPRICHD [6..6]                                                  */
                                    /* DMA_CHPRI0_PLPRICHD                                                       */
#define  DMA_CHPRI0_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI0_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI0 BPHPRICHEN [7..7]                                                 */
                                   /* DMA_CHPRI0_BPHPRICHEN                                                     */
#define  DMA_CHPRI0_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                        service request.                                                          */
#define  DMA_CHPRI0_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                            of a higher priority channel.                                             */


/*                                                           CHPRI7                                                            */
/*                                                 DMA CHPRI7 PLPRICHD [6..6]                                                  */
                             /* DMA_CHPRI7_PLPRICHD                                                       */
#define  DMA_CHPRI7_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI7_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI7 BPHPRICHEN [7..7]                                                 */
                              /* DMA_CHPRI7_BPHPRICHEN                                                     */
#define  DMA_CHPRI7_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                    service request.                                                          */
#define  DMA_CHPRI7_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                       of a higher priority channel.                                             */


/*                                                           CHPRI6                                                            */
/*                                                 DMA CHPRI6 PLPRICHD [6..6]                                                  */
                                     /* DMA_CHPRI6_PLPRICHD                                                       */
#define  DMA_CHPRI6_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI6_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI6 BPHPRICHEN [7..7]                                                 */
                                     /* DMA_CHPRI6_BPHPRICHEN                                                     */
 #define DMA_CHPRI6_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                 service request.                                                          */
 #define DMA_CHPRI6_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                   of a higher priority channel.                                             */


/*                                                           CHPRI5                                                            */
/*                                                 DMA CHPRI5 PLPRICHD [6..6]                                                  */
                                     /* DMA_CHPRI5_PLPRICHD                                                       */
 #define DMA_CHPRI5_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
 #define DMA_CHPRI5_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI5 BPHPRICHEN [7..7]                                                 */
                                  /* DMA_CHPRI5_BPHPRICHEN                                                     */
#define  DMA_CHPRI5_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                   service request.                                                          */
#define  DMA_CHPRI5_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                       of a higher priority channel.                                             */


/*                                                           CHPRI4                                                            */
/*                                                 DMA CHPRI4 PLPRICHD [6..6]                                                  */
                                   /* DMA_CHPRI4_PLPRICHD                                                       */
#define  DMA_CHPRI4_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI4_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI4 BPHPRICHEN [7..7]                                                 */
                                    /* DMA_CHPRI4_BPHPRICHEN                                                     */
#define  DMA_CHPRI4_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                       service request.                                                          */
#define  DMA_CHPRI4_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                      of a higher priority channel.                                             */


/*                                                           CHPRI11                                                           */
/*                                                 DMA CHPRI11 PLPRICHD [6..6]                                                 */
                                      /* DMA_CHPRI11_PLPRICHD                                                      */
#define  DMA_CHPRI11_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI11_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI11 BPHPRICHEN [7..7]                                                */
                                     /* DMA_CHPRI11_BPHPRICHEN                                                    */
#define  DMA_CHPRI11_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                    service request.                                                          */
#define  DMA_CHPRI11_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                    of a higher priority channel.                                             */


/*                                                           CHPRI10                                                           */
/*                                                 DMA CHPRI10 PLPRICHD [6..6]                                                 */
                                      /* DMA_CHPRI10_PLPRICHD                                                      */
#define  DMA_CHPRI10_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI10_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                        priority.                                                                 */


/*                                                DMA CHPRI10 BPHPRICHEN [7..7]                                                */
                                      /* DMA_CHPRI10_BPHPRICHEN                                                    */
#define  DMA_CHPRI10_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                         service request.                                                          */
#define  DMA_CHPRI10_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                       of a higher priority channel.                                             */


/*                                                           CHPRI9                                                            */
/*                                                 DMA CHPRI9 PLPRICHD [6..6]                                                  */
                                  /* DMA_CHPRI9_PLPRICHD                                                       */
#define  DMA_CHPRI9_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI9_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                        priority.                                                                 */


/*                                                DMA CHPRI9 BPHPRICHEN [7..7]                                                 */
                                     /* DMA_CHPRI9_BPHPRICHEN                                                     */
#define  DMA_CHPRI9_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                        service request.                                                          */
#define  DMA_CHPRI9_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                        of a higher priority channel.                                             */


/*                                                           CHPRI8                                                            */
/*                                                 DMA CHPRI8 PLPRICHD [6..6]                                                  */
                                     /* DMA_CHPRI8_PLPRICHD                                                       */
#define  DMA_CHPRI8_PLPRICHD_0                  0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI8_PLPRICHD_1                  1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI8 BPHPRICHEN [7..7]                                                 */
                             /* DMA_CHPRI8_BPHPRICHEN                                                     */
#define  DMA_CHPRI8_BPHPRICHEN_0                0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                         service request.                                                          */
#define  DMA_CHPRI8_BPHPRICHEN_1                1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                        of a higher priority channel.                                             */


/*                                                           CHPRI15                                                           */
/*                                                 DMA CHPRI15 PLPRICHD [6..6]                                                 */
                              /* DMA_CHPRI15_PLPRICHD                                                      */
#define  DMA_CHPRI15_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI15_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI15 BPHPRICHEN [7..7]                                                */
                               /* DMA_CHPRI15_BPHPRICHEN                                                    */
#define  DMA_CHPRI15_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                        service request.                                                          */
#define  DMA_CHPRI15_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                      of a higher priority channel.                                             */


/*                                                           CHPRI14                                                           */
/*                                                 DMA CHPRI14 PLPRICHD [6..6]                                                 */
                                    /* DMA_CHPRI14_PLPRICHD                                                      */
#define  DMA_CHPRI14_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
#define  DMA_CHPRI14_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI14 BPHPRICHEN [7..7]                                                */
                                /* DMA_CHPRI14_BPHPRICHEN                                                    */
 #define DMA_CHPRI14_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                               service request.                                                          */
 #define DMA_CHPRI14_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                       of a higher priority channel.                                             */


/*                                                           CHPRI13                                                           */
/*                                                 DMA CHPRI13 PLPRICHD [6..6]                                                 */
                                   /* DMA_CHPRI13_PLPRICHD                                                      */
 #define DMA_CHPRI13_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
 #define DMA_CHPRI13_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                         priority.                                                                 */


/*                                                DMA CHPRI13 BPHPRICHEN [7..7]                                                */
                                  /* DMA_CHPRI13_BPHPRICHEN                                                    */
#define  DMA_CHPRI13_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                        service request.                                                          */
#define  DMA_CHPRI13_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                        of a higher priority channel.                                             */


/*                                                           CHPRI12                                                           */
/*                                                 DMA CHPRI12 PLPRICHD [6..6]                                                 */
                                   /* DMA_CHPRI12_PLPRICHD                                                      */
 #define DMA_CHPRI12_PLPRICHD_0                 0U     /* 0 : Channel n can suspend a lower priority channel.                       */
 #define DMA_CHPRI12_PLPRICHD_1                 1U     /* 1 : Channel n cannot suspend any channelU regardless of channel
                                                     priority.                                                                 */


/*                                                DMA CHPRI12 BPHPRICHEN [7..7]                                                */
                                /* DMA_CHPRI12_BPHPRICHEN                                                    */
 #define DMA_CHPRI12_BPHPRICHEN_0               0U     /* 0 : Channel n cannot be suspended by a higher priority channels
                                                        service request.                                                          */
 #define DMA_CHPRI12_BPHPRICHEN_1               1U     /* 1 : Channel n can be temporarily suspended by the service request
                                                        of a higher priority channel.                                             */


/*                                                         TCD_SADDR                                                          */
/*                                                        TCD_SADDROF                                                         */
/*                                                          TCD_TATT                                                          */
/*                                                DMA TCD_TATT STSIZE [8..10]                                                 */
                                      /* DMA_TCD_TATT_STSIZE                                                      */
#define  DMA_TCD_TATT_STSIZE_0                 0U     /* 0 : 8-bit                                                                 */
#define  DMA_TCD_TATT_STSIZE_1                 1U     /* 1 : 16-bit                                                                */
#define  DMA_TCD_TATT_STSIZE_10                2U     /* 10 : 32-bit                                                               */

/*                                               DMA TCD_TATT SADDRMV [11..15]                                                */
                                      /* DMA_TCD_TATT_SADDRMV                                                     */
#define  DMA_TCD_TATT_SADDRMV_0                0U     /* 0 : Source address modulo feature is disabled                             */


/*                                                     TCD_MINBCNT_MINLMD_DMA                                                     */
/*                                                   TCD_SMLOF_MINLMENOFD_DMA                                                   */
/*                                       DMA TCD_SMLOF_MINLMENOFD_DMA DMINLOFEN [30..30]                                        */
                                     /* DMA_TCD_SMLOF_MINLMENOFD_DMA_DMINLOFEN                                     */
#define  DMA_TCD_SMLOF_MINLMENOFD_DMA_DMINLOFEN_0   0U  /* 0 : The minor loop offset is not applied to the DADDR                     */
#define  DMA_TCD_SMLOF_MINLMENOFD_DMA_DMINLOFEN_1   1U  /* 1 : The minor loop offset is applied to the DADDR                         */


/*                                       DMA TCD_SMLOF_MINLMENOFD_DMA SMINLOFEN [31..31]                                        */
                               /* DMA_TCD_SMLOF_MINLMENOFD_DMA_SMINLOFEN                                     */
#define  DMA_TCD_SMLOF_MINLMENOFD_DMA_SMINLOFEN_0   0U  /* 0 : The minor loop offset is not applied to the SADDR                     */
#define  DMA_TCD_SMLOF_MINLMENOFD_DMA_SMINLOFEN_1   1U  /* 1 : The minor loop offset is applied to the SADDR                         */


/*                                                   TCD_SMINLOF_MINLMOFEN_DMA                                                    */
/*                                        DMA TCD_SMINLOF_MINLMOFEN_DMA DMINLOFEN [30..30]                                        */
    /* DMA_TCD_SMINLOF_MINLMOFEN_DMA_DMINLOFEN                                      */
#define  DMA_TCD_SMINLOF_MINLMOFEN_DMA_DMINLOFEN_0   0U   /* 0 : The minor loop offset is not applied to the DADDR                     */
#define  DMA_TCD_SMINLOF_MINLMOFEN_DMA_DMINLOFEN_1   1U   /* 1 : The minor loop offset is applied to the DADDR                         */


/*                                        DMA TCD_SMINLOF_MINLMOFEN_DMA SMINLOFEN [31..31]                                        */
                  /* DMA_TCD_SMINLOF_MINLMOFEN_DMA_SMINLOFEN                                      */
#define  DMA_TCD_SMINLOF_MINLMOFEN_DMA_SMINLOFEN_0   0U   /* 0 : The minor loop offset is not applied to the SADDR                     */
#define  DMA_TCD_SMINLOF_MINLMOFEN_DMA_SMINLOFEN_1   1U   /* 1 : The minor loop offset is applied to the SADDR                         */


/*                                                        TCD_SADDRAV                                                         */
/*                                                         TCD_DADDR                                                          */
/*                                                        TCD_DADDRSOF                                                        */
/*                                                   TCD_CMAJICNT_LINKD_DMA                                                   */
/*                                       DMA TCD_CMAJICNT_LINKD_DMA MINLINKEN [15..15]                                        */
                                  /* DMA_TCD_CMAJICNT_LINKD_DMA_MINLINKEN                                     */
 #define DMA_TCD_CMAJICNT_LINKD_DMA_LINKEN_0   0U  /* 0 : The channel-to-channel linking is disabled                            */
 #define DMA_TCD_CMAJICNT_LINKD_DMA_LINKEN_1   1U  /* 1 : The channel-to-channel linking is enabled                             */


/*                                                 TCD_CMAJICNT_CHLINKEN_DMA                                                  */
/*                                      DMA TCD_CMAJICNT_CHLINKEN_DMA MINLINKEN [15..15]                                      */
                                  /* DMA_TCD_CMAJICNT_CHLINKEN_DMA_MINLINKEN                                  */
#define  DMA_TCD_CMAJICNT_LINKEN_DMA_LINKEN_0   0U/* 0 : The channel-to-channel linking is disabled                           */
#define  DMA_TCD_CMAJICNT_LINKEN_DMA_LINKEN_1   1U/* 1 : The channel-to-channel linking is enabled                            */


/*                                                       TCD_DADDRAVSGA                                                       */
/*                                                          TCD_CSTS                                                          */
/*                                                 DMA TCD_CSTS START [0..0]                                                  */
                                  /* DMA_TCD_CSTS_START                                                       */
#define  DMA_TCD_CSTS_START_0                  0U     /* 0 : The channel is not explicitly started.                                */
#define  DMA_TCD_CSTS_START_1                  1U     /* 1 : The channel is explicitly started via a software initiated
                                                     service request.                                                          */


/*                                                DMA TCD_CSTS MAJICMPIEN [1..1]                                                */
                                  /* DMA_TCD_CSTS_MAJICMPIEN                                                    */
#define  DMA_TCD_CSTS_MAJICMPIEN_0               0U     /* 0 : The end-of-major loop interrupt is disabled.                          */
#define  DMA_TCD_CSTS_MAJICMPIEN_1               1U     /* 1 : The end-of-major loop interrupt is enabled.                           */


/*                                               DMA TCD_CSTS MAJIHCMPIEN [2..2]                                                */
                                  /* DMA_TCD_CSTS_MAJIHCMPIEN                                                   */
#define  DMA_TCD_CSTS_MAJIHCMPIEN_0              0U     /* 0 : The half-point interrupt is disabled.                                 */
#define  DMA_TCD_CSTS_MAJIHCMPIEN_1              1U     /* 1 : The half-point interrupt is enabled.                                  */

/*                                               DMA TCD_CSTS DMAREQD [3..3]                                                */
                                  /* DMA_TCD_CSTS_DMAREQD                                                   */
#define  DMA_TCD_CSTS_DMAREQD_0              0U     /* 0 : The channel's ERQ bit is not affected.                                 */
#define  DMA_TCD_CSTS_DMAREQD_1              1U     /* 1 : The channel's ERQ bit is cleared when the major loop is complete.                                  */

/*                                                 DMA TCD_CSTS SGFEN [4..4]                                                  */
                                      /* DMA_TCD_CSTS_SGFEN                                                       */
#define  DMA_TCD_CSTS_SGFEN_0                  0U     /* 0 : The current channels TCD is normal format.                            */
#define  DMA_TCD_CSTS_SGFEN_1                  1U     /* 1 : The current channels TCD specifies a scatter gather format.
                                                     The DLASTSGA field provides a memory pointer to the next
                                                     TCD to be loaded into this channel after the major loop
                                                     completes its execution.                                                  */

/*                                               DMA TCD_CSTS MAJILINKEN [5..5]                                                */
                                    /* DMA_TCD_CSTS_MAJILINKEN                                                   */
#define  DMA_TCD_CSTS_MAJILINKEN_0              0U     /* 0 : The channel-to-channel linking is disabled.                           */
#define  DMA_TCD_CSTS_MAJILINKEN_1              1U     /* 1 : The channel-to-channel linking is enabled.                            */

/*                                               DMA TCD_CSTS MAJLCMPFLG [7..7]                                                */
                                    /* DMA_TCD_CSTS_MAJLCMPFLG                                                   */
#define  DMA_TCD_CSTS_MAJLCMPFLG_0              0U     /* 0 : Indicates the DMA has not completed the major loop.
                                                       This bit must be cleared to write the MAJILINKEN or SGFEN bits.*/
#define  DMA_TCD_CSTS_MAJLCMPFLG_1              1U     /* 1 : Indicates the DMA has completed the major loop.                            */

/*                                                DMA TCD_CSTS BWCTRL [14..15]                                                */
                                     /* DMA_TCD_CSTS_BWCTRL                                                      */
#define  DMA_TCD_CSTS_BWCTRL_0                 0U     /* 0 : No eDMA engine stalls.                                                */
#define  DMA_TCD_CSTS_BWCTRL_10                2U     /* 10 : eDMA engine stalls for 4 cycles after each R/W.                      */
#define  DMA_TCD_CSTS_BWCTRL_11                3U     /* 11 : eDMA engine stalls for 8 cycles after each R/W.                      */


/*                                                 TCD_MAJICNTSTAT_LINKD_DMA                                                  */
/*                                       DMA TCD_MAJICNTSTAT_LINKD_DMA LINKEN [15..15]                                        */
                                  /* DMA_TCD_MAJICNTSTAT_LINKD_DMA_LINKEN                                     */
#define  DMA_TCD_MAJICNTSTAT_LINKD_DMA_LINKEN_0   0U  /* 0 : The channel-to-channel linking is disabled                            */
#define  DMA_TCD_MAJICNTSTAT_LINKD_DMA_LINKEN_1   1U  /* 1 : The channel-to-channel linking is enabled                             */


/*                                                 TCD_MAJICNTSTAT_LINKEN_DMA                                                 */
/*                                     DMA TCD_MAJICNTSTAT_LINKEN_DMA LINKEN [15..15]                                      */
                                    /* DMA_TCD_MAJICNTSTAT_LINKEN_DMA_LINKEN                                 */
#define  DMA_TCD_MAJICNTSTAT_LINKEN_DMA_LINKEN_0   0U/* 0 : The channel-to-channel linking is disabled                          */
#define  DMA_TCD_MAJICNTSTAT_LINKEN_DMA_LINKEN_1   1U/* 1 : The channel-to-channel linking is enabled                           */


/*                                                                                                                             */
/*                                                             MPU                                                              */
/*                                                                                                                             */

/*                                                            CESTS                                                            */
/*                                                    MPU CESTS MPUEN [0..0]                                                     */
                                 /* MPU_CESTS_MPUEN                                                             */
#define  MPU_CESTS_MPUEN_0                        0U     /* 0 : MPU is disabled. All accesses from all bus masters are allowed.       */
#define  MPU_CESTS_MPUEN_1                        1U     /* 1 : MPU is enabled                                                        */


/*                                                   MPU CESTS RDINUM [8..11]                                                   */
                                 /* MPU_CESTS_RDINUM                                                           */
#define  MPU_CESTS_RDINUM_0000                   0U     /* 0000 : 8 region descriptors                                               */
#define  MPU_CESTS_RDINUM_0001                   1U     /* 0001 : 12 region descriptors                                              */
#define  MPU_CESTS_RDINUM_0010                   2U     /* 0010 : 16 region descriptors                                              */


/*                                                  MPU CESTS SPEFLG3 [28..28]                                                  */
                                 /* MPU_CESTS_SPEFLG3                                                          */
#define  MPU_CESTS_SPEFLG3_0                     0U     /* 0 : No error has occurred for slave port 3.                               */
#define  MPU_CESTS_SPEFLG3_1                     1U     /* 1 : An error has occurred for slave port 3.                               */


/*                                                  MPU CESTS SPEFLG2 [29..29]                                                  */
                                 /* MPU_CESTS_SPEFLG2                                                          */
#define  MPU_CESTS_SPEFLG2_0                     0U     /* 0 : No error has occurred for slave port 2.                               */
#define  MPU_CESTS_SPEFLG2_1                     1U     /* 1 : An error has occurred for slave port 2.                               */


/*                                                  MPU CESTS SPEFLG1 [30..30]                                                  */
                                 /* MPU_CESTS_SPEFLG1                                                          */
#define  MPU_CESTS_SPEFLG1_0                     0U     /* 0 : No error has occurred for slave port 1.                               */
#define  MPU_CESTS_SPEFLG1_1                     1U     /* 1 : An error has occurred for slave port 1.                               */


/*                                                  MPU CESTS SPEFLG0 [31..31]                                                  */
                                 /* MPU_CESTS_SPEFLG0                                                          */
#define  MPU_CESTS_SPEFLG0_0                     0U     /* 0 : No error has occurred for slave port 0.                               */
#define  MPU_CESTS_SPEFLG0_1                     1U     /* 1 : An error has occurred for slave port 0.                               */


/*                                                           EADDR0                                                            */
/*                                                          EDETAIL0                                                           */
/*                                                   MPU EDETAIL0 RWE [0..0]                                                    */
                                 /* MPU_EDETAIL0_RWE                                                           */
#define  MPU_EDETAIL0_RWE_0                      0U     /* 0 : Read                                                                  */
#define  MPU_EDETAIL0_RWE_1                      1U     /* 1 : Write                                                                 */


/*                                                  MPU EDETAIL0 AINFOE [1..3]                                                  */
                                 /* MPU_EDETAIL0_AINFOE                                                        */
#define  MPU_EDETAIL0_AINFOE_000                 0U     /* 000 : User modeU instruction access                                       */
#define  MPU_EDETAIL0_AINFOE_001                 1U     /* 001 : User modeU data access                                              */
#define  MPU_EDETAIL0_AINFOE_010                 2U     /* 010 : Supervisor modeU instruction access                                 */
#define  MPU_EDETAIL0_AINFOE_011                 3U     /* 011 : Supervisor modeU data access                                        */


/*                                                           EADDR1                                                            */
/*                                                          EDETAIL1                                                           */
/*                                                   MPU EDETAIL1 RWE [0..0]                                                    */
                                 /* MPU_EDETAIL1_RWE                                                           */
 #define MPU_EDETAIL1_RWE_0                      0U     /* 0 : Read                                                                  */
 #define MPU_EDETAIL1_RWE_1                      1U     /* 1 : Write                                                                 */


/*                                                  MPU EDETAIL1 AINFOE [1..3]                                                  */
                                 /* MPU_EDETAIL1_AINFOE                                                        */
 #define MPU_EDETAIL1_AINFOE_000                 0U     /* 000 : User modeU instruction access                                       */
 #define MPU_EDETAIL1_AINFOE_001                 1U     /* 001 : User modeU data access                                              */
 #define MPU_EDETAIL1_AINFOE_010                 2U     /* 010 : Supervisor modeU instruction access                                 */
 #define MPU_EDETAIL1_AINFOE_011                 3U     /* 011 : Supervisor modeU data access                                        */


/*                                                           EADDR2                                                            */
/*                                                          EDETAIL2                                                           */
/*                                                   MPU EDETAIL2 RWE [0..0]                                                    */
                                 /* MPU_EDETAIL2_RWE                                                           */
#define  MPU_EDETAIL2_RWE_0                      0U     /* 0 : Read                                                                  */
#define  MPU_EDETAIL2_RWE_1                      1U     /* 1 : Write                                                                 */


/*                                                  MPU EDETAIL2 AINFOE [1..3]                                                  */
                                 /* MPU_EDETAIL2_AINFOE                                                        */
#define  MPU_EDETAIL2_AINFOE_000                 0U     /* 000 : User modeU instruction access                                       */
#define  MPU_EDETAIL2_AINFOE_001                 1U     /* 001 : User modeU data access                                              */
#define  MPU_EDETAIL2_AINFOE_010                 2U     /* 010 : Supervisor modeU instruction access                                 */
#define  MPU_EDETAIL2_AINFOE_011                 3U     /* 011 : Supervisor modeU data access                                        */


/*                                                           EADDR3                                                            */
/*                                                          EDETAIL3                                                           */
/*                                                   MPU EDETAIL3 RWE [0..0]                                                    */
                                 /* MPU_EDETAIL3_RWE                                                           */
 #define MPU_EDETAIL3_RWE_0                      0U     /* 0 : Read                                                                  */
 #define MPU_EDETAIL3_RWE_1                      1U     /* 1 : Write                                                                 */


/*                                                  MPU EDETAIL3 AINFOE [1..3]                                                  */
                                 /* MPU_EDETAIL3_AINFOE                                                        */
#define  MPU_EDETAIL3_AINFOE_000                 0U     /* 000 : User modeU instruction access                                       */
#define  MPU_EDETAIL3_AINFOE_001                 1U     /* 001 : User modeU data access                                              */
#define  MPU_EDETAIL3_AINFOE_010                 2U     /* 010 : Supervisor modeU instruction access                                 */
#define  MPU_EDETAIL3_AINFOE_011                 3U     /* 011 : Supervisor modeU data access                                        */


/*                                                         REGD0_WORD0                                                         */
/*                                                         REGD0_WORD1                                                         */
/*                                                         REGD0_WORD2                                                         */
/*                                               MPU REGD0_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD0_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD0_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD0_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD0_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD0_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD0_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD0_WORD2_PIDENM0                                                    */
#define  MPU_REGD0_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD0_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD0_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD0_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD0_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD0_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD0_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD0_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD0_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD0_WORD2_PIDENM1                                                    */
 #define MPU_REGD0_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
 #define MPU_REGD0_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD0_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD0_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD0_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD0_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD0_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD0_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD0_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD0_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD0_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD0_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD0_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD0_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD0_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD0_WORD2_WENM4                                                      */
#define  MPU_REGD0_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD0_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD0_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD0_WORD2_RENM4                                                      */
#define  MPU_REGD0_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD0_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD0_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD0_WORD2_WENM5                                                      */
#define  MPU_REGD0_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD0_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD0_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD0_WORD2_RENM5                                                      */
#define  MPU_REGD0_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_REGD0_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD0_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD0_WORD2_WENM6                                                      */
#define  MPU_REGD0_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_REGD0_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD0_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD0_WORD2_RENM6                                                      */
#define  MPU_REGD0_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                         read is not performed                                                     */
#define  MPU_REGD0_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD0_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD0_WORD2_WENM7                                                      */
#define MPU_REGD0_WORD2_WENM7_0                  0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_REGD0_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD0_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD0_WORD2_RENM7                                                      */
#define  MPU_REGD0_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD0_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD0_WORD3                                                         */
/*                                                MPU REGD0_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD0_WORD3_RDVALID                                                    */
#define  MPU_REGD0_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD0_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD1_WORD0                                                         */
/*                                                         REGD1_WORD1                                                         */
/*                                                         REGD1_WORD2                                                         */
/*                                               MPU REGD1_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD1_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD1_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD1_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD1_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD1_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD1_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD1_WORD2_PIDENM0                                                    */
#define  MPU_REGD1_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD1_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD1_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD1_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD1_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD1_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD1_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD1_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD1_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD1_WORD2_PIDENM1                                                    */
#define  MPU_REGD1_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD1_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD1_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD1_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD1_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD1_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD1_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD1_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD1_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD1_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD1_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD1_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD1_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD1_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD1_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD1_WORD2_WENM4                                                      */
#define MPU_REGD1_WORD2_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define MPU_REGD1_WORD2_WENM4_1                  1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD1_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD1_WORD2_RENM4                                                      */
#define  MPU_REGD1_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                    read is not performed                                                     */
#define  MPU_REGD1_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD1_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD1_WORD2_WENM5                                                      */
#define  MPU_REGD1_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD1_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD1_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD1_WORD2_RENM5                                                      */
#define  MPU_REGD1_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD1_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD1_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD1_WORD2_WENM6                                                      */
#define  MPU_REGD1_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_REGD1_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD1_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD1_WORD2_RENM6                                                      */
#define  MPU_REGD1_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD1_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD1_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD1_WORD2_WENM7                                                      */
#define  MPU_REGD1_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD1_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD1_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD1_WORD2_RENM7                                                      */
#define  MPU_REGD1_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD1_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD1_WORD3                                                         */
/*                                                MPU REGD1_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD1_WORD3_RDVALID                                                    */
#define  MPU_REGD1_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD1_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD2_WORD0                                                         */
/*                                                         REGD2_WORD1                                                         */
/*                                                         REGD2_WORD2                                                         */
/*                                               MPU REGD2_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD2_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD2_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD2_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD2_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD2_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD2_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD2_WORD2_PIDENM0                                                    */
#define  MPU_REGD2_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD2_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD2_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD2_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD2_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD2_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD2_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD2_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD2_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD2_WORD2_PIDENM1                                                    */
#define  MPU_REGD2_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD2_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD2_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD2_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD2_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD2_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD2_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD2_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD2_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD2_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD2_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD2_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD2_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD2_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD2_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD2_WORD2_WENM4                                                      */
#define  MPU_REGD2_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD2_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD2_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD2_WORD2_RENM4                                                      */
#define  MPU_REGD2_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                  read is not performed                                                     */
#define  MPU_REGD2_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD2_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD2_WORD2_WENM5                                                      */
#define  MPU_REGD2_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                    write is not performed                                                    */
#define  MPU_REGD2_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD2_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD2_WORD2_RENM5                                                      */
#define  MPU_REGD2_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                    read is not performed                                                     */
#define  MPU_REGD2_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD2_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD2_WORD2_WENM6                                                      */
#define  MPU_REGD2_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD2_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD2_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD2_WORD2_RENM6                                                      */
#define  MPU_REGD2_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_REGD2_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD2_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD2_WORD2_WENM7                                                      */
#define  MPU_REGD2_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_REGD2_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD2_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD2_WORD2_RENM7                                                      */
#define  MPU_REGD2_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                    read is not performed                                                     */
#define  MPU_REGD2_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD2_WORD3                                                         */
/*                                                MPU REGD2_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD2_WORD3_RDVALID                                                    */
#define  MPU_REGD2_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD2_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD3_WORD0                                                         */
/*                                                         REGD3_WORD1                                                         */
/*                                                         REGD3_WORD2                                                         */
/*                                               MPU REGD3_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD3_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD3_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD3_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD3_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD3_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD3_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD3_WORD2_PIDENM0                                                    */
#define  MPU_REGD3_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD3_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD3_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD3_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD3_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD3_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD3_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD3_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD3_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD3_WORD2_PIDENM1                                                    */
#define  MPU_REGD3_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD3_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD3_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD3_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD3_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD3_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD3_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD3_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD3_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD3_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD3_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD3_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD3_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD3_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD3_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD3_WORD2_WENM4                                                      */
#define  MPU_REGD3_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_REGD3_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD3_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD3_WORD2_RENM4                                                      */
#define  MPU_REGD3_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                 read is not performed                                                     */
#define  MPU_REGD3_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD3_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD3_WORD2_WENM5                                                      */
#define  MPU_REGD3_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD3_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD3_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD3_WORD2_RENM5                                                      */
#define  MPU_REGD3_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_REGD3_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD3_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD3_WORD2_WENM6                                                      */
#define MPU_REGD3_WORD2_WENM6_0                  0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD3_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD3_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD3_WORD2_RENM6                                                      */
#define  MPU_REGD3_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD3_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD3_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD3_WORD2_WENM7                                                      */
#define  MPU_REGD3_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD3_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD3_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD3_WORD2_RENM7                                                      */
#define  MPU_REGD3_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD3_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD3_WORD3                                                         */
/*                                                MPU REGD3_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD3_WORD3_RDVALID                                                    */
#define  MPU_REGD3_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD3_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD4_WORD0                                                         */
/*                                                         REGD4_WORD1                                                         */
/*                                                         REGD4_WORD2                                                         */
/*                                               MPU REGD4_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD4_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD4_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD4_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD4_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD4_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD4_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD4_WORD2_PIDENM0                                                    */
#define  MPU_REGD4_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD4_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD4_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD4_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD4_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD4_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD4_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD4_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD4_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD4_WORD2_PIDENM1                                                    */
#define  MPU_REGD4_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD4_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD4_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD4_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD4_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD4_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD4_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD4_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD4_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD4_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD4_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD4_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD4_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD4_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD4_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD4_WORD2_WENM4                                                      */
#define  MPU_REGD4_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD4_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD4_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD4_WORD2_RENM4                                                      */
#define  MPU_REGD4_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_REGD4_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD4_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD4_WORD2_WENM5                                                      */
#define  MPU_REGD4_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_REGD4_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD4_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD4_WORD2_RENM5                                                      */
#define  MPU_REGD4_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                               read is not performed                                                     */
#define  MPU_REGD4_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD4_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD4_WORD2_WENM6                                                      */
#define  MPU_REGD4_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                    write is not performed                                                    */
#define  MPU_REGD4_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD4_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD4_WORD2_RENM6                                                      */
#define  MPU_REGD4_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD4_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD4_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD4_WORD2_WENM7                                                      */
#define  MPU_REGD4_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                write is not performed                                                    */
#define  MPU_REGD4_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD4_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD4_WORD2_RENM7                                                      */
#define MPU_REGD4_WORD2_RENM7_0                  0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                       read is not performed                                                     */
#define MPU_REGD4_WORD2_RENM7_1                  1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD4_WORD3                                                         */
/*                                                MPU REGD4_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD4_WORD3_RDVALID                                                    */
#define  MPU_REGD4_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD4_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD5_WORD0                                                         */
/*                                                         REGD5_WORD1                                                         */
/*                                                         REGD5_WORD2                                                         */
/*                                               MPU REGD5_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD5_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD5_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD5_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD5_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD5_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD5_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD5_WORD2_PIDENM0                                                    */
#define  MPU_REGD5_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD5_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD5_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD5_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD5_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD5_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD5_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD5_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD5_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD5_WORD2_PIDENM1                                                    */
#define  MPU_REGD5_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD5_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD5_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD5_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD5_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD5_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD5_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD5_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD5_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD5_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD5_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD5_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD5_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD5_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD5_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD5_WORD2_WENM4                                                      */
#define  MPU_REGD5_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_REGD5_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD5_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD5_WORD2_RENM4                                                      */
#define  MPU_REGD5_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_REGD5_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD5_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD5_WORD2_WENM5                                                      */
#define  MPU_REGD5_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                 write is not performed                                                    */
#define  MPU_REGD5_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD5_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD5_WORD2_RENM5                                                      */
#define  MPU_REGD5_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_REGD5_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD5_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD5_WORD2_WENM6                                                      */
#define  MPU_REGD5_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_REGD5_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD5_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD5_WORD2_RENM6                                                      */
#define  MPU_REGD5_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD5_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD5_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD5_WORD2_WENM7                                                      */
#define  MPU_REGD5_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_REGD5_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD5_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD5_WORD2_RENM7                                                      */
#define  MPU_REGD5_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                       read is not performed                                                     */
#define  MPU_REGD5_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD5_WORD3                                                         */
/*                                                MPU REGD5_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD5_WORD3_RDVALID                                                    */
#define  MPU_REGD5_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD5_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD6_WORD0                                                         */
/*                                                         REGD6_WORD1                                                         */
/*                                                         REGD6_WORD2                                                         */
/*                                               MPU REGD6_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD6_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD6_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD6_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD6_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD6_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD6_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD6_WORD2_PIDENM0                                                    */
#define  MPU_REGD6_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD6_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD6_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD6_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD6_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD6_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD6_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD6_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD6_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD6_WORD2_PIDENM1                                                    */
#define  MPU_REGD6_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD6_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD6_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD6_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD6_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD6_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD6_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD6_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD6_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD6_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD6_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD6_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD6_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD6_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD6_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD6_WORD2_WENM4                                                      */
#define  MPU_REGD6_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_REGD6_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD6_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD6_WORD2_RENM4                                                      */
#define  MPU_REGD6_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                         read is not performed                                                     */
#define  MPU_REGD6_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD6_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD6_WORD2_WENM5                                                      */
#define  MPU_REGD6_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD6_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD6_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD6_WORD2_RENM5                                                      */
#define  MPU_REGD6_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
    #define                                                     read is not performed                                                     */
#define  MPU_REGD6_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD6_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD6_WORD2_WENM6                                                      */
#define  MPU_REGD6_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD6_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD6_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD6_WORD2_RENM6                                                      */
#define  MPU_REGD6_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                       read is not performed                                                     */
#define  MPU_REGD6_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD6_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD6_WORD2_WENM7                                                      */
#define  MPU_REGD6_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_REGD6_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD6_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD6_WORD2_RENM7                                                      */
#define  MPU_REGD6_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                       read is not performed                                                     */
#define  MPU_REGD6_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD6_WORD3                                                         */
/*                                                MPU REGD6_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD6_WORD3_RDVALID                                                    */
#define  MPU_REGD6_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD6_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                         REGD7_WORD0                                                         */
/*                                                         REGD7_WORD1                                                         */
/*                                                         REGD7_WORD2                                                         */
/*                                               MPU REGD7_WORD2 SMCTRLM0 [3..4]                                                */
                                 /* MPU_REGD7_WORD2_SMCTRLM0                                                   */
#define  MPU_REGD7_WORD2_SMCTRLM0_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD7_WORD2_SMCTRLM0_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD7_WORD2_SMCTRLM0_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD7_WORD2_SMCTRLM0_11             3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                MPU REGD7_WORD2 PIDENM0 [5..5]                                                */
                                 /* MPU_REGD7_WORD2_PIDENM0                                                    */
#define  MPU_REGD7_WORD2_PIDENM0_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD7_WORD2_PIDENM0_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                               MPU REGD7_WORD2 SMCTRLM1 [9..10]                                               */
                                 /* MPU_REGD7_WORD2_SMCTRLM1                                                   */
#define  MPU_REGD7_WORD2_SMCTRLM1_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD7_WORD2_SMCTRLM1_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD7_WORD2_SMCTRLM1_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD7_WORD2_SMCTRLM1_11             3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                               MPU REGD7_WORD2 PIDENM1 [11..11]                                               */
                                 /* MPU_REGD7_WORD2_PIDENM1                                                    */
#define  MPU_REGD7_WORD2_PIDENM1_0               0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_REGD7_WORD2_PIDENM1_1               1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                              MPU REGD7_WORD2 SMCTRLM2 [15..16]                                               */
                                 /* MPU_REGD7_WORD2_SMCTRLM2                                                   */
#define  MPU_REGD7_WORD2_SMCTRLM2_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD7_WORD2_SMCTRLM2_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD7_WORD2_SMCTRLM2_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD7_WORD2_SMCTRLM2_11             3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                              MPU REGD7_WORD2 SMCTRLM3 [21..22]                                               */
                                 /* MPU_REGD7_WORD2_SMCTRLM3                                                   */
#define  MPU_REGD7_WORD2_SMCTRLM3_0              0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_REGD7_WORD2_SMCTRLM3_1              1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_REGD7_WORD2_SMCTRLM3_10             2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_REGD7_WORD2_SMCTRLM3_11             3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                MPU REGD7_WORD2 WENM4 [24..24]                                                */
                                 /* MPU_REGD7_WORD2_WENM4                                                      */
#define  MPU_REGD7_WORD2_WENM4_0                 0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_REGD7_WORD2_WENM4_1                 1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                MPU REGD7_WORD2 RENM4 [25..25]                                                */
                                 /* MPU_REGD7_WORD2_RENM4                                                      */
#define  MPU_REGD7_WORD2_RENM4_0                 0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                 read is not performed                                                     */
#define  MPU_REGD7_WORD2_RENM4_1                 1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                MPU REGD7_WORD2 WENM5 [26..26]                                                */
                                 /* MPU_REGD7_WORD2_WENM5                                                      */
#define  MPU_REGD7_WORD2_WENM5_0                 0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_REGD7_WORD2_WENM5_1                 1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                MPU REGD7_WORD2 RENM5 [27..27]                                                */
                                 /* MPU_REGD7_WORD2_RENM5                                                      */
#define  MPU_REGD7_WORD2_RENM5_0                 0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD7_WORD2_RENM5_1                 1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                MPU REGD7_WORD2 WENM6 [28..28]                                                */
                                 /* MPU_REGD7_WORD2_WENM6                                                      */
#define  MPU_REGD7_WORD2_WENM6_0                 0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_REGD7_WORD2_WENM6_1                 1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                MPU REGD7_WORD2 RENM6 [29..29]                                                */
                                 /* MPU_REGD7_WORD2_RENM6                                                      */
#define  MPU_REGD7_WORD2_RENM6_0                 0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_REGD7_WORD2_RENM6_1                 1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                MPU REGD7_WORD2 WENM7 [30..30]                                                */
                                 /* MPU_REGD7_WORD2_WENM7                                                      */
#define  MPU_REGD7_WORD2_WENM7_0                 0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                  write is not performed                                                    */
#define  MPU_REGD7_WORD2_WENM7_1                 1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                MPU REGD7_WORD2 RENM7 [31..31]                                                */
                                 /* MPU_REGD7_WORD2_RENM7                                                      */
#define  MPU_REGD7_WORD2_RENM7_0                 0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_REGD7_WORD2_RENM7_1                 1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                         REGD7_WORD3                                                         */
/*                                                MPU REGD7_WORD3 RDVALID [0..0]                                                */
                                 /* MPU_REGD7_WORD3_RDVALID                                                    */
#define  MPU_REGD7_WORD3_RDVALID_0               0U     /* 0 : Region descriptor is invalid                                          */
#define  MPU_REGD7_WORD3_RDVALID_1               1U     /* 1 : Region descriptor is valid                                            */


/*                                                          RGDAACC0                                                           */
/*                                                 MPU RGDAACC0 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC0_SMCTRLM0                                                      */
#define  MPU_RGDAACC0_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC0_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC0_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC0_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC0 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC0_PIDENM0                                                       */
#define  MPU_RGDAACC0_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC0_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC0 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC0_SMCTRLM1                                                      */
#define  MPU_RGDAACC0_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC0_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC0_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC0_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC0 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC0_PIDENM1                                                       */
#define  MPU_RGDAACC0_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC0_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC0 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC0_SMCTRLM2                                                      */
#define  MPU_RGDAACC0_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC0_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC0_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC0_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC0 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC0_SMCTRLM3                                                      */
#define  MPU_RGDAACC0_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC0_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC0_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC0_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC0 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC0_WENM4                                                         */
#define  MPU_RGDAACC0_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC0_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC0 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC0_RENM4                                                         */
#define  MPU_RGDAACC0_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                read is not performed                                                     */
#define  MPU_RGDAACC0_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC0 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC0_WENM5                                                         */
#define  MPU_RGDAACC0_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                   write is not performed                                                    */
#define  MPU_RGDAACC0_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC0 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC0_RENM5                                                         */
#define  MPU_RGDAACC0_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC0_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC0 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC0_WENM6                                                         */
#define  MPU_RGDAACC0_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                write is not performed                                                    */
#define  MPU_RGDAACC0_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC0 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC0_RENM6                                                         */
#define  MPU_RGDAACC0_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                read is not performed                                                     */
#define  MPU_RGDAACC0_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC0 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC0_WENM7                                                         */
#define  MPU_RGDAACC0_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC0_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC0 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC0_RENM7                                                         */
#define  MPU_RGDAACC0_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC0_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC1                                                           */
/*                                                 MPU RGDAACC1 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC1_SMCTRLM0                                                      */
#define  MPU_RGDAACC1_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC1_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC1_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC1_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC1 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC1_PIDENM0                                                       */
#define  MPU_RGDAACC1_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC1_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC1 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC1_SMCTRLM1                                                      */
#define  MPU_RGDAACC1_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC1_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC1_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC1_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC1 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC1_PIDENM1                                                       */
#define  MPU_RGDAACC1_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC1_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC1 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC1_SMCTRLM2                                                      */
#define  MPU_RGDAACC1_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC1_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC1_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC1_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC1 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC1_SMCTRLM3                                                      */
#define  MPU_RGDAACC1_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC1_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC1_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC1_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC1 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC1_WENM4                                                         */
#define  MPU_RGDAACC1_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_RGDAACC1_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC1 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC1_RENM4                                                         */
#define  MPU_RGDAACC1_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                               read is not performed                                                     */
#define  MPU_RGDAACC1_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC1 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC1_WENM5                                                         */
#define  MPU_RGDAACC1_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                               write is not performed                                                    */
#define  MPU_RGDAACC1_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC1 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC1_RENM5                                                         */
#define  MPU_RGDAACC1_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                  read is not performed                                                     */
#define  MPU_RGDAACC1_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC1 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC1_WENM6                                                         */
#define  MPU_RGDAACC1_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                   write is not performed                                                    */
#define  MPU_RGDAACC1_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC1 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC1_RENM6                                                         */
 #define MPU_RGDAACC1_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                     read is not performed                                                     */
 #define MPU_RGDAACC1_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC1 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC1_WENM7                                                         */
#define  MPU_RGDAACC1_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                               write is not performed                                                    */
#define  MPU_RGDAACC1_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC1 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC1_RENM7                                                         */
#define  MPU_RGDAACC1_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                    read is not performed                                                     */
#define  MPU_RGDAACC1_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC2                                                           */
/*                                                 MPU RGDAACC2 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC2_SMCTRLM0                                                      */
#define  MPU_RGDAACC2_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC2_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC2_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC2_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC2 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC2_PIDENM0                                                       */
#define  MPU_RGDAACC2_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC2_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC2 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC2_SMCTRLM1                                                      */
#define  MPU_RGDAACC2_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC2_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC2_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC2_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC2 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC2_PIDENM1                                                       */
#define  MPU_RGDAACC2_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC2_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC2 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC2_SMCTRLM2                                                      */
#define  MPU_RGDAACC2_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC2_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC2_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC2_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC2 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC2_SMCTRLM3                                                      */
#define  MPU_RGDAACC2_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC2_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC2_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC2_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC2 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC2_WENM4                                                         */
#define  MPU_RGDAACC2_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_RGDAACC2_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC2 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC2_RENM4                                                         */
#define  MPU_RGDAACC2_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC2_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC2 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC2_WENM5                                                         */
#define  MPU_RGDAACC2_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_RGDAACC2_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC2 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC2_RENM5                                                         */
#define  MPU_RGDAACC2_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_RGDAACC2_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC2 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC2_WENM6                                                         */
#define  MPU_RGDAACC2_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                               write is not performed                                                    */
#define  MPU_RGDAACC2_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC2 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC2_RENM6                                                         */
#define  MPU_RGDAACC2_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                               read is not performed                                                     */
#define  MPU_RGDAACC2_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC2 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC2_WENM7                                                         */
#define  MPU_RGDAACC2_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC2_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC2 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC2_RENM7                                                         */
#define  MPU_RGDAACC2_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                         read is not performed                                                     */
#define  MPU_RGDAACC2_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC3                                                           */
/*                                                 MPU RGDAACC3 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC3_SMCTRLM0                                                      */
#define  MPU_RGDAACC3_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC3_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC3_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC3_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC3 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC3_PIDENM0                                                       */
#define  MPU_RGDAACC3_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC3_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC3 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC3_SMCTRLM1                                                      */
#define  MPU_RGDAACC3_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC3_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC3_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC3_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC3 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC3_PIDENM1                                                       */
#define  MPU_RGDAACC3_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC3_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC3 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC3_SMCTRLM2                                                      */
#define  MPU_RGDAACC3_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC3_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC3_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC3_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC3 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC3_SMCTRLM3                                                      */
#define  MPU_RGDAACC3_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC3_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC3_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC3_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC3 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC3_WENM4                                                         */
#define  MPU_RGDAACC3_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_RGDAACC3_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC3 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC3_RENM4                                                         */
#define  MPU_RGDAACC3_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                         read is not performed                                                     */
#define  MPU_RGDAACC3_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC3 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC3_WENM5                                                         */
#define  MPU_RGDAACC3_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_RGDAACC3_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC3 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC3_RENM5                                                         */
#define  MPU_RGDAACC3_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_RGDAACC3_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC3 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC3_WENM6                                                         */
#define  MPU_RGDAACC3_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_RGDAACC3_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC3 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC3_RENM6                                                         */
#define  MPU_RGDAACC3_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC3_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC3 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC3_WENM7                                                         */
#define  MPU_RGDAACC3_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC3_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC3 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC3_RENM7                                                         */
#define  MPU_RGDAACC3_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC3_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC4                                                           */
/*                                                 MPU RGDAACC4 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC4_SMCTRLM0                                                      */
#define  MPU_RGDAACC4_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC4_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC4_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC4_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC4 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC4_PIDENM0                                                       */
#define  MPU_RGDAACC4_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC4_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC4 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC4_SMCTRLM1                                                      */
#define  MPU_RGDAACC4_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC4_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC4_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC4_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC4 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC4_PIDENM1                                                       */
#define  MPU_RGDAACC4_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC4_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC4 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC4_SMCTRLM2                                                      */
#define  MPU_RGDAACC4_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC4_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC4_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC4_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC4 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC4_SMCTRLM3                                                      */
#define  MPU_RGDAACC4_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC4_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC4_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC4_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC4 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC4_WENM4                                                         */
#define  MPU_RGDAACC4_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                    write is not performed                                                    */
#define  MPU_RGDAACC4_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC4 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC4_RENM4                                                         */
#define  MPU_RGDAACC4_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC4_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC4 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC4_WENM5                                                         */
#define  MPU_RGDAACC4_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC4_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC4 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC4_RENM5                                                         */
#define  MPU_RGDAACC4_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC4_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC4 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC4_WENM6                                                         */
#define  MPU_RGDAACC4_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                write is not performed                                                    */
#define  MPU_RGDAACC4_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC4 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC4_RENM6                                                         */
#define  MPU_RGDAACC4_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC4_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC4 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC4_WENM7                                                         */
#define  MPU_RGDAACC4_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_RGDAACC4_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC4 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC4_RENM7                                                         */
#define  MPU_RGDAACC4_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_RGDAACC4_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC5                                                           */
/*                                                 MPU RGDAACC5 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC5_SMCTRLM0                                                      */
#define  MPU_RGDAACC5_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC5_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC5_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC5_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC5 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC5_PIDENM0                                                       */
#define  MPU_RGDAACC5_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC5_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC5 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC5_SMCTRLM1                                                      */
#define  MPU_RGDAACC5_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC5_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC5_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC5_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC5 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC5_PIDENM1                                                       */
#define  MPU_RGDAACC5_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC5_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC5 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC5_SMCTRLM2                                                      */
#define  MPU_RGDAACC5_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC5_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC5_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC5_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC5 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC5_SMCTRLM3                                                      */
#define  MPU_RGDAACC5_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC5_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC5_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC5_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC5 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC5_WENM4                                                         */
#define  MPU_RGDAACC5_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_RGDAACC5_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC5 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC5_RENM4                                                         */
 #define MPU_RGDAACC5_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                       read is not performed                                                     */
 #define MPU_RGDAACC5_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC5 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC5_WENM5                                                         */
#define  MPU_RGDAACC5_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_RGDAACC5_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC5 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC5_RENM5                                                         */
#define  MPU_RGDAACC5_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                read is not performed                                                     */
#define  MPU_RGDAACC5_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC5 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC5_WENM6                                                         */
#define  MPU_RGDAACC5_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_RGDAACC5_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC5 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC5_RENM6                                                         */
#define  MPU_RGDAACC5_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                     read is not performed                                                     */
#define  MPU_RGDAACC5_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC5 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC5_WENM7                                                         */
#define  MPU_RGDAACC5_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                     write is not performed                                                    */
#define  MPU_RGDAACC5_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC5 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC5_RENM7                                                         */
#define  MPU_RGDAACC5_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                  read is not performed                                                     */
#define  MPU_RGDAACC5_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC6                                                           */
/*                                                 MPU RGDAACC6 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC6_SMCTRLM0                                                      */
#define  MPU_RGDAACC6_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC6_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC6_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC6_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC6 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC6_PIDENM0                                                       */
#define  MPU_RGDAACC6_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC6_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC6 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC6_SMCTRLM1                                                      */
#define  MPU_RGDAACC6_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC6_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC6_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC6_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC6 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC6_PIDENM1                                                       */
#define  MPU_RGDAACC6_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC6_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC6 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC6_SMCTRLM2                                                      */
#define  MPU_RGDAACC6_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC6_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC6_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC6_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC6 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC6_SMCTRLM3                                                      */
#define  MPU_RGDAACC6_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC6_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC6_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC6_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC6 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC6_WENM4                                                         */
#define  MPU_RGDAACC6_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC6_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC6 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC6_RENM4                                                         */
#define  MPU_RGDAACC6_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                        read is not performed                                                     */
#define  MPU_RGDAACC6_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC6 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC6_WENM5                                                         */
#define  MPU_RGDAACC6_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                    write is not performed                                                    */
#define  MPU_RGDAACC6_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC6 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC6_RENM5                                                         */
#define  MPU_RGDAACC6_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC6_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC6 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC6_WENM6                                                         */
#define  MPU_RGDAACC6_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC6_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC6 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC6_RENM6                                                         */
#define  MPU_RGDAACC6_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC6_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC6 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC6_WENM7                                                         */
#define  MPU_RGDAACC6_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                write is not performed                                                    */
#define  MPU_RGDAACC6_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC6 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC6_RENM7                                                         */
#define  MPU_RGDAACC6_RENM7_0                    0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                    read is not performed                                                     */
#define  MPU_RGDAACC6_RENM7_1                    1U     /* 1 : Bus master 7 reads allowed                                            */


/*                                                          RGDAACC7                                                           */
/*                                                 MPU RGDAACC7 SMCTRLM0 [3..4]                                                 */
                                 /* MPU_RGDAACC7_SMCTRLM0                                                      */
#define  MPU_RGDAACC7_SMCTRLM0_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC7_SMCTRLM0_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC7_SMCTRLM0_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC7_SMCTRLM0_11                3U     /* 11 : Same as User mode defined in M0UM                                    */


/*                                                 MPU RGDAACC7 PIDENM0 [5..5]                                                  */
                                 /* MPU_RGDAACC7_PIDENM0                                                       */
#define  MPU_RGDAACC7_PIDENM0_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC7_PIDENM0_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC7 SMCTRLM1 [9..10]                                                 */
                                 /* MPU_RGDAACC7_SMCTRLM1                                                      */
#define  MPU_RGDAACC7_SMCTRLM1_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC7_SMCTRLM1_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC7_SMCTRLM1_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC7_SMCTRLM1_11                3U     /* 11 : Same as User mode defined in M1UM                                    */


/*                                                MPU RGDAACC7 PIDENM1 [11..11]                                                 */
                                 /* MPU_RGDAACC7_PIDENM1                                                       */
#define  MPU_RGDAACC7_PIDENM1_0                  0U     /* 0 : Do not include the process identifier in the evaluation               */
#define  MPU_RGDAACC7_PIDENM1_1                  1U     /* 1 : Include the process identifier and mask (RGDn.RGDAACC) in
                                                     the region hit evaluation                                                 */


/*                                                MPU RGDAACC7 SMCTRLM2 [15..16]                                                */
                                 /* MPU_RGDAACC7_SMCTRLM2                                                      */
#define  MPU_RGDAACC7_SMCTRLM2_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC7_SMCTRLM2_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC7_SMCTRLM2_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC7_SMCTRLM2_11                3U     /* 11 : Same as User mode defined in M2UM                                    */


/*                                                MPU RGDAACC7 SMCTRLM3 [21..22]                                                */
                                 /* MPU_RGDAACC7_SMCTRLM3                                                      */
#define  MPU_RGDAACC7_SMCTRLM3_0                 0U     /* 0 : r/w/x; readU write and execute allowed                                */
#define  MPU_RGDAACC7_SMCTRLM3_1                 1U     /* 1 : r/x; read and execute allowedU but no write                           */
#define  MPU_RGDAACC7_SMCTRLM3_10                2U     /* 10 : r/w; read and write allowedU but no execute                          */
#define  MPU_RGDAACC7_SMCTRLM3_11                3U     /* 11 : Same as User mode defined in M3UM                                    */


/*                                                 MPU RGDAACC7 WENM4 [24..24]                                                  */
                                 /* MPU_RGDAACC7_WENM4                                                         */
#define  MPU_RGDAACC7_WENM4_0                    0U     /* 0 : Bus master 4 writes terminate with an access error and the
                                                        write is not performed                                                    */
#define  MPU_RGDAACC7_WENM4_1                    1U     /* 1 : Bus master 4 writes allowed                                           */


/*                                                 MPU RGDAACC7 RENM4 [25..25]                                                  */
                                 /* MPU_RGDAACC7_RENM4                                                         */
#define  MPU_RGDAACC7_RENM4_0                    0U     /* 0 : Bus master 4 reads terminate with an access error and the
                                                       read is not performed                                                     */
#define  MPU_RGDAACC7_RENM4_1                    1U     /* 1 : Bus master 4 reads allowed                                            */


/*                                                 MPU RGDAACC7 WENM5 [26..26]                                                  */
                                 /* MPU_RGDAACC7_WENM5                                                         */
#define  MPU_RGDAACC7_WENM5_0                    0U     /* 0 : Bus master 5 writes terminate with an access error and the
                                                         write is not performed                                                    */
#define  MPU_RGDAACC7_WENM5_1                    1U     /* 1 : Bus master 5 writes allowed                                           */


/*                                                 MPU RGDAACC7 RENM5 [27..27]                                                  */
                                 /* MPU_RGDAACC7_RENM5                                                         */
#define  MPU_RGDAACC7_RENM5_0                    0U     /* 0 : Bus master 5 reads terminate with an access error and the
                                                   read is not performed                                                     */
#define  MPU_RGDAACC7_RENM5_1                    1U     /* 1 : Bus master 5 reads allowed                                            */


/*                                                 MPU RGDAACC7 WENM6 [28..28]                                                  */
                                 /* MPU_RGDAACC7_WENM6                                                         */
#define  MPU_RGDAACC7_WENM6_0                    0U     /* 0 : Bus master 6 writes terminate with an access error and the
                                                      write is not performed                                                    */
#define  MPU_RGDAACC7_WENM6_1                    1U     /* 1 : Bus master 6 writes allowed                                           */


/*                                                 MPU RGDAACC7 RENM6 [29..29]                                                  */
                                 /* MPU_RGDAACC7_RENM6                                                         */
#define  MPU_RGDAACC7_RENM6_0                    0U     /* 0 : Bus master 6 reads terminate with an access error and the
                                                      read is not performed                                                     */
#define  MPU_RGDAACC7_RENM6_1                    1U     /* 1 : Bus master 6 reads allowed                                            */


/*                                                 MPU RGDAACC7 WENM7 [30..30]                                                  */
                                 /* MPU_RGDAACC7_WENM7                                                         */
#define  MPU_RGDAACC7_WENM7_0                    0U     /* 0 : Bus master 7 writes terminate with an access error and the
                                                       write is not performed                                                    */
#define  MPU_RGDAACC7_WENM7_1                    1U     /* 1 : Bus master 7 writes allowed                                           */


/*                                                 MPU RGDAACC7 RENM7 [31..31]                                                  */
                                 /* MPU_RGDAACC7_RENM7                                                         */
#define MPU_RGDAACC7_RENM7_0                     0U     /* 0 : Bus master 7 reads terminate with an access error and the
                                                 read is not performed                                                     */
#define MP_RGDAACC7_RENM7_1                     1U     /* 1 : Bus master 7 reads allowed                                            */




/*                                                                                                                             */
/*                                                            EREP                                                             */
/*                                                                                                                             */

/*                                                            CFG0                                                             */
/*                                                EREP CFG0 UINTNENM1 [26..26]                                                 */
                                 /* EREP_CFG0_UINTNENM1                                                       */
#define  EREP_CFG0_UINTNENM1_0                  0U     /* 0 : Interrupt notification of Memory 1 non-correctable error
                                                      events is disabled.                                                       */
#define  EREP_CFG0_UINTNENM1_1                  1U     /* 1 : Interrupt notification of Memory 1 non-correctable error
                                                        events is enabled.                                                        */


/*                                                EREP CFG0 SCINTNENM1 [27..27]                                                */
                                 /* EREP_CFG0_SCINTNENM1                                                      */
#define  EREP_CFG0_SCINTNENM1_0                 0U     /* 0 : Interrupt notification of Memory 1 single-bit correction
                                                        events is disabled.                                                       */
#define  EREP_CFG0_SCINTNENM1_1                 1U     /* 1 : Interrupt notification of Memory 1 single-bit correction
                                                        events is enabled.                                                        */


/*                                                EREP CFG0 UINTNENM0 [30..30]                                                 */
                                 /* EREP_CFG0_UINTNENM0                                                       */
#define  EREP_CFG0_UINTNENM0_0                  0U     /* 0 : Interrupt notification of Memory 0 non-correctable error
                                                      events is disabled.                                                       */
#define  EREP_CFG0_UINTNENM0_1                  1U     /* 1 : Interrupt notification of Memory 0 non-correctable error
                                                       events is enabled.                                                        */


/*                                                EREP CFG0 SCINTNENM0 [31..31]                                                */
                                 /* EREP_CFG0_SCINTNENM0                                                      */
#define  EREP_CFG0_SCINTNENM0_0                 0U     /* 0 : Interrupt notification of Memory 0 single-bit correction
                                                        events is disabled.                                                       */
#define  EREP_CFG0_SCINTNENM0_1                 1U     /* 1 : Interrupt notification of Memory 0 single-bit correction
                                                       events is enabled.                                                        */


/*                                                             STS0                                                             */
/*                                                  EREP STS0 UEFLGM1 [26..26]                                                  */
                                 /* EREP_SRS0_UEFLGM1                                                          */
#define  EREP_SRS0_UEFLGM1_0                     0U     /* 0 : No non-correctable error event on Memory 1 detected                   */
#define  EREP_SRS0_UEFLGM1_1                     1U     /* 1 : Non-correctable error event on Memory 1 detected                      */


/*                                                 EREP STS0 SBCFLGM1 [27..27]                                                  */
                                 /* EREP_SRS0_SBCFLGM1                                                         */
#define  EREP_SRS0_SBCFLGM1_0                    0U     /* 0 : No single-bit correction event on Memory 1 detected                   */
#define  EREP_SRS0_SBCFLGM1_1                    1U     /* 1 : Single-bit correction event on Memory 1 detected                      */


/*                                                  EREP STS0 UEFLGM0 [30..30]                                                  */
                                 /* EREP_SRS0_UEFLGM0                                                          */
#define  EREP_SRS0_UEFLGM0_0                     0U     /* 0 : No non-correctable error event on Memory 0 detected                   */
#define  EREP_SRS0_UEFLGM0_1                     1U     /* 1 : Non-correctable error event on Memory 0 detected                      */


/*                                                 EREP STS0 SBCFLGM0 [31..31]                                                  */
                                 /* EREP_SRS0_SBCFLGM0                                                         */
#define  EREP_SRS0_SBCFLGM0_0                    0U     /* 0 : No single-bit correction event on Memory 0 detected                   */
#define  EREP_SRS0_SBCFLGM0_1                    1U     /* 1 : Single-bit correction event on Memory 0 detected                      */


/* ========================================================  EADDR0  ========================================================= */
/* ========================================================  EADDR1  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           EINJ                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
/*                                                   EINJ CFG GEINJEN [0..0]                                                   */
                                  /* EINJ_CFG_GEINJEN                                                          */
#define  EINJ_CFG_GEINJEN_0                     0U     /* 0 : Disabled                                                              */
#define  EINJ_CFG_GEINJEN_1                     1U     /* 1 : Enabled                                                               */


/*                                                            CHEN                                                             */
/*                                                EINJ CHEN EINJENCH1 [30..30]                                                 */
                                  /* EINJ_CHEN_EINJENCH1                                                       */
#define  EINJ_CHEN_EINJENCH1_0                  0U     /* 0 : Error injection is disabled on Error Injection Channel 1              */
#define  EINJ_CHEN_EINJENCH1_1                  1U     /* 1 : Error injection is enabled on Error Injection Channel 1               */


/*                                                EINJ CHEN EINJENCH0 [31..31]                                                 */
                                  /* EINJ_CHEN_EINJENCH0                                                       */
#define  EINJ_CHEN_EINJENCH0_0                  0U     /* 0 : Error injection is disabled on Error Injection Channel 0              */
#define  EINJ_CHEN_EINJENCH0_1                  1U     /* 1 : Error injection is enabled on Error Injection Channel 0               */


/* ======================================================  CHD0_WORD0  ======================================================= */
/* ======================================================  CHD0_WORD1  ======================================================= */
/* ======================================================  CHD1_WORD0  ======================================================= */
/* ======================================================  CHD1_WORD1  ======================================================= */


/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  STS  ========================================================== */
/* ===============================================  FLASH STS PROVFLG [4..4]  ================================================ */
                                  /* FLASH_STS_PROVFLG                                                         */
#define  FLASH_STS_PROVFLG_0                    0U     /* 0 : No protection violation detected                                      */
#define  FLASH_STS_PROVFLG_1                    1U     /* 1 : Protection violation detected                                         */


/* ===============================================  FLASH STS ACCEFLG [5..5]  ================================================ */
                                  /* FLASH_STS_ACCEFLG                                                         */
#define  FLASH_STS_ACCEFLG_0                    0U     /* 0 : No access error detected                                              */
#define  FLASH_STS_ACCEFLG_1                    1U     /* 1 : Access error detected                                                 */


/* ===============================================  FLASH STS COLEFLG [6..6]  ================================================ */
                                  /* FLASH_STS_COLEFLG                                                         */
#define  FLASH_STS_COLEFLG_0                    0U     /* 0 : No collision error detected                                           */
#define  FLASH_STS_COLEFLG_1                    1U     /* 1 : Collision error detected                                              */


/* ==========================================================  CFG  ========================================================== */
/* ==============================================  FLASH CFG ERACMDSUS [4..4]  =============================================== */
                                  /* FLASH_CFG_ERACMDSUS                                                       */
#define  FLASH_CFG_ERACMDSUS_0                  0U     /* 0 : No suspend requested                                                  */
#define  FLASH_CFG_ERACMDSUS_1                  1U     /* 1 : Suspend the current Erase Flash Sector command execution              */


/* ===============================================  FLASH CFG ERAABREQ [5..5]  =============================================== */
                                  /* FLASH_CFG_ERAABREQ                                                        */
#define  FLASH_CFG_ERAABREQ_0                   0U     /* 0 : No request or request complete                                        */


/* ===============================================  FLASH CFG RCOLEIEN [6..6]  =============================================== */
                                  /* FLASH_CFG_RCOLEIEN                                                        */
#define  FLASH_CFG_RCOLEIEN_0                   0U     /* 0 : Read collision error interrupt disabled                               */
#define  FLASH_CFG_RCOLEIEN_1                   1U     /* 1 : Read collision error interrupt enabled. An interrupt request
                                                     is generated whenever an FTFC read collision error is detected
                                                     (see the description of FSTAT[RDCOLERR]).                                 */

/* ===============================================  FLASH CFG CMDCIEN [7..7]  ================================================ */
                                  /* FLASH_CFG_CMDCIEN                                                         */
#define  FLASH_CFG_CMDCIEN_0                    0U     /* 0 : Command complete interrupt disabled                                   */
#define  FLASH_CFG_CMDCIEN_1                    1U     /* 1 : Command complete interrupt enabled. An interrupt request
                                                     is generated whenever the STS[OCIFLG] flag is set.                        */


/* ==========================================================  SEC  ========================================================== */
/* ===============================================  FLASH SEC SECFLG [0..1]  ================================================ */
                                  /* FLASH_SEC_SECFLG                                                         */
#define  FLASH_SEC_SECFLG_10                  2U     /* 10 : MCU security status is unsecure (The standard shipping
                                                         condition of the FTFC is unsecure.)                                       */


/* ===============================================  FLASH SEC FCACCEN [2..3]  ================================================ */
                                  /* FLASH_SEC_FCACCEN                                                         */
#define  FLASH_SEC_FCACCEN_00                   0U     /* 00 : Factory access granted                                               */
#define  FLASH_SEC_FCACCEN_11                   3U     /* 11 : Factory access granted                                               */


/* ================================================  FLASH SEC MERAEN [4..5]  ================================================ */
                                  /* FLASH_SEC_MERAEN                                                          */
#define  FLASH_SEC_MERAEN_00                    0U     /* 00 : Mass erase is enabled                                                */
#define  FLASH_SEC_MERAEN_01                    1U     /* 01 : Mass erase is enabled                                                */
#define  FLASH_SEC_MERAEN_11                    3U     /* 11 : Mass erase is enabled                                                */


/* ==============================================  FLASH SEC BKEYACCEN [6..7]  =============================================== */
                                  /* FLASH_SEC_BKEYACCEN                                                       */
#define  FLASH_SEC_BKEYACCEN_00                 0U     /* 00 : Backdoor key access disabled                                         */
#define  FLASH_SEC_BKEYACCEN_01                 1U     /* 01 : Backdoor key access disabled (preferred KEYEN state to
                                                     disable backdoor key access)                                              */
#define  FLASH_SEC_BKEYACCEN_10                 2U     /* 10 : Backdoor key access enabled                                          */
#define  FLASH_SEC_BKEYACCEN_11                 3U     /* 11 : Backdoor key access disabled                                         */


/* ==========================================================  NOPT  ========================================================== */
/* =======================================================  CCMDDATA3  ======================================================= */
/* =======================================================  CCMDDATA2  ======================================================= */
/* =======================================================  CCMDDATA1  ======================================================= */
/* =======================================================  CCMDDATA0  ======================================================= */
/* =======================================================  CCMDDATA7  ======================================================= */
/* =======================================================  CCMDDATA6  ======================================================= */
/* =======================================================  CCMDDATA5  ======================================================= */
/* =======================================================  CCMDDATA4  ======================================================= */
/* =======================================================  CCMDDATAB  ======================================================= */
/* =======================================================  CCMDDATAA  ======================================================= */
/* =======================================================  CCMDDATA9  ======================================================= */
/* =======================================================  CCMDDATA8  ======================================================= */
/* ========================================================  PFPRO3  ========================================================= */
/* ========================================================  PFPRO2  ========================================================= */
/* ========================================================  PFPRO1  ========================================================= */
/* ========================================================  PFPRO0  ========================================================= */
/* ========================================================  EEPRO  ========================================================= */
/* ========================================================  DFPRO  ======================================================== */
/* =============================================  FLASH DFPRO DFPRO [0..7]  ============================================== */
                                 /* FLASH_DFLASHPRO_DFLASHPRO                                                    */
#define  FLASH_DFLASHPRO_DFLASHPRO_00000000         0U     /* 00000000 : Data Flash region is protected                                 */
#define  FLASH_DFLASHPRO_DFLASHPRO_00000001         1U     /* 00000001 : Data Flash region is not protected                             */


/* ========================================================  CSECSTS  ======================================================== */
/* ========================================================  ESTS  ========================================================= */
/* ==============================================  FLASH ESTS DBFIFLG [1..1]  ============================================== */
                                 /* FLASH_ESTS_DBFIFLG                                                      */
#define  FLASH_ESTS_DBFIFLG_0                 0U     /* 0 : Double bit fault not detected during a valid flash read
                                                        access from the platform flash controller                                 */
#define  FLASH_ESTS_DBFIFLG_1                 1U     /* 1 : Double bit fault detected (or FERCNFG[FDFD] is set) during
                                                       a valid flash read access from the platform flash controller              */


/* ========================================================  ECFG  ========================================================= */
/* ==============================================  FLASH ECFG DBFIEN [1..1]  =============================================== */
                                 /* FLASH_ECFG_DBFIEN                                                       */
#define  FLASH_ECFG_DBFIEN_0                  0U     /* 0 : Double bit fault detect interrupt disabled                            */
#define  FLASH_ECFG_DBFIEN_1                  1U     /* 1 : Double bit fault detect interrupt enabled. An interrupt
                                                     request is generated whenever the FERSTAT[DFDIF] flag is
                                                     set.                                                                      */


/* =============================================  FLASH ECFG EDBFINTD [5..5]  ============================================== */
                                 /* FLASH_ECFG_EDBFINTD                                                     */
#define  FLASH_ECFG_EDBFINTD_0                0U     /* 0 : FERSTAT[DFDIF] sets only if a double bit fault is detected
                                                        during read access from the platform flash controller                     */
#define  FLASH_ECFG_EDBFINTD_1                1U     /* 1 : FERSTAT[DFDIF] sets during any valid flash read access from
                                                       the platform flash controller. An interrupt request is
                                                     generated if the DFDIE bit is set.                                        */




/* =========================================================================================================================== */
/* ================                                          DMACHM                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CFG  ========================================================= */
/* =============================================  DMACHM CFG PRDTREN [6..6]  ============================================== */
                                 /* DMACHM_CFG_PRDTREN                                                     */
#define  DMACHM_CFG_PRDTREN_0                0U     /* 0 : Triggering is disabled. If triggering is disabled and ENBL
                                                      is setU the DMA Channel will simply route the specified
                                                     source to the DMA channel. (Normal mode)                                  */
#define  DMACHM_CFG_PRDTREN_1                1U     /* 1 : Triggering is enabled. If triggering is enabled and ENBL
                                                        is setU the DMAMUX is in Periodic Trigger mode.                           */


/* ===============================================  DMACHM CFG CHEN [7..7]  =============================================== */
                                 /* DMACHM_CFG_CHEN                                                        */
#define  DMACHM_CFG_CHEN_0                   0U     /* 0 : DMA channel is disabled. This mode is primarily used during
                                                        configuration of the DMAMux. The DMA has separate channel
                                                     enables/disablesU which should be used to disable or reconfigure
                                                     a DMA channel.                                                            */
#define  DMACHM_CFG_CHEN_1                   1U     /* 1 : DMA channel is enabled                                                */




/* =========================================================================================================================== */
/* ================                                           CAN                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  MCFG  ========================================================== */
/* ================================================  CAN MCFG IDFFMT [8..9]  ================================================ */
                                  /* CAN_MCFG_IDFFMT                                                          */
#define  CAN_MCFG_IDFFMT_00                    0U     /* 00 : Format A: One full ID (standard and extended) per ID Filter
                                                     Table element.                                                            */
#define  CAN_MCFG_IDFFMT_01                    1U     /* 01 : Format B: Two full standard IDs or two partial 14-bit (standard
                                                     and extended) IDs per ID Filter Table element.                            */
#define  CAN_MCFG_IDFFMT_10                    2U     /* 10 : Format C: Four partial 8-bit Standard IDs per ID Filter
                                                     Table element.                                                            */
#define  CAN_MCFG_IDFFMT_11                    3U     /* 11 : Format D: All frames rejected.                                       */


/* ==============================================  CAN MCFG CANFDEN [11..11]  =============================================== */
                                  /* CAN_MCFG_CANFDEN                                                         */
#define  CAN_MCFG_CANFDEN_1                    1U     /* 1 : CAN FD is enabled. CAN is able to receive and transmit
                                                     messages in both CAN FD and CAN 2.0 formats.                              */
#define  CAN_MCFG_CANFDEN_0                    0U     /* 0 : CAN FD is disabled. CAN is able to receive and transmit
                                                     messages in CAN 2.0 format.                                               */


/* ================================================  CAN MCFG TAEN [12..12]  ================================================ */
                                  /* CAN_MCFG_TAEN                                                            */
#define  CAN_MCFG_TAEN_0                       0U     /* 0 : Abort disabled.                                                       */
#define  CAN_MCFG_TAEN_1                       1U     /* 1 : Abort enabled.                                                        */


/* ===============================================  CAN MCFG LPRIEN [13..13]  =============================================== */
                                  /* CAN_MCFG_LPRIEN                                                          */
#define  CAN_MCFG_LPRIEN_0                     0U     /* 0 : Local Priority disabled.                                              */
#define  CAN_MCFG_LPRIEN_1                     1U     /* 1 : Local Priority enabled.                                               */


/* ================================================  CAN MCFG PNEN [14..14]  ================================================ */
                                  /* CAN_MCFG_PNEN                                                            */
#define  CAN_MCFG_PNEN_0                       0U     /* 0 : Pretended Networking mode is disabled.                                */
#define  CAN_MCFG_PNEN_1                       1U     /* 1 : Pretended Networking mode is enabled.                                 */


/* =================================                CAN MCFG DMAEN [15..15]                                                   */
                                  /* CAN_MCFG_DMAEN                                                           */
#define  CAN_MCFG_DMAEN_0                      0U     /* 0 : DMA feature for RX FIFO disabled.                                     */
#define  CAN_MCFG_DMAEN_1                      1U     /* 1 : DMA feature for RX FIFO enabled.                                      */


/* ==============================================  CAN MCFG IRXMQEN [16..16]  =============================================== */
                                  /* CAN_MCFG_IRXMQEN                                                         */
#define  CAN_MCFG_IRXMQEN_0                    0U     /* 0 : Individual Rx masking and queue feature are disabled. For
                                                        backward compatibility with legacy applicationsU the reading
                                                     of C/S word locks the MB even if it is EMPTY.                             */
#define  CAN_MCFG_IRXMQEN_1                    1U     /* 1 : Individual Rx masking and queue feature are enabled.                  */


/* ================================================  CAN MCFG SRD [17..17]  ================================================= */
                                  /* CAN_MCFG_SRD                                                             */
#define  CAN_MCFG_SRD_0                        0U     /* 0 : Self reception enabled.                                               */
#define  CAN_MCFG_SRD_1                        1U     /* 1 : Self reception disabled.                                              */


/* ================================================  CAN MCFG LPM [20..20]  ================================================= */
                                  /* CAN_MCFG_LPM                                                             */
#define  CAN_MCFG_LPM_0                        0U     /* 0 : CAN is not in a low-power mode.                                   */
#define  CAN_MCFG_LPM_1                        1U     /* 1 : CAN is in a low-power mode.                                       */


/* ================================================  CAN MCFG WIEN [21..21]  ================================================ */
                                  /* CAN_MCFG_WIEN                                                            */
#define  CAN_MCFG_WIEN_0                       0U     /* 0 : TWRNINT and RWRNINT bits are zeroU independent of the values
                                                         in the error counters.                                                    */
#define  CAN_MCFG_WIEN_1                       1U     /* 1 : TWRNINT and RWRNINT bits are set when the respective error
                                                        counter transitions from less than 96 to greater than or
                                                     equal to 96.                                                              */


/* ===============================================  CAN MCFG FRZFLG [24..24]  =============================================== */
                                  /* CAN_MCFG_FRZFLG                                                          */
#define  CAN_MCFG_FRZFLG_0                     0U     /* 0 : CAN not in Freeze modeU prescaler running.                        */
#define  CAN_MCFG_FRZFLG_1                     1U     /* 1 : CAN in Freeze modeU prescaler stopped.                            */


/* ===============================================  CAN MCFG CANRST [25..25]  =============================================== */
                                  /* CAN_MCFG_CANRST                                                          */
#define  CAN_MCFG_CANRST_0                     0U     /* 0 : No reset request.                                                     */
#define  CAN_MCFG_CANRST_1                     1U     /* 1 : Resets the registers affected by soft reset.                          */


/* ===============================================  CAN MCFG NRDY [27..27]  ================================================ */
                                  /* CAN_MCFG_NRDY                                                           */
#define  CAN_MCFG_NRDY_0                      0U     /* 0 : CAN module is either in Normal modeU Listen-Only mode
                                                     or Loop-Back mode.                                                        */


/* ================================================  CAN MCFG EFRZ [28..28]  ================================================ */
                                  /* CAN_MCFG_EFRZ                                                            */
#define  CAN_MCFG_EFRZ_0                       0U     /* 0 : No Freeze mode request.                                               */
#define  CAN_MCFG_EFRZ_1                       1U     /* 1 : Enters Freeze mode if the FRZ bit is asserted.                        */


/* ===============================================  CAN MCFG FIFOEN [29..29]  =============================================== */
                                  /* CAN_MCFG_FIFOEN                                                          */
#define  CAN_MCFG_FIFOEN_0                     0U     /* 0 : Rx FIFO not enabled.                                                  */
#define  CAN_MCFG_FIFOEN_1                     1U     /* 1 : Rx FIFO enabled.                                                      */


/* ===============================================  CAN MCFG FRZEN [30..30]  ================================================ */
                                  /* CAN_MCFG_FRZEN                                                           */
#define  CAN_MCFG_FRZEN_0                      0U     /* 0 : Not enabled to enter Freeze mode.                                     */
#define  CAN_MCFG_FRZEN_1                      1U     /* 1 : Enabled to enter Freeze mode.                                         */


/* ================================================  CAN MCFG CMD [31..31]  ================================================= */
                                  /* CAN_MCFG_CMD                                                             */
#define  CAN_MCFG_CMD_0                        0U     /* 0 : Enable the CAN module.                                            */
#define  CAN_MCFG_CMD_1                        1U     /* 1 : Disable the CAN module.                                           */


/* =========================================================  CTRL1  ========================================================= */
/* ================================================  CAN CTRL1 PTS [0..0]  ================================================= */
                                  /* CAN_CTRL1_PTS                                                           */
#define  CAN_CTRL1_PTS_0                      0U     /* 0 : the length of the propagation segment in the bit time is 0.    */
#define  CAN_CTRL1_PTS_1                      1U     /* 1 : the length of the propagation segment in the bit time is 1.    */
#define  CAN_CTRL1_PTS_2                      2U     /* 2 : the length of the propagation segment in the bit time is 2.    */
#define  CAN_CTRL1_PTS_3                      3U     /* 4 : the length of the propagation segment in the bit time is 3.    */
#define  CAN_CTRL1_PTS_4                      4U     /* 4 : the length of the propagation segment in the bit time is 4.    */
#define  CAN_CTRL1_PTS_5                      5U     /* 5 : the length of the propagation segment in the bit time is 5.    */
#define  CAN_CTRL1_PTS_6                      6U     /* 6 : the length of the propagation segment in the bit time is 6.    */
#define  CAN_CTRL1_PTS_7                      7U     /* 7 : the length of the propagation segment in the bit time is 7.    */

/* ================================================  CAN CTRL1 LOEN [3..3]  ================================================= */
                                  /* CAN_CTRL1_LOEN                                                           */
#define  CAN_CTRL1_LOEN_0                      0U     /* 0 : Listen-Only mode is deactivated.                                      */
#define  CAN_CTRL1_LOEN_1                      1U     /* 1 : CAN module operates in Listen-Only mode.                          */


/* ================================================  CAN CTRL1 TXLB [4..4]  ================================================= */
                                  /* CAN_CTRL1_TXLB                                                           */
#define  CAN_CTRL1_TXLB_0                      0U     /* 0 : Buffer with highest priority is transmitted first.                    */
#define  CAN_CTRL1_TXLB_1                      1U     /* 1 : Lowest number buffer is transmitted first.                            */


/* ===============================================  CAN CTRL1 TMRSYN [5..5]  ================================================ */
                                  /* CAN_CTRL1_TMRSYN                                                         */
#define  CAN_CTRL1_TMRSYN_0                    0U     /* 0 : Timer Sync feature disabled                                           */
#define  CAN_CTRL1_TMRSYN_1                    1U     /* 1 : Timer Sync feature enabled                                            */


/* ================================================  CAN CTRL1 BORD [6..6]  ================================================= */
                                  /* CAN_CTRL1_BORD                                                           */
#define  CAN_CTRL1_BORD_0                      0U     /* 0 : Automatic recovering from Bus Off state enabled.                      */
#define  CAN_CTRL1_BORD_1                      1U     /* 1 : Automatic recovering from Bus Off state disabled.                     */


/* ================================================  CAN CTRL1 TSEN [7..7]  ================================================= */
                                  /* CAN_CTRL1_TSEN                                                           */
#define  CAN_CTRL1_TSEN_0                      0U     /* 0 : Just one sample is used to determine the bit value.                   */
#define  CAN_CTRL1_TSEN_1                      1U     /* 1 : Three samples are used to determine the value of the received
                                                     bit: the regular one (sample point) and 2 preceding samples;
                                                     a majority rule is used.                                                  */


/* ==============================================  CAN CTRL1 RXWIEN [10..10]  =============================================== */
                                  /* CAN_CTRL1_RXWIEN                                                         */
#define  CAN_CTRL1_RXWIEN_0                    0U     /* 0 : Rx Warning Interrupt disabled.                                        */
#define  CAN_CTRL1_RXWIEN_1                    1U     /* 1 : Rx Warning Interrupt enabled.                                         */


/* ==============================================  CAN CTRL1 TXWIEN [11..11]  =============================================== */
                                  /* CAN_CTRL1_TXWIEN                                                         */
#define  CAN_CTRL1_TXWIEN_0                    0U     /* 0 : Tx Warning Interrupt disabled.                                        */
#define  CAN_CTRL1_TXWIEN_1                    1U     /* 1 : Tx Warning Interrupt enabled.                                         */


/* ===============================================  CAN CTRL1 LBEN [12..12]  ================================================ */
                                  /* CAN_CTRL1_LBEN                                                           */
#define  CAN_CTRL1_LBEN_0                      0U     /* 0 : Loop Back disabled.                                                   */
#define  CAN_CTRL1_LBEN_1                      1U     /* 1 : Loop Back enabled.                                                    */


/* ==============================================  CAN CTRL1 CLKSEL [13..13]  =============================================== */
                                  /* CAN_CTRL1_CLKSEL                                                         */
#define  CAN_CTRL1_CLKSEL_0                    0U     /* 0 : The CAN engine clock source is the oscillator clock. Under
                                                         this conditionU the oscillator clock frequency must be
                                                     lower than the bus clock.                                                 */
#define  CAN_CTRL1_CLKSEL_1                    1U     /* 1 : The CAN engine clock source is the peripheral clock.                  */


/* ===============================================  CAN CTRL1 ERRIEN [14..14]  ================================================ */
                                  /* CAN_CTRL1_ERRIEN                                                           */
#define  CAN_CTRL1_ERRIEN_0                      0U     /* 0 : Error interrupt disabled.                                             */
#define  CAN_CTRL1_ERRIEN_1                      1U     /* 1 : Error interrupt enabled.                                              */


/* ===============================================  CAN CTRL1 BOIEN [15..15]  =============================================== */
                                  /* CAN_CTRL1_BOIEN                                                          */
#define  CAN_CTRL1_BOIEN_0                     0U     /* 0 : Bus Off interrupt disabled.                                           */
#define  CAN_CTRL1_BOIEN_1                     1U     /* 1 : Bus Off interrupt enabled.                                            */

/* ===============================================  CAN CTRL1 PBS2 [16..18]  =============================================== */
                                  /* CAN_CTRL1_PBS2                                                          */
#define  CAN_CTRL1_PBS2_1                     1U     /* 1 : the length of phase segment 2 in the bit time is 1.      */
#define  CAN_CTRL1_PBS2_2                     2U     /* 2 : the length of phase segment 2 in the bit time is 2.      */
#define  CAN_CTRL1_PBS2_3                     3U     /* 3 : the length of phase segment 2 in the bit time is 3.      */
#define  CAN_CTRL1_PBS2_4                     4U     /* 4 : the length of phase segment 2 in the bit time is 4.      */
#define  CAN_CTRL1_PBS2_5                     5U     /* 5 : the length of phase segment 2 in the bit time is 5.      */
#define  CAN_CTRL1_PBS2_6                     6U     /* 6 : the length of phase segment 2 in the bit time is 6.      */
#define  CAN_CTRL1_PBS2_7                     7U     /* 7 : the length of phase segment 2 in the bit time is 7.      */

/* ===============================================  CAN CTRL1 PBS1 [19..21]  =============================================== */
                                  /* CAN_CTRL1_PBS1                                                          */
#define  CAN_CTRL1_PBS1_0                     0U     /* 0 : the length of phase segment 1 in the bit time is 0.      */
#define  CAN_CTRL1_PBS1_1                     1U     /* 1 : the length of phase segment 1 in the bit time is 1.      */
#define  CAN_CTRL1_PBS1_2                     2U     /* 2 : the length of phase segment 1 in the bit time is 2.      */
#define  CAN_CTRL1_PBS1_3                     3U     /* 3 : the length of phase segment 1 in the bit time is 3.      */
#define  CAN_CTRL1_PBS1_4                     4U     /* 4 : the length of phase segment 1 in the bit time is 4.      */
#define  CAN_CTRL1_PBS1_5                     5U     /* 5 : the length of phase segment 1 in the bit time is 5.      */
#define  CAN_CTRL1_PBS1_6                     6U     /* 6 : the length of phase segment 1 in the bit time is 6.      */
#define  CAN_CTRL1_PBS1_7                     7U     /* 7 : the length of phase segment 1 in the bit time is 7.      */

/* ===============================================  CAN CTRL1 SJW [22..23]  =============================================== */
                                  /* CAN_CTRL1_SJW                                                          */
#define  CAN_CTRL1_SJW_0                     0U     /* 0 :  the maximum number of time quanta  is 0.      */
#define  CAN_CTRL1_SJW_1                     1U     /* 1 :  the maximum number of time quanta  is 1.      */
#define  CAN_CTRL1_SJW_2                     2U     /* 2 :  the maximum number of time quanta  is 2.      */
#define  CAN_CTRL1_SJW_3                     3U     /* 3 :  the maximum number of time quanta  is 3.      */

/* =========================================================  FRTMR  ========================================================= */
/* =======================================================  RXMASK  ======================================================== */
/* =======================================================  RX14MASK  ======================================================== */
/* =======================================================  RX15MASK  ======================================================== */
/* ========================================================  ERRCNT  ========================================================= */
/* ========================================================  ERRFLG1  ======================================================== */
/* ==============================================  CAN ERRFLG1 ERRFLG [1..1]  =============================================== */
                                 /* CAN_ERRFLG1_ERRFLG                                                       */
#define CAN_ERRFLG1_ERRFLG_0                   0U     /* 0 : No such occurrence.                                                   */
#define CAN_ERRFLG1_ERRFLG_1                   1U     /* 1 : Indicates setting of any Error Bit in the Error and Status
                                                     Register.                                                                 */


/* ===============================================  CAN ERRFLG1 BOFLG [2..2]  =============================================== */
                                 /* CAN_ERRFLG1_BOFLG                                                        */
#define  CAN_ERRFLG1_BOFLG_0                   0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_BOFLG_1                   1U     /* 1 : CAN module entered Bus Off state.                                 */


/* =========                                        CAN ERRFLG1 RXFLG [3..3]                                                  */
                                 /* CAN_ERRFLG1_RXFLG                                                        */
#define  CAN_ERRFLG1_RXFLG_0                   0U     /* 0 : CAN is not receiving a message.                                   */
#define  CAN_ERRFLG1_RXFLG_1                   1U     /* 1 : CAN is receiving a message.                                       */


/* ===============================================  CAN ERRFLG1 FCFLG [4..5]  ================================================ */
                                 /* CAN_ERRFLG1_FCFLG                                                         */
#define  CAN_ERRFLG1_FCFLG_00                   0U     /* 00 : Error Active                                                         */
#define  CAN_ERRFLG1_FCFLG_01                   1U     /* 01 : Error Passive                                                        */
#define  CAN_ERRFLG1_FCFLG_1x_2                 2U     /* 1x_2 : Bus Off                                                            */
#define  CAN_ERRFLG1_FCFLG_1x_3                 3U     /* 1x_3 : Bus Off                                                            */


/* ===============================================  CAN ERRFLG1 TXFLG [6..6]  =============================================== */
                                 /* CAN_ERRFLG1_TXFLG                                                        */
#define  CAN_ERRFLG1_TXFLG_0                   0U     /* 0 : CAN is not transmitting a message.                                */
#define  CAN_ERRFLG1_TXFLG_1                   1U     /* 1 : CAN is transmitting a message.                                    */


/* ===============================================  CAN ERRFLG1 BIDLEFLG [7..7]  =============================================== */
                                 /* CAN_ERRFLG1_BIDLEFLG                                                        */
#define  CAN_ERRFLG1_BIDLEFLG_0                   0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_BIDLEFLG_1                   1U     /* 1 : CAN bus is now IDLE.                                                  */


/* ===============================================  CAN ERRFLG1 RXERRWFLG [8..8]  ================================================ */
                                 /* CAN_ERRFLG1_RXERRWFLG                                                         */
#define  CAN_ERRFLG1_RXERRWFLG_0                    0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_RXERRWFLG_1                    1U     /* 1 : RXERRCNT is greater than or equal to 96.                              */


/* ===============================================  CAN ERRFLG1 TXERRWFLG [9..9]  ================================================ */
                                 /* CAN_ERRFLG1_TXERRWFLG                                                         */
#define  CAN_ERRFLG1_TXERRWFLG_0                    0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_TXERRWFLG_1                    1U     /* 1 : TXERRCNT is greater than or equal to 96.                              */


/* =============================================  CAN ERRFLG1 SERRFLG [10..10]  ============================================= */
                                 /* CAN_ERRFLG1_SERRFLG                                                      */
#define  CAN_ERRFLG1_SERRFLG_0                 0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_SERRFLG_1                 1U     /* 1 : A Stuffing Error occurred since last read of this register.           */


/* =============================================  CAN ERRFLG1 FERRFLG [11..11]  ============================================= */
                                 /* CAN_ERRFLG1_FERRFLG                                                      */
#define  CAN_ERRFLG1_FERRFLG_0                 0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FERRFLG_1                 1U     /* 1 : A Form Error occurred since last read of this register.               */


/* ============================================  CAN ERRFLG1 CRCERRFLG [12..12]  ============================================ */
                                 /* CAN_ERRFLG1_CRCERRFLG                                                    */
#define  CAN_ERRFLG1_CRCERRFLG_0               0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_CRCERRFLG_1               1U     /* 1 : A CRC error occurred since last read of this register.                */


/* ============================================  CAN ERRFLG1 ACKERRFLG [13..13]  ============================================ */
                                 /* CAN_ERRFLG1_ACKERRFLG                                                    */
#define  CAN_ERRFLG1_ACKERRFLG_0               0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_ACKERRFLG_1               1U     /* 1 : An ACK error occurred since last read of this register.               */


/* ============================================  CAN ERRFLG1 B0ERRFLG [14..14]  ============================================= */
                                 /* CAN_ERRFLG1_B0ERRFLG                                                     */
#define  CAN_ERRFLG1_B0ERRFLG_0                0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_B0ERRFLG_1                1U     /* 1 : At least one bit sent as dominant is received as recessive.           */


/* ============================================  CAN ERRFLG1 B1ERRFLG [15..15]  ============================================= */
                                 /* CAN_ERRFLG1_B1ERRFLG                                                     */
#define  CAN_ERRFLG1_B1ERRFLG_0                0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_B1ERRFLG_1                1U     /* 1 : At least one bit sent as recessive is received as dominant.           */


/* =============================================  CAN ERRFLG1 RXWINTFLG [16..16]  ============================================== */
                                 /* CAN_ERRFLG1_RXWINTFLG                                                       */
#define  CAN_ERRFLG1_RXWINTFLG_0                  0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_RXWINTFLG_1                  1U     /* 1 : The Rx error counter transitioned from less than 96 to greater
                                                     than or equal to 96.                                                      */


/* =============================================  CAN ERRFLG1 TXWINTFLG [17..17]  ============================================== */
                                 /* CAN_ERRFLG1_TXWINTFLG                                                       */
#define  CAN_ERRFLG1_TXWINTFLG_0                  0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_TXWINTFLG_1                  1U     /* 1 : The Tx error counter transitioned from less than 96 to greater
                                                     than or equal to 96.                                                      */


/* ==============================================  CAN ERRFLG1 BSYNFLG [18..18]  =============================================== */
                                 /* CAN_ERRFLG1_BSYNFLG                                                         */
#define  CAN_ERRFLG1_BSYNFLG_0                    0U     /* 0 : CAN is not synchronized to the CAN bus.                           */
#define  CAN_ERRFLG1_BSYNFLG_1                    1U     /* 1 : CAN is synchronized to the CAN bus.                               */


/* =============================================  CAN ERRFLG1 BOCINTFLG [19..19]  ============================================== */
                                 /* CAN_ERRFLG1_BOCINTFLG                                                       */
#define  CAN_ERRFLG1_BOCINTFLG_0                  0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_BOCINTFLG_1                  1U     /* 1 : CAN module has completed Bus Off process.                         */


/* ============================================  CAN ERRFLG1 FDERRFLG [20..20]  ============================================= */
                                 /* CAN_ERRFLG1_FDERRFLG                                                     */
#define  CAN_ERRFLG1_FDERRFLG_0                0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDERRFLG_1                1U     /* 1 : Indicates setting of any Error Bit detected in the Data
                                                     Phase of CAN FD frames with the BRS bit set.                              */


/* =============================================  CAN ERRFLG1 OVRFLG [21..21]  ============================================== */
                                 /* CAN_ERRFLG1_OVRFLG                                                       */
#define  CAN_ERRFLG1_OVRFLG_0                  0U     /* 0 : Overrun has not occurred.                                             */
#define  CAN_ERRFLG1_OVRFLG_1                  1U     /* 1 : Overrun has occurred.                                                 */


/* ============================================  CAN ERRFLG1 FDSERRFLG [26..26]  ============================================ */
                                 /* CAN_ERRFLG1_FDSERRFLG                                                    */
#define  CAN_ERRFLG1_FDSERRFLG_0               0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDSERRFLG_1               1U     /* 1 : A Stuffing Error occurred since last read of this register.           */


/* ============================================  CAN ERRFLG1 FDFERRFLG [27..27]  ============================================ */
                                 /* CAN_ERRFLG1_FDFERRFLG                                                    */
#define  CAN_ERRFLG1_FDFERRFLG_0               0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDFERRFLG_1               1U     /* 1 : A Form Error occurred since last read of this register.               */


/* ===========================================  CAN ERRFLG1 FDCRCERRFLG [28..28]  =========================================== */
                                 /* CAN_ERRFLG1_FDCRCERRFLG                                                  */
#define  CAN_ERRFLG1_FDCRCERRFLG_0             0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDCRCERRFLG_1             1U     /* 1 : A CRC error occurred since last read of this register.                */


/* ===========================================  CAN ERRFLG1 FDB0ERRFLG [30..30]  ============================================ */
                                 /* CAN_ERRFLG1_FDB0ERRFLG                                                   */
#define  CAN_ERRFLG1_FDB0ERRFLG_0              0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDB0ERRFLG_1              1U     /* 1 : At least one bit sent as dominant is received as recessive.           */


/* ===========================================  CAN ERRFLG1 FDB1ERRFLG [31..31]  ============================================ */
                                 /* CAN_ERRFLG1_FDB1ERRFLG                                                   */
#define  CAN_ERRFLG1_FDB1ERRFLG_0              0U     /* 0 : No such occurrence.                                                   */
#define  CAN_ERRFLG1_FDB1ERRFLG_1              1U     /* 1 : At least one bit sent as recessive is received as dominant.           */


/* =========================================================  MBiIEN  ========================================================= */
/* =========================================================  IFLG  ========================================================== */
/* ================================================  CAN IFLG MB0INT [0..0]  ================================================ */
                                 /* CAN_IFLG_MB0INT                                                          */
#define  CAN_IFLG_MB0INT_0                     0U     /* 0 : The corresponding buffer has no occurrence of successfully
                                                 completed transmission or reception when MCR[RFEN] 0.                     */
#define  CAN_IFLG_MB0INT_1                     1U     /* 1 : The corresponding buffer has successfully completed transmission
                                                       or reception when MCR[RFEN] 0.                                            */


/* ================================================  CAN IFLG MB5INT [5..5]  ================================================ */
                                 /* CAN_IFLG_MB5INT                                                          */
#define  CAN_IFLG_MB5INT_0                     0U     /* 0 : No occurrence of MB5 completing transmission/reception when
                                                 MCR[RFEN] 0U or of frame(s) available in the FIFOU when
                                                     MCR[RFEN] 1                                                               */
#define  CAN_IFLG_MB5INT_1                     1U     /* 1 : MB5 completed transmission/reception when MCR[RFEN] 0U or
                                                 frame(s) available in the Rx FIFO when MCR[RFEN] 1. It
                                                     generates a DMA request in case of MCR[RFEN] and MCR[DMA]
                                                     are enabled.                                                              */


/* ================================================  CAN IFLG MB6INT [6..6]  ================================================ */
                                 /* CAN_IFLG_MB6INT                                                          */
#define  CAN_IFLG_MB6INT_0                     0U     /* 0 : No occurrence of MB6 completing transmission/reception when
                                                        MCR[RFEN] 0U or of Rx FIFO almost full when MCR[RFEN] 1                   */
#define  CAN_IFLG_MB6INT_1                     1U     /* 1 : MB6 completed transmission/reception when MCR[RFEN] 0U or
                                                         Rx FIFO almost full when MCR[RFEN] 1                                      */


/* ================================================  CAN IFLG MB7INT [7..7]  ================================================ */
                                 /* CAN_IFLG_MB7INT                                                          */
#define  CAN_IFLG_MB7INT_0                     0U     /* 0 : No occurrence of MB7 completing transmission/reception when
                                                       MCR[RFEN] 0U or of Rx FIFO overflow when MCR[RFEN] 1                      */
#define  CAN_IFLG_MB7INT_1                     1U     /* 1 : MB7 completed transmission/reception when MCR[RFEN] 0U or
                                                      Rx FIFO overflow when MCR[RFEN] 1                                         */


/* =========================================================  CTRL2  ========================================================= */
/* ================================================  CAN CTRL2 EFD [11..11]  ================================================ */
                                 /* CAN_CTRL2_EFD                                                            */
#define  CAN_CTRL2_EFD_0                       0U     /* 0 : Edge Filter is enabled.                                               */
#define  CAN_CTRL2_EFD_1                       1U     /* 1 : Edge Filter is disabled.                                              */


/* ==============================================  CAN CTRL2 ISOFDEN [12..12]  ============================================== */
                                 /* CAN_CTRL2_ISOFDEN                                                        */
#define  CAN_CTRL2_ISOFDEN_0                   0U     /* 0 : CAN operates using the non-ISO CAN FD protocol.                   */
#define  CAN_CTRL2_ISOFDEN_1                   1U     /* 1 : CAN operates using the ISO CAN FD protocol (ISO 11898-1).         */


/* ===============================================  CAN CTRL2 PEEN [14..14]  ================================================ */
                                 /* CAN_CTRL2_PEEN                                                           */
#define  CAN_CTRL2_PEEN_0                      0U     /* 0 : Protocol Exception is disabled.                                       */
#define  CAN_CTRL2_PEEN_1                      1U     /* 1 : Protocol Exception is enabled.                                        */


/* ==============================================  CAN CTRL2 TMRSRC [15..15]  =============================================== */
                                 /* CAN_CTRL2_TMRSRC                                                         */
#define  CAN_CTRL2_TMRSRC_0                    0U     /* 0 : The Free Running Timer is clocked by the CAN bit clockU
                                                      which defines the baud rate on the CAN bus.                               */
#define  CAN_CTRL2_TMRSRC_1                    1U     /* 1 : The Free Running Timer is clocked by an external time tick.
                                                      The period can be either adjusted to be equal to the baud
                                                     rate on the CAN busU or a different value as required.
                                                     See the device specific section for details about the external
                                                     time tick.                                                                */


/* ===============================================  CAN CTRL2 CMPEN [16..16]  =============================================== */
                                 /* CAN_CTRL2_CMPEN                                                          */
#define  CAN_CTRL2_CMPEN_0                     0U     /* 0 : Rx Mailbox filters IDE bit is always compared and RTR is
                                                      never compared despite mask bits.                                         */
#define  CAN_CTRL2_CMPEN_1                     1U     /* 1 : Enables the comparison of both Rx Mailbox filters IDE and
                                                        RTR bit with their corresponding bits within the incoming
                                                     frame. Mask bits do apply.                                                */


/* ================================================  CAN CTRL2 RFS [17..17]  ================================================ */
                                 /* CAN_CTRL2_RFS                                                            */
#define  CAN_CTRL2_RFS_0                       0U     /* 0 : Remote Response Frame is generated.                                   */
#define  CAN_CTRL2_RFS_1                       1U     /* 1 : Remote Request Frame is stored.                                       */


/* ===============================================  CAN CTRL2 MBPRI [18..18]  =============================================== */
                                 /* CAN_CTRL2_MBPRI                                                          */
#define  CAN_CTRL2_MBPRI_0                     0U     /* 0 : Matching starts from Rx FIFO and continues on Mailboxes.              */
#define  CAN_CTRL2_MBPRI_1                     1U     /* 1 : Matching starts from Mailboxes and continues on Rx FIFO.              */


/* ==============================================  CAN CTRL2 BOCIEN [30..30]  =============================================== */
                                 /* CAN_CTRL2_BOCIEN                                                         */
#define  CAN_CTRL2_BOCIEN_0                    0U     /* 0 : Bus Off Done interrupt disabled.                                      */
#define  CAN_CTRL2_BOCIEN_1                    1U     /* 1 : Bus Off Done interrupt enabled.                                       */


/* =============================================  CAN CTRL2 FDERRIEN [31..31]  ============================================== */
                                 /* CAN_CTRL2_FDERRIEN                                                       */
#define  CAN_CTRL2_FDERRIEN_0                  0U     /* 0 : ERRINT_FAST Error interrupt disabled.                                 */
#define  CAN_CTRL2_FDERRIEN_1                  1U     /* 1 : ERRINT_FAST Error interrupt enabled.                                  */


/* ========================================================  ERRFLG2  ======================================================== */
/* ==============================================  CAN ERRFLG2 IAMBFLG [13..13]  =============================================== */
                                 /* CAN_ERRFLG2_IAMBFLG                                                         */
#define  CAN_ERRFLG2_IAMBFLG_0                    0U     /* 0 : If ESR2[VPS] is assertedU the ESR2[LPTM] is not an inactive
                                                        Mailbox.                                                                  */
#define  CAN_ERRFLG2_IAMBFLG_1                    1U     /* 1 : If ESR2[VPS] is assertedU there is at least one inactive
                                                         Mailbox. LPTM content is the number of the first one.                     */


/* ==============================================  CAN ERRFLG2 CVFLG [14..14]  ============================================== */
                                 /* CAN_ERRFLG2_CVFLG                                                        */
#define  CAN_ERRFLG2_CVFLG_0                   0U     /* 0 : Contents of IMB and LPTM are invalid.                                 */
#define  CAN_ERRFLG2_CVFLG_1                   1U     /* 1 : Contents of IMB and LPTM are valid.                                   */


/* ==========================================================  CRC  ========================================================== */
/* =======================================================  FIFOGMASK  ======================================================= */
/* =======================================================  FIFOINFO  ======================================================== */
/* ========================================================  BTIM  ========================================================= */
/* ==============================================  CAN BTIM EBTEN [31..31]  =============================================== */
                                 /* CAN_BTIM_EBTEN                                                         */
#define  CAN_BTIM_EBTEN_0                    0U     /* 0 : Extended bit time definitions disabled.                               */
#define  CAN_BTIM_EBTEN_1                    1U     /* 1 : Extended bit time definitions enabled.                                */


/* =========================================================  RAMn  ========================================================= */
/* =======================================================  RXIMASK  ======================================================== */
/* ========================================================  PNCTRL1  ======================================================== */
/* ===============================================  CAN PNCTRL1 FCSEL [0..1]  =============================================== */
                                 /* CAN_PNCTRL1_FCSEL                                                        */
#define  CAN_PNCTRL1_FCSEL_00                  0U     /* 00 : Message ID filtering only                                            */
#define  CAN_PNCTRL1_FCSEL_01                  1U     /* 01 : Message ID filtering and payload filtering                           */
#define  CAN_PNCTRL1_FCSEL_10                  2U     /* 10 : Message ID filtering occurring a specified number of times.          */
#define  CAN_PNCTRL1_FCSEL_11                  3U     /* 11 : Message ID filtering and payload filtering a specified
                                                     number of times                                                           */


/* ==============================================  CAN PNCTRL1 IDFLSEL [2..3]  ============================================== */
                                 /* CAN_PNCTRL1_IDFLSEL                                                      */
#define  CAN_PNCTRL1_IDFLSEL_00                0U     /* 00 : Match upon a ID contents against an exact target value               */
#define  CAN_PNCTRL1_IDFLSEL_01                1U     /* 01 : Match upon a ID value greater than or equal to a specified
                                                     target value                                                              */
#define  CAN_PNCTRL1_IDFLSEL_10                2U     /* 10 : Match upon a ID value smaller than or equal to a specified
                                                      target value                                                              */
#define  CAN_PNCTRL1_IDFLSEL_11                3U     /* 11 : Match upon a ID value inside a rangeU greater than or equal
                                                       to a specified lower limit and smaller than or equal a
                                                     specified upper limit                                                     */


/* ==============================================  CAN PNCTRL1 PFLSEL [4..5]  =============================================== */
                                 /* CAN_PNCTRL1_PFLSEL                                                       */
#define  CAN_PNCTRL1_PFLSEL_00                 0U     /* 00 : Match upon a payload contents against an exact target value          */
#define  CAN_PNCTRL1_PFLSEL_01                 1U     /* 01 : Match upon a payload value greater than or equal to a specified
                                                     target value                                                              */
#define  CAN_PNCTRL1_PFLSEL_10                 2U     /* 10 : Match upon a payload value smaller than or equal to a specified
                                                      target value                                                              */
#define  CAN_PNCTRL1_PFLSEL_11                 3U     /* 11 : Match upon a payload value inside a rangeU greater than
                                                      or equal to a specified lower limit and smaller than or
                                                     equal a specified upper limit                                             */


/* ==============================================  CAN PNCTRL1 NUMMSG [8..15]  ============================================== */
                                 /* CAN_PNCTRL1_NUMMSG                                                       */
#define  CAN_PNCTRL1_NUMMSG_00000001           1U     /* 00000001 : Received message must match the predefined filtering
                                                         criteria for ID and/or PL once before generating a wake
                                                     up event.                                                                 */
#define  CAN_PNCTRL1_NUMMSG_00000010           2U     /* 00000010 : Received message must match the predefined filtering
                                                        criteria for ID and/or PL twice before generating a wake
                                                     up event.                                                                 */
#define  CAN_PNCTRL1_NUMMSG_11111111           255U   /* 11111111 : Received message must match the predefined filtering
                                                      criteria for ID and/or PL 255 times before generating a
                                                     wake up event.                                                            */


/* ==============================================  CAN PNCTRL1 WUMEN [16..16]  ============================================== */
                                 /* CAN_PNCTRL1_WUMEN                                                        */
#define  CAN_PNCTRL1_WUMEN_0                   0U     /* 0 : Wake up match event is disabled                                       */
#define  CAN_PNCTRL1_WUMEN_1                   1U     /* 1 : Wake up match event is enabled                                        */


/* ==============================================  CAN PNCTRL1 WUTEN [17..17]  ============================================== */
                                 /* CAN_PNCTRL1_WUTEN                                                        */
#define  CAN_PNCTRL1_WUTEN_0                   0U     /* 0 : Timeout wake up event is disabled                                     */
#define  CAN_PNCTRL1_WUTEN_1                   1U     /* 1 : Timeout wake up event is enabled                                      */



/* ========================================================  PNCTRL2  ======================================================== */
/* =========================================================  PNWM  ========================================================== */
/* ===============================================  CAN PNWM WUMFLG [16..16]  =============================================== */
                                 /* CAN_PNWM_WUMFLG                                                          */
#define  CAN_PNWM_WUMFLG_0                     0U     /* 0 : No wake up by match event detected                                    */
#define  CAN_PNWM_WUMFLG_1                     1U     /* 1 : Wake up by match event detected                                       */


/* ===============================================  CAN PNWM WUTFLG [17..17]  =============================================== */
                                 /* CAN_PNWM_WUTFLG                                                          */
#define  CAN_PNWM_WUTFLG_0                     0U     /* 0 : No wake up by timeout event detected                                  */
#define  CAN_PNWM_WUTFLG_1                     1U     /* 1 : Wake up by timeout event detected                                     */


/* ========================================================  PNIDF1  ========================================================= */
/* ===============================================  CAN PNIDF1 RFF [29..29]  ================================================ */
                                 /* CAN_PNIDF1_RFF                                                           */
#define  CAN_PNIDF1_RFF_0                      0U     /* 0 : Reject remote frame (accept data frame)                               */
#define  CAN_PNIDF1_RFF_1                      1U     /* 1 : Accept remote frame                                                   */


/* ===============================================  CAN PNIDF1 EXFF [30..30]  =============================================== */
                                 /* CAN_PNIDF1_EXFF                                                          */
#define  CAN_PNIDF1_EXFF_0                     0U     /* 0 : Accept standard frame format                                          */
#define  CAN_PNIDF1_EXFF_1                     1U     /* 1 : Accept extended frame format                                          */


/* ========================================================  PNDLCF  ========================================================= */
/* ========================================================  PNPLF1  ========================================================= */
/* ========================================================  PNPHF1  ========================================================= */
/* ========================================================  PNIDF2  ========================================================= */
/* ==============================================  CAN PNIDF2 RFMASK [29..29]  ============================================== */
                                 /* CAN_PNIDF2_RFMASK                                                        */
#define  CAN_PNIDF2_RFMASK_0                   0U     /* 0 : The corresponding bit in the filter is 'dont care'                    */
#define  CAN_PNIDF2_RFMASK_1                   1U     /* 1 : The corresponding bit in the filter is checked                        */


/* =============================================  CAN PNIDF2 EXFMASK [30..30]  ============================================== */
                                 /* CAN_PNIDF2_EXFMASK                                                       */
#define  CAN_PNIDF2_EXFMASK_0                  0U     /* 0 : The corresponding bit in the filter is 'dont care'                    */
#define  CAN_PNIDF2_EXFMASK_1                  1U     /* 1 : The corresponding bit in the filter is checked                        */


/* ========================================================  PNPLF2  ========================================================= */
/* ========================================================  PNPHF2  ========================================================= */
/* ========================================================  WMB0_CS  ======================================================== */
/* ===============================================  CAN WMB0_CS RTR [20..20]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB0_CS_RTR                                            */
#define  CAN_WMB_CS_WMB_CS_WMB0_CS_RTR_0       0U     /* 0 : Frame is data one (not remote)                                        */
#define  CAN_WMB_CS_WMB_CS_WMB0_CS_RTR_1       1U     /* 1 : Frame is a remote one                                                 */


/* ===============================================  CAN WMB0_CS IDE [21..21]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB0_CS_IDE                                            */
#define  CAN_WMB_CS_WMB_CS_WMB0_CS_IDE_0       0U     /* 0 : Frame format is standard                                              */
#define  CAN_WMB_CS_WMB_CS_WMB0_CS_IDE_1       1U     /* 1 : Frame format is extended                                              */


/* ========================================================  WMB1_CS  ======================================================== */
/* ===============================================  CAN WMB1_CS RTR [20..20]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB1_CS_RTR                                            */
#define  CAN_WMB_CS_WMB_CS_WMB1_CS_RTR_0       0U     /* 0 : Frame is data one (not remote)                                        */
#define  CAN_WMB_CS_WMB_CS_WMB1_CS_RTR_1       1U     /* 1 : Frame is a remote one                                                 */


/* ===============================================  CAN WMB1_CS IDE [21..21]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB1_CS_IDE                                            */
#define  CAN_WMB_CS_WMB_CS_WMB1_CS_IDE_0       0U     /* 0 : Frame format is standard                                              */
#define  CAN_WMB_CS_WMB_CS_WMB1_CS_IDE_1       1U     /* 1 : Frame format is extended                                              */


/* ========================================================  WMB2_CS  ======================================================== */
/* ===============================================  CAN WMB2_CS RTR [20..20]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB2_CS_RTR                                            */
#define  CAN_WMB_CS_WMB_CS_WMB2_CS_RTR_0       0U     /* 0 : Frame is data one (not remote)                                        */
#define  CAN_WMB_CS_WMB_CS_WMB2_CS_RTR_1       1U     /* 1 : Frame is a remote one                                                 */


/* ===============================================  CAN WMB2_CS IDE [21..21]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB2_CS_IDE                                            */
#define  CAN_WMB_CS_WMB_CS_WMB2_CS_IDE_0       0U     /* 0 : Frame format is standard                                              */
#define  CAN_WMB_CS_WMB_CS_WMB2_CS_IDE_1       1U     /* 1 : Frame format is extended                                              */


/* ========================================================  WMB3_CS  ======================================================== */
/* ===============================================  CAN WMB3_CS RTR [20..20]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB3_CS_RTR                                            */
#define  CAN_WMB_CS_WMB_CS_WMB3_CS_RTR_0       0U     /* 0 : Frame is data one (not remote)                                        */
#define  CAN_WMB_CS_WMB_CS_WMB3_CS_RTR_1       1U     /* 1 : Frame is a remote one                                                 */


/* ===============================================  CAN WMB3_CS IDE [21..21]  =============================================== */
                                 /* CAN_WMB_CS_WMB_CS_WMB3_CS_IDE                                            */
#define  CAN_WMB_CS_WMB_CS_WMB3_CS_IDE_0       0U     /* 0 : Frame format is standard                                              */
#define  CAN_WMB_CS_WMB_CS_WMB3_CS_IDE_1       1U     /* 1 : Frame format is extended                                              */


/* ========================================================  WMB0_ID  ======================================================== */
/* ========================================================  WMB1_ID  ======================================================== */
/* ========================================================  WMB2_ID  ======================================================== */
/* ========================================================  WMB3_ID  ======================================================== */
/* ======================================================  WMB0_LDATA  ====================================================== */
/* ======================================================  WMB1_LDATA  ====================================================== */
/* ======================================================  WMB2_LDATA  ====================================================== */
/* ======================================================  WMB3_LDATA  ====================================================== */
/* ======================================================  WMB0_HDATA  ====================================================== */
/* ======================================================  WMB1_HDATA  ====================================================== */
/* ======================================================  WMB2_HDATA  ====================================================== */
/* ======================================================  WMB3_HDATA  ====================================================== */
/* ========================================================  FDCTRL  ========================================================= */
/* ===============================================  CAN FDCTRL TDCF [14..14]  =============================================== */
                                 /* CAN_FDCTRL_TDCF                                                          */
#define  CAN_FDCTRL_TDCF_0                     0U     /* 0 : Measured loop delay is in range.                                      */
#define  CAN_FDCTRL_TDCF_1                     1U     /* 1 : Measured loop delay is out of range.                                  */


/* ==============================================  CAN FDCTRL TDCEN [15..15]  =============================================== */
                                 /* CAN_FDCTRL_TDCEN                                                         */
#define  CAN_FDCTRL_TDCEN_0                    0U     /* 0 : TDC is disabled                                                       */
#define  CAN_FDCTRL_TDCEN_1                    1U     /* 1 : TDC is enabled                                                        */


/* ==============================================  CAN FDCTRL MBSIZE [16..17]  ============================================== */
                                 /* CAN_FDCTRL_MBSIZE                                                        */
#define  CAN_FDCTRL_MBSIZE_00                  0U     /* 00 : Selects 8 bytes per Message Buffer.                                  */
#define  CAN_FDCTRL_MBSIZE_01                  1U     /* 01 : Selects 16 bytes per Message Buffer.                                 */
#define  CAN_FDCTRL_MBSIZE_10                  2U     /* 10 : Selects 32 bytes per Message Buffer.                                 */
#define  CAN_FDCTRL_MBSIZE_11                  3U     /* 11 : Selects 64 bytes per Message Buffer.                                 */


/* ==============================================  CAN FDCTRL BRSEN [31..31]  =============================================== */
                                 /* CAN_FDCTRL_BRSEN                                                         */
#define  CAN_FDCTRL_BRSEN_0                    0U     /* 0 : Transmit a frame in nominal rate. The BRS bit in the Tx
                                                         MB has no effect.                                                         */
#define  CAN_FDCTRL_BRSEN_1                    1U     /* 1 : Transmit a frame with bit rate switching if the BRS bit
                                                         in the Tx MB is recessive.                                                */


/* ========================================================  FDBTIM  ========================================================= */
/* =========================================================  FDCRC  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           CFGTMR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CSTS  ========================================================== */
/* ==============================================  CFGTMR CSTS CLKDFSEL [0..2]  =============================================== */
                                 /* CFGTMR_CSTS_CLKDFSEL                                                       */
#define  CFGTMR_CSTS_CLKDFSEL_000                0U     /* 000 : Divide by 1                                                         */
#define  CFGTMR_CSTS_CLKDFSEL_001                1U     /* 001 : Divide by 2                                                         */
#define  CFGTMR_CSTS_CLKDFSEL_010                2U     /* 010 : Divide by 4                                                         */
#define  CFGTMR_CSTS_CLKDFSEL_011                3U     /* 011 : Divide by 8                                                         */
#define  CFGTMR_CSTS_CLKDFSEL_100                4U     /* 100 : Divide by 16                                                        */
#define  CFGTMR_CSTS_CLKDFSEL_101                5U     /* 101 : Divide by 32                                                        */
#define  CFGTMR_CSTS_CLKDFSEL_110                6U     /* 110 : Divide by 64                                                        */
#define  CFGTMR_CSTS_CLKDFSEL_111                7U     /* 111 : Divide by 128                                                       */


/* ==============================================  CFGTMR CSTS CCLKSSEL [3..4]  =============================================== */
                                 /* CFGTMR_CSTS_CCLKSSEL                                                       */
#define  CFGTMR_CSTS_CCLKSSEL_00                 0U     /* 00 : No clock selected. This in effect disables the CFGTMR counter.          */
#define  CFGTMR_CSTS_CCLKSSEL_01                 1U     /* 01 : CFGTMR input clock                                                      */
#define  CFGTMR_CSTS_CCLKSSEL_10                 2U     /* 10 : Fixed frequency clock                                                */
#define  CFGTMR_CSTS_CCLKSSEL_11                 3U     /* 11 : External clock                                                       */


/* ================================================  CFGTMR CSTS CMSEL [5..5]  ================================================ */
                                 /* CFGTMR_CSTS_CMSEL                                                          */
#define  CFGTMR_CSTS_CMSEL_0                     0U     /* 0 : CFGTMR counter operates in Up Counting mode.                             */
#define  CFGTMR_CSTS_CMSEL_1                     1U     /* 1 : CFGTMR counter operates in Up-Down Counting mode.                        */


/* ================================================  CFGTMR CSTS RPIEN [6..6]  ================================================ */
                                 /* CFGTMR_CSTS_RPIEN                                                          */
#define  CFGTMR_CSTS_RPIEN_0                     0U     /* 0 : Reload point interrupt is disabled.                                   */
#define  CFGTMR_CSTS_RPIEN_1                     1U     /* 1 : Reload point interrupt is enabled.                                    */


/* ================================================  CFGTMR CSTS RFLG [7..7]  ================================================= */
                                 /* CFGTMR_CSTS_RFLG                                                           */
#define  CFGTMR_CSTS_RFLG_0                      0U     /* 0 : A selected reload point did not happen.                               */
#define  CFGTMR_CSTS_RFLG_1                      1U     /* 1 : A selected reload point happened.                                     */


/* ==============================================  CFGTMR CSTS CFGTMROIEN [8..8]  =============================================== */
                                 /* CFGTMR_CSTS_CFGTMROIEN                                                       */
#define  CFGTMR_CSTS_CFGTMROIEN_0                  0U     /* 0 : Disable TOF interrupts. Use software polling.                         */
#define  CFGTMR_CSTS_CFGTMROIEN_1                  1U     /* 1 : Enable TOF interrupts. An interrupt is generated when TOF
                                                     equals one.                                                               */


/* ==============================================  CFGTMR CSTS CFGTMROFLG [9..9]  =============================================== */
                                 /* CFGTMR_CSTS_CFGTMROFLG                                                       */
#define  CFGTMR_CSTS_CFGTMROFLG_0                  0U     /* 0 : CFGTMR counter has not overflowed.                                       */
#define  CFGTMR_CSTS_CFGTMROFLG_1                  1U     /* 1 : CFGTMR counter has overflowed.                                           */


/* =============================================  CFGTMR CSTS PWMOENCH0 [16..16]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH0                                                       */
#define  CFGTMR_CSTS_PWMOENCH0_0                  0U     /* 0 : Channel 0 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH0_1                  1U     /* 1 : Channel 0 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH1 [17..17]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH1                                                       */
#define  CFGTMR_CSTS_PWMOENCH1_0                  0U     /* 0 : Channel 1 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH1_1                  1U     /* 1 : Channel 1 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH2 [18..18]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH2                                                       */
#define  CFGTMR_CSTS_PWMOENCH2_0                  0U     /* 0 : Channel 2 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH2_1                  1U     /* 1 : Channel 2 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH3 [19..19]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH3                                                       */
#define  CFGTMR_CSTS_PWMOENCH3_0                  0U     /* 0 : Channel 3 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH3_1                  1U     /* 1 : Channel 3 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH4 [20..20]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH4                                                       */
#define  CFGTMR_CSTS_PWMOENCH4_0                  0U     /* 0 : Channel 4 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH4_1                  1U     /* 1 : Channel 4 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH5 [21..21]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH5                                                       */
#define  CFGTMR_CSTS_PWMOENCH5_0                  0U     /* 0 : Channel 5 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH5_1                  1U     /* 1 : Channel 5 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH6 [22..22]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH6                                                       */
#define  CFGTMR_CSTS_PWMOENCH6_0                  0U     /* 0 : Channel 6 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH6_1                  1U     /* 1 : Channel 6 output port is enabled                                        */

/* =============================================  CFGTMR CSTS PWMOENCH7 [23..23]  ============================================== */
                                 /* CFGTMR_CSTS_PWMOENCH7                                                       */
#define  CFGTMR_CSTS_PWMOENCH7_0                  0U     /* 0 : Channel 7 output port is disabled                                       */
#define  CFGTMR_CSTS_PWMOENCH7_1                  1U     /* 1 : Channel 7 output port is enabled                                        */


/* ==============================================  CFGTMR CSTS FPSCSEL [24..27]  ============================================== */
                                 /* CFGTMR_CSTS_FPSCSEL                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0000                0U     /* 0000 : Divide by 1                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0001                1U     /* 0001 : Divide by 2                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0010                2U     /* 0010 : Divide by 3                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0011                3U     /* 0011 : Divide by 4                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0100                4U     /* 0100 : Divide by 5                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0101                5U     /* 0101 : Divide by 6                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0110                6U     /* 0110 : Divide by 7                                                        */
#define  CFGTMR_CSTS_FPSCSEL_0111                7U     /* 0111 : Divide by 8                                                        */
#define  CFGTMR_CSTS_FPSCSEL_1000                8U     /* 1000 : Divide by 9                                                        */
#define  CFGTMR_CSTS_FPSCSEL_1001                9U     /* 1001 : Divide by 10                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1010                10U    /* 1010 : Divide by 11                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1011                11U    /* 1011 : Divide by 12                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1100                12U    /* 1100 : Divide by 13                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1101                13U    /* 1101 : Divide by 14                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1110                14U    /* 1110 : Divide by 15                                                       */
#define  CFGTMR_CSTS_FPSCSEL_1111                15U    /* 1111 : Divide by 16                                                       */


/* ==========================================================  CNT  ========================================================== */
/* ==========================================================  MOD  ========================================================== */
/* ========================================================  CHnCSTS  ======================================================== */
/* ==============================================  CFGTMR CHnCSTS DMAEN [0..0]  =============================================== */
                                 /* CFGTMR_CHnCSTS_DMAEN                                         */
#define  CFGTMR_CHnCSTS_DMAEN_0    0U     /* 0 : Disable DMA transfers.                                                */
#define  CFGTMR_CHnCSTS_DMAEN_1    1U     /* 1 : Enable DMA transfers.                                                 */


/* =============================================  CFGTMR CHnCSTS CRSTCTRL [1..1]  ============================================= */
                                 /* CFGTMR_CHnCSTS_CRSTCTRL                                      */
#define  CFGTMR_CHnCSTS_CRSTCTRL_0   0U   /* 0 : CFGTMR counter is not reset when the selected channel (n) input
                                                        event is detected.                                                        */
#define  CFGTMR_CHnCSTS_CRSTCTRL_1   1U   /* 1 : CFGTMR counter is reset when the selected channel (n) input
                                                        event is detected.                                                        */

/* ==============================================  CFGTMR CHnCSTS CHMSEL0 [2..2]  =============================================== */
                                 /* CFGTMR_CHnCSTS_CHMSEL0                                         */
#define  CFGTMR_CHnCSTS_CHMSEL0_0    0U
#define  CFGTMR_CHnCSTS_CHMSEL0_1    1U

/* ==============================================  CFGTMR CHnCSTS CHMSEL1 [3..3]  =============================================== */
                                 /* CFGTMR_CHnCSTS_CHMSEL1                                         */
#define  CFGTMR_CHnCSTS_CHMSEL1_0    0U
#define  CFGTMR_CHnCSTS_CHMSEL1_1    1U

/* ==============================================  CFGTMR CHnCSTS CHMSEL2 [4..4]  =============================================== */
                                 /* CFGTMR_CHnCSTS_CHMSEL2                                         */
#define  CFGTMR_CHnCSTS_CHMSEL2_0    0U
#define  CFGTMR_CHnCSTS_CHMSEL2_1    1U

/* ==============================================  CFGTMR CHnCSTS CHMSEL3 [5..5]  =============================================== */
                                 /* CFGTMR_CHnCSTS_CHMSEL3                                         */
#define  CFGTMR_CHnCSTS_CHMSEL3_0    0U
#define  CFGTMR_CHnCSTS_CHMSEL3_1    1U

/* ==============================================  CFGTMR CHnCSTS CHIEN [6..6]  =============================================== */
                                 /* CFGTMR_CHnCSTS_CHIEN                                         */
#define  CFGTMR_CHnCSTS_CHIEN_0    0U     /* 0 : Disable channel (n) interrupt. Use software polling.                  */
#define  CFGTMR_CHnCSTS_CHIEN_1    1U     /* 1 : Enable channel (n) interrupt.                                         */


/* =============================================  CFGTMR CHnCSTS CHEVFLG [7..7]  ============================================== */
                                 /* CFGTMR_CHnCSTS_CHEVFLG                                       */
#define  CFGTMR_CHnCSTS_CHEVFLG_0   0U    /* 0 : No channel (n) event has occurred.                                    */
#define  CFGTMR_CHnCSTS_CHEVFLG_1   1U    /* 1 : A channel (n) event has occurred.                                     */


/* ============================================  CFGTMR CHnCSTS CHOTMCTRL [8..8]  ============================================= */
                                 /* CFGTMR_CHnCSTS_CHOTMCTRL                                     */
#define  CFGTMR_CHnCSTS_CHOTMCTRL_0   0U  /* 0 : Channel outputs will generate the normal PWM outputs without
                                                       generating a pulse.                                                       */
#define  CFGTMR_CHnCSTS_CHOTMCTRL_1   1U  /* 1 : If a match in the channel occursU a trigger generation on
                                                        channel output will happen. The trigger pulse width has
                                                     one CFGTMR clock cycle.                                                      */


/* ==============================================  CFGTMR CHnCSTS CHISTS [9..9]  ============================================== */
                                 /* CFGTMR_CHnCSTS_CHISTS                                        */
#define  CFGTMR_CHnCSTS_CHISTS_0   0U     /* 0 : The channel (n) input is zero.                                        */
#define  CFGTMR_CHnCSTS_CHISTS_1   1U     /* 1 : The channel (n) input is one.                                         */


/* ============================================  CFGTMR CHnCSTS CHOLSEL [10..10]  ============================================= */
                                 /* CFGTMR_CHnCSTS_CHOLSEL                                       */
#define  CFGTMR_CHnCSTS_CHOLSEL_0   0U    /* 0 : The channel (n) output is zero.                                       */
#define  CFGTMR_CHnCSTS_CHOLSEL_1   1U    /* 1 : The channel (n) output is one.                                        */

/* =========================================================  CHnV  ========================================================== */
/* =========================================================  INITV  ========================================================= */
/* =========================================================  CCSTS  ========================================================= */
/* ==============================================  CFGTMR CCSTS CHEVFLG0 [0..0]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG0                                                       */
#define  CFGTMR_CCSTS_CHEVFLG0_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG0_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG1 [1..1]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG1                                                       */
#define  CFGTMR_CCSTS_CHEVFLG1_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG1_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG2 [2..2]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG2                                                       */
#define  CFGTMR_CCSTS_CHEVFLG2_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG2_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG3 [3..3]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG3                                                       */
#define  CFGTMR_CCSTS_CHEVFLG3_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG3_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG4 [4..4]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG4                                                       */
#define  CFGTMR_CCSTS_CHEVFLG4_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG4_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG [5..5]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG5                                                      */
#define  CFGTMR_CCSTS_CHEVFLG5_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG5_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG6 [6..6]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG6                                                       */
#define  CFGTMR_CCSTS_CHEVFLG6_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG6_1                  1U     /* 1 : A channel event has occurred.                                         */

/* ==============================================  CFGTMR CCSTS CHEVFLG7 [7..7]  =============================================== */
                                 /* CFGTMR_CCSTS_CHEVFLG7                                                       */
#define  CFGTMR_CCSTS_CHEVFLG7_0                  0U     /* 0 : No channel event has occurred.                                        */
#define  CFGTMR_CCSTS_CHEVFLG7_1                  1U     /* 1 : A channel event has occurred.                                         */


/* ==========================================================  FMSEL  ========================================================== */
/* ================================================  CFGTMR FMSEL CFGTMREN [0..0]  ================================================ */
                                 /* CFGTMR_FMSEL_CFGTMREN                                                          */
#define  CFGTMR_FMSEL_CFGTMREN_0                     0U     /* 0 : TPM compatibility. Free running counter and synchronization
                                                       compatible with TPM.                                                      */
#define  CFGTMR_FMSEL_CFGTMREN_1                     1U     /* 1 : Free running counter and synchronization are different from
                                                      TPM behavior.                                                             */


/* ===============================================  CFGTMR FMSEL WPUNLOCK [2..2]  =============================================== */
                                 /* CFGTMR_FMSEL_WPUNLOCK                                                        */
#define  CFGTMR_FMSEL_WPUNLOCK_0                   0U     /* 0 : Write protection is enabled.                                          */
#define  CFGTMR_FMSEL_WPUNLOCK_1                   1U     /* 1 : Write protection is disabled.                                         */


/* ===============================================  CFGTMR FMSEL PWMSMCFG [3..3]  =============================================== */
                                 /* CFGTMR_FMSEL_PWMSMCFG                                                        */
#define  CFGTMR_FMSEL_PWMSMCFG_0                   0U     /* 0 : No restrictions. Software and hardware triggers can be used
                                                         by MODU CnVU OUTMASKU and CFGTMR counter synchronization.                    */
#define  CFGTMR_FMSEL_PWMSMCFG_1                   1U     /* 1 : Software trigger can only be used by MOD and CHnV synchronizationU
                                                         and hardware triggers can only be used by OUTMASK and CFGTMR
                                                     counter synchronization.                                                  */


/* ================================================  CFGTMR FMSEL CTMEN [4..4]  ================================================= */
                                 /* CFGTMR_FMSEL_CTMEN                                                           */
#define  CFGTMR_FMSEL_CTMEN_0                      0U     /* 0 : Capture test mode is disabled.                                        */
#define  CFGTMR_FMSEL_CTMEN_1                      1U     /* 1 : Capture test mode is enabled.                                         */


/* ==============================================  CFGTMR FMSEL FCTRLMSEL [5..6]  =============================================== */
                                 /* CFGTMR_FMSEL_FCTRLMSEL                                                       */
#define  CFGTMR_FMSEL_FCTRLMSEL_00                 0U     /* 00 : Fault control is disabled for all channels.                          */
#define  CFGTMR_FMSEL_FCTRLMSEL_01                 1U     /* 01 : Fault control is enabled for even channels only (channels
                                                     0U 2U 4U and 6)U and the selected mode is the manual fault
                                                     clearing.                                                                 */
#define  CFGTMR_FMSEL_FCTRLMSEL_10                 2U     /* 10 : Fault control is enabled for all channelsU and the selected
                                                       mode is the manual fault clearing.                                        */
#define  CFGTMR_FMSEL_FCTRLMSEL_11                 3U     /* 11 : Fault control is enabled for all channelsU and the selected
                                                       mode is the automatic fault clearing.                                     */


/* ===============================================  CFGTMR FMSEL FCTRLIEN [7..7]  =============================================== */
                                 /* CFGTMR_FMSEL_FCTRLIEN                                                        */
#define  CFGTMR_FMSEL_FCTRLIEN_0                   0U     /* 0 : Fault control interrupt is disabled.                                  */
#define  CFGTMR_FMSEL_FCTRLIEN_1                   1U     /* 1 : Fault control interrupt is enabled.                                   */


/* ==========================================================  SYN  ========================================================== */
/* ===============================================  CFGTMR SYN MINLPEN [0..0]  ================================================ */
                                 /* CFGTMR_SYN_MINLPEN                                                         */
#define  CFGTMR_SYN_MINLPEN_0                    0U     /* 0 : The minimum loading point is disabled.                                */
#define  CFGTMR_SYN_MINLPEN_1                    1U     /* 1 : The minimum loading point is enabled.                                 */


/* ===============================================  CFGTMR SYN MAXLPEN [1..1]  ================================================ */
                                 /* CFGTMR_SYN_MAXLPEN                                                         */
#define  CFGTMR_SYN_MAXLPEN_0                    0U     /* 0 : The maximum loading point is disabled.                                */
#define  CFGTMR_SYN_MAXLPEN_1                    1U     /* 1 : The maximum loading point is enabled.                                 */


/* ==============================================  CFGTMR SYN CFGTMRCRINT [2..2]  =============================================== */
                                 /* CFGTMR_SYN_CFGTMRCRINT                                                       */
#define  CFGTMR_SYN_CFGTMRCRINT_0                  0U     /* 0 : CFGTMR counter continues to count normally.                              */
#define  CFGTMR_SYN_CFGTMRCRINT_1                  1U     /* 1 : CFGTMR counter is updated with its initial value when the selected
                                                     trigger is detected.                                                      */


/* ===============================================  CFGTMR SYN OVSMSEL [3..3]  ================================================ */
                                 /* CFGTMR_SYN_OVSMSEL                                                         */
#define  CFGTMR_SYN_OVSMSEL_0                    0U     /* 0 : OUTMASK register is updated with the value of its buffer
                                                        in all rising edges of the CFGTMR input clock.                               */
#define  CFGTMR_SYN_OVSMSEL_1                    1U     /* 1 : OUTMASK register is updated with the value of its buffer
                                                        only by the PWM synchronization.                                          */


/* ===============================================  CFGTMR SYN HWT0SEL [4..4]  ================================================ */
                                 /* CFGTMR_SYN_HWT0SEL                                                         */
#define  CFGTMR_SYN_HWT0SEL_0                    0U     /* 0 : Trigger is disabled.                                                  */
#define  CFGTMR_SYN_HWT0SEL_1                    1U     /* 1 : Trigger is enabled.                                                   */


/* ===============================================  CFGTMR SYN HWT1SEL [5..5]  ================================================ */
                                 /* CFGTMR_SYN_HWT1SEL                                                         */
#define  CFGTMR_SYN_HWT1SEL_0                    0U     /* 0 : Trigger is disabled.                                                  */
#define  CFGTMR_SYN_HWT1SEL_1                    1U     /* 1 : Trigger is enabled.                                                   */


/* ===============================================  CFGTMR SYN HWT2SEL [6..6]  ================================================ */
                                 /* CFGTMR_SYN_HWT2SEL                                                         */
#define  CFGTMR_SYN_HWT2SEL_0                    0U     /* 0 : Trigger is disabled.                                                  */
#define  CFGTMR_SYN_HWT2SEL_1                    1U     /* 1 : Trigger is enabled.                                                   */


/* ================================================  CFGTMR SYN SWTSEL [7..7]  ================================================ */
                                 /* CFGTMR_SYN_SWTSEL                                                          */
#define  CFGTMR_SYN_SWTSEL_0                     0U     /* 0 : Software trigger is not selected.                                     */
#define  CFGTMR_SYN_SWTSEL_1                     1U     /* 1 : Software trigger is selected.                                         */


/* =========================================================  CHOI  ========================================================== */
/* ===============================================  CFGTMR CHOI CHOISEL0 [0..0]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL0                                                        */
#define  CFGTMR_CHOI_CHOISEL0_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL0_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL1 [1..1]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL1                                                        */
#define  CFGTMR_CHOI_CHOISEL1_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL1_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL2 [2..2]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL2                                                        */
#define  CFGTMR_CHOI_CHOISEL2_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL2_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL3 [3..3]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL3                                                        */
#define  CFGTMR_CHOI_CHOISEL3_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL3_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL4 [4..4]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL4                                                        */
#define  CFGTMR_CHOI_CHOISEL4_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL4_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL5 [5..5]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL5                                                        */
#define  CFGTMR_CHOI_CHOISEL5_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL5_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL6 [6..6]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL6                                                        */
#define  CFGTMR_CHOI_CHOISEL6_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL6_1                   1U     /* 1 : The initialization value is 1.                                        */

/* ===============================================  CFGTMR CHOI CHOISEL7 [7..7]  =============================================== */
                                 /* CFGTMR_CHOI_CHOISEL7                                                        */
#define  CFGTMR_CHOI_CHOISEL7_0                   0U     /* 0 : The initialization value is 0.                                        */
#define  CFGTMR_CHOI_CHOISEL7_1                   1U     /* 1 : The initialization value is 1.                                        */


/* =========================================================  OMASK  ========================================================= */
/* ==============================================  CFGTMR OMASK CHOMASK0 [0..0]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK0                                                       */
#define  CFGTMR_OMASK_CHOMASK0_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK0_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */

/* ==============================================  CFGTMR OMASK CHOMASK1 [1..1]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK1                                                       */
#define  CFGTMR_OMASK_CHOMASK1_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK1_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK2 [2..2]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK2                                                       */
#define  CFGTMR_OMASK_CHOMASK2_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK2_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK3 [3..3]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK3                                                       */
#define  CFGTMR_OMASK_CHOMASK3_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK3_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK4 [4..4]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK4                                                       */
#define  CFGTMR_OMASK_CHOMASK4_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK4_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK5 [5..5]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK5                                                       */
#define  CFGTMR_OMASK_CHOMASK5_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK5_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK6 [6..6]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK6                                                       */
#define  CFGTMR_OMASK_CHOMASK6_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK6_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */
/* ==============================================  CFGTMR OMASK CHOMASK7 [7..7]  =============================================== */
                                 /* CFGTMR_OMASK_CHOMASK7                                                       */
#define  CFGTMR_OMASK_CHOMASK7_0                  0U     /* 0 : Channel output is not masked. It continues to operate normally.       */
#define  CFGTMR_OMASK_CHOMASK7_1                  1U     /* 1 : Channel output is masked. It is forced to its inactive state.         */

/* =========================================================  FLCH  ========================================================== */
/* ================================================  CFGTMR FLCH CCHO0 [1..1]  ================================================ */
                                 /* CFGTMR_FLCH_CCHO0                                                          */
#define  CFGTMR_FLCH_CCHO0_0                     0U     /* 0 : The channel (n+1) output is the same as the channel (n)
                                                       output.                                                                   */
#define  CFGTMR_FLCH_CCHO0_1                     1U     /* 1 : The channel (n+1) output is the complement of the channel
                                                        (n) output.                                                               */


/* ===============================================  CFGTMR FLCH DECSTS0 [3..3]  =============================================== */
                                 /* CFGTMR_FLCH_DECSTS0                                                        */
#define  CFGTMR_FLCH_DECSTS0_0                   0U     /* 0 : The dual edge captures are inactive.                                  */
#define  CFGTMR_FLCH_DECSTS0_1                   1U     /* 1 : The dual edge captures are active.                                    */


/* ===============================================  CFGTMR FLCH DTIEN0 [4..4]  ================================================ */
                                 /* CFGTMR_FLCH_DTIEN0                                                         */
#define  CFGTMR_FLCH_DTIEN0_0                    0U     /* 0 : The deadtime insertion in this pair of channels is disabled.          */
#define  CFGTMR_FLCH_DTIEN0_1                    1U     /* 1 : The deadtime insertion in this pair of channels is enabled.           */


/* ==============================================  CFGTMR FLCH PWMSYNEN0 [5..5]  ============================================== */
                                 /* CFGTMR_FLCH_PWMSYNEN0                                                      */
#define  CFGTMR_FLCH_PWMSYNEN0_0                 0U     /* 0 : The PWM synchronization in this pair of channels is disabled.         */
#define  CFGTMR_FLCH_PWMSYNEN0_1                 1U     /* 1 : The PWM synchronization in this pair of channels is enabled.          */


/* ==============================================  CFGTMR FLCH FCTRLEN0 [6..6]  =============================================== */
                                 /* CFGTMR_FLCH_FCTRLEN0                                                       */
#define  CFGTMR_FLCH_FCTRLEN0_0                  0U     /* 0 : The fault control in this pair of channels is disabled.               */
#define  CFGTMR_FLCH_FCTRLEN0_1                  1U     /* 1 : The fault control in this pair of channels is enabled.                */

/* ================================================  CFGTMR FLCH CCHO1 [9..9]  ================================================ */
                                 /* CFGTMR_FLCH_CCHO1                                                          */
#define  CFGTMR_FLCH_CCHO1_0                     0U     /* 0 : The channel (n+1) output is the same as the channel (n)
                                                       output.                                                                   */
#define  CFGTMR_FLCH_CCHO1_1                     1U     /* 1 : The channel (n+1) output is the complement of the channel
                                                     (n) output.                                                               */


/* ==============================================  CFGTMR FLCH DECSTS1 [11..11]  ============================================== */
                                 /* CFGTMR_FLCH_DECSTS1                                                        */
#define  CFGTMR_FLCH_DECSTS1_0                   0U     /* 0 : The dual edge captures are inactive.                                  */
#define  CFGTMR_FLCH_DECSTS1_1                   1U     /* 1 : The dual edge captures are active.                                    */


/* ==============================================  CFGTMR FLCH DTIEN1 [12..12]  =============================================== */
                                 /* CFGTMR_FLCH_DTIEN1                                                         */
#define  CFGTMR_FLCH_DTIEN1_0                    0U     /* 0 : The deadtime insertion in this pair of channels is disabled.          */
#define  CFGTMR_FLCH_DTIEN1_1                    1U     /* 1 : The deadtime insertion in this pair of channels is enabled.           */


/* =============================================  CFGTMR FLCH PWMSYNEN1 [13..13]  ============================================= */
                                 /* CFGTMR_FLCH_PWMSYNEN1                                                      */
#define  CFGTMR_FLCH_PWMSYNEN1_0                 0U     /* 0 : The PWM synchronization in this pair of channels is disabled.         */
#define  CFGTMR_FLCH_PWMSYNEN1_1                 1U     /* 1 : The PWM synchronization in this pair of channels is enabled.          */


/* =============================================  CFGTMR FLCH FCTRLEN1 [14..14]  ============================================== */
                                 /* CFGTMR_FLCH_FCTRLEN1                                                       */
#define  CFGTMR_FLCH_FCTRLEN1_0                  0U     /* 0 : The fault control in this pair of channels is disabled.               */
#define  CFGTMR_FLCH_FCTRLEN1_1                  1U     /* 1 : The fault control in this pair of channels is enabled.                */


/* ===============================================  CFGTMR FLCH CCHO2 [17..17]  =============================================== */
                                 /* CFGTMR_FLCH_CCHO2                                                          */
#define  CFGTMR_FLCH_CCHO2_0                     0U     /* 0 : The channel (n+1) output is the same as the channel (n)
                                                        output.                                                                   */
#define  CFGTMR_FLCH_CCHO2_1                     1U     /* 1 : The channel (n+1) output is the complement of the channel
                                                        (n) output.                                                               */


/* ==============================================  CFGTMR FLCH DECSTS2 [19..19]  ============================================== */
                                 /* CFGTMR_FLCH_DECSTS2                                                        */
#define  CFGTMR_FLCH_DECSTS2_0                   0U     /* 0 : The dual edge captures are inactive.                                  */
#define  CFGTMR_FLCH_DECSTS2_1                   1U     /* 1 : The dual edge captures are active.                                    */


/* ==============================================  CFGTMR FLCH DTIEN2 [20..20]  =============================================== */
                                 /* CFGTMR_FLCH_DTIEN2                                                         */
#define  CFGTMR_FLCH_DTIEN2_0                    0U     /* 0 : The deadtime insertion in this pair of channels is disabled.          */
#define  CFGTMR_FLCH_DTIEN2_1                    1U     /* 1 : The deadtime insertion in this pair of channels is enabled.           */


/* =============================================  CFGTMR FLCH PWMSYNEN2 [21..21]  ============================================= */
                                 /* CFGTMR_FLCH_PWMSYNEN2                                                      */
#define  CFGTMR_FLCH_PWMSYNEN2_0                 0U     /* 0 : The PWM synchronization in this pair of channels is disabled.         */
#define  CFGTMR_FLCH_PWMSYNEN2_1                 1U     /* 1 : The PWM synchronization in this pair of channels is enabled.          */


/* =============================================  CFGTMR FLCH FCTRLEN2 [22..22]  ============================================== */
                                 /* CFGTMR_FLCH_FCTRLEN2                                                       */
#define  CFGTMR_FLCH_FCTRLEN2_0                  0U     /* 0 : The fault control in this pair of channels is disabled.               */
#define  CFGTMR_FLCH_FCTRLEN2_1                  1U     /* 1 : The fault control in this pair of channels is enabled.                */


/* ===============================================  CFGTMR FLCH CCHO3 [25..25]  =============================================== */
                                 /* CFGTMR_FLCH_CCHO3                                                          */
#define  CFGTMR_FLCH_CCHO3_0                     0U     /* 0 : The channel (n+1) output is the same as the channel (n)
                                                         output.                                                                   */
#define  CFGTMR_FLCH_CCHO3_1                     1U     /* 1 : The channel (n+1) output is the complement of the channel
                                                        (n) output.                                                               */


/* ==============================================  CFGTMR FLCH DECSTS3 [27..27]  ============================================== */
                                 /* CFGTMR_FLCH_DECSTS3                                                        */
#define  CFGTMR_FLCH_DECSTS3_0                   0U     /* 0 : The dual edge captures are inactive.                                  */
#define  CFGTMR_FLCH_DECSTS3_1                   1U     /* 1 : The dual edge captures are active.                                    */


/* ==============================================  CFGTMR FLCH DTIEN3 [28..28]  =============================================== */
                                 /* CFGTMR_FLCH_DTIEN3                                                         */
#define  CFGTMR_FLCH_DTIEN3_0                    0U     /* 0 : The deadtime insertion in this pair of channels is disabled.          */
#define  CFGTMR_FLCH_DTIEN3_1                    1U     /* 1 : The deadtime insertion in this pair of channels is enabled.           */


/* =============================================  CFGTMR FLCH PWMSYNEN3 [29..29]  ============================================= */
                                 /* CFGTMR_FLCH_PWMSYNEN3                                                      */
#define  CFGTMR_FLCH_PWMSYNEN3_0                 0U     /* 0 : The PWM synchronization in this pair of channels is disabled.         */
#define  CFGTMR_FLCH_PWMSYNEN3_1                 1U     /* 1 : The PWM synchronization in this pair of channels is enabled.          */


/* =============================================  CFGTMR FLCH FCTRLEN3 [30..30]  ============================================== */
                                 /* CFGTMR_FLCH_FCTRLEN3                                                       */
#define  CFGTMR_FLCH_FCTRLEN3_0                  0U     /* 0 : The fault control in this pair of channels is disabled.               */
#define  CFGTMR_FLCH_FCTRLEN3_1                  1U     /* 1 : The fault control in this pair of channels is enabled.                */


/* =========================================================  DCFG  ========================================================== */
/* ================================================  CFGTMR DCFG DPSCCFG [6..7]  ================================================ */
                                 /* CFGTMR_DCFG_DPSCCFG                                                          */
#define  CFGTMR_DCFG_DPSCCFG_00                  0U     /* 00 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_DCFG_DPSCCFG_01                  1U     /* 01 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_DCFG_DPSCCFG_10                  2U     /* 10 : Divide the CFGTMR input clock by 4.                                     */
#define  CFGTMR_DCFG_DPSCCFG_11                  3U     /* 11 : Divide the CFGTMR input clock by 16.                                    */


/* ========================================================  EXTTRG  ========================================================= */
/* ============================================  CFGTMR EXTTRG EXTTRGENCH2 [0..0]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH2                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH2_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH2_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH3 [1..1]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH3                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH3_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH3_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH4 [2..2]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH4                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH4_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH4_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH5 [3..3]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH5                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH5_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH5_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH0 [4..4]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH0                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH0_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH0_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH1 [5..5]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH1                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH1_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH1_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* =============================================  CFGTMR EXTTRG INITTRGEN [6..6]  ============================================= */
                                 /* CFGTMR_EXTTRG_INITTRGEN                                                    */
#define  CFGTMR_EXTTRG_INITTRGEN_0               0U     /* 0 : The generation of initialization trigger is disabled.                 */
#define  CFGTMR_EXTTRG_INITTRGEN_1               1U     /* 1 : The generation of initialization trigger is enabled.                  */

/* =============================================  CFGTMR EXTTRG CHTRGFLG [7..7]  ============================================== */
                                 /* CFGTMR_EXTTRG_CHTRGFLG                                                     */
#define  CFGTMR_EXTTRG_CHTRGFLG_0                0U     /* 0 : No channel trigger was generated.                                     */
#define  CFGTMR_EXTTRG_CHTRGFLG_1                1U     /* 1 : A channel trigger was generated.                                      */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH6 [8..8]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH6                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH6_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH6_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* ============================================  CFGTMR EXTTRG EXTTRGENCH7 [9..9]  ============================================ */
                                 /* CFGTMR_EXTTRG_EXTTRGENCH7                                                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH7_0             0U     /* 0 : The generation of this external trigger is disabled.                  */
#define  CFGTMR_EXTTRG_EXTTRGENCH7_1             1U     /* 1 : The generation of this external trigger is enabled.                   */


/* =========================================================  CHPOL  ========================================================= */
/* ===============================================  CFGTMR CHPOL CHPOL0 [0..0]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL0                                                         */
#define  CFGTMR_CHPOL_CHPOL0_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL0_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL1 [1..1]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL1                                                         */
#define  CFGTMR_CHPOL_CHPOL1_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL1_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL2 [2..2]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL2                                                         */
#define  CFGTMR_CHPOL_CHPOL2_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL2_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL3 [3..3]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL3                                                         */
#define  CFGTMR_CHPOL_CHPOL3_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL3_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL4 [4..4]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL4                                                         */
#define  CFGTMR_CHPOL_CHPOL4_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL4_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL5 [5..5]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL5                                                         */
#define  CFGTMR_CHPOL_CHPOL5_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL5_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL [6..6]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL6                                                         */
#define  CFGTMR_CHPOL_CHPOL6_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL6_1                    1U     /* 1 : The channel polarity is active low.                                   */

/* ===============================================  CFGTMR CHPOL CHPOL7 [7..7]  ================================================ */
                                 /* CFGTMR_CHPOL_CHPOL7                                                         */
#define  CFGTMR_CHPOL_CHPOL7_0                    0U     /* 0 : The channel polarity is active high.                                  */
#define  CFGTMR_CHPOL_CHPOL7_1                    1U     /* 1 : The channel polarity is active low.                                   */


/* =========================================================  FMSTS  ========================================================= */
/* ==============================================  CFGTMR FMSTS FIDFLG0 [0..0]  =============================================== */
                                 /* CFGTMR_FMSTS_FIDFLG0                                                       */
#define  CFGTMR_FMSTS_FIDFLG0_0                  0U     /* 0 : No fault condition was detected at the fault input.                   */
#define  CFGTMR_FMSTS_FIDFLG0_1                  1U     /* 1 : A fault condition was detected at the fault input.                    */


/* ==============================================  CFGTMR FMSTS FIDFLG1 [1..1]  =============================================== */
                                 /* CFGTMR_FMSTS_FIDFLG1                                                       */
#define  CFGTMR_FMSTS_FIDFLG1_0                  0U     /* 0 : No fault condition was detected at the fault input.                   */
#define  CFGTMR_FMSTS_FIDFLG1_1                  1U     /* 1 : A fault condition was detected at the fault input.                    */


/* ==============================================  CFGTMR FMSTS FIDFLG2 [2..2]  =============================================== */
                                 /* CFGTMR_FMSTS_FIDFLG2                                                       */
#define  CFGTMR_FMSTS_FIDFLG2_0                  0U     /* 0 : No fault condition was detected at the fault input.                   */
#define  CFGTMR_FMSTS_FIDFLG2_1                  1U     /* 1 : A fault condition was detected at the fault input.                    */


/* ==============================================  CFGTMR FMSTS FIDFLG3 [3..3]  =============================================== */
                                 /* CFGTMR_FMSTS_FIDFLG3                                                       */
#define  CFGTMR_FMSTS_FIDFLG3_0                  0U     /* 0 : No fault condition was detected at the fault input.                   */
#define  CFGTMR_FMSTS_FIDFLG3_1                  1U     /* 1 : A fault condition was detected at the fault input.                    */


/* ===============================================  CFGTMR FMSTS FICTRL [5..5]  =============================================== */
                                 /* CFGTMR_FMSTS_FICTRL                                                        */
#define  CFGTMR_FMSTS_FICTRL_0                   0U     /* 0 : The logic OR of the enabled fault inputs is 0.                        */
#define  CFGTMR_FMSTS_FICTRL_1                   1U     /* 1 : The logic OR of the enabled fault inputs is 1.                        */


/* ================================================  CFGTMR FMSTS WPEN [6..6]  ================================================ */
                                 /* CFGTMR_FMSTS_WPEN                                                          */
#define  CFGTMR_FMSTS_WPEN_0                     0U     /* 0 : Write protection is disabled. Write protected bits can be
                                                       written.                                                                  */
#define  CFGTMR_FMSTS_WPEN_1                     1U     /* 1 : Write protection is enabled. Write protected bits cannot
                                                        be written.                                                               */


/* ===============================================  CFGTMR FMSTS FCDFLG [7..7]  =============================================== */
                                 /* CFGTMR_FMSTS_FCDFLG                                                        */
#define  CFGTMR_FMSTS_FCDFLG_0                   0U     /* 0 : No fault condition was detected.                                      */
#define  CFGTMR_FMSTS_FCDFLG_1                   1U     /* 1 : A fault condition was detected.                                       */


/* ========================================================  ICFCTRL  ======================================================== */
/* =========================================================  FCTRL  ========================================================= */
/* ===============================================  CFGTMR FCTRL FIEN0 [0..0]  ================================================ */
                                 /* CFGTMR_FCTRL_FIEN0                                                         */
#define  CFGTMR_FCTRL_FIEN0_0                    0U     /* 0 : Fault input is disabled.                                              */
#define  CFGTMR_FCTRL_FIEN0_1                    1U     /* 1 : Fault input is enabled.                                               */


/* ===============================================  CFGTMR FCTRL FIEN1 [1..1]  ================================================ */
                                 /* CFGTMR_FCTRL_FIEN1                                                         */
#define  CFGTMR_FCTRL_FIEN1_0                    0U     /* 0 : Fault input is disabled.                                              */
#define  CFGTMR_FCTRL_FIEN1_1                    1U     /* 1 : Fault input is enabled.                                               */


/* ===============================================  CFGTMR FCTRL FIEN2 [2..2]  ================================================ */
                                 /* CFGTMR_FCTRL_FIEN2                                                         */
#define  CFGTMR_FCTRL_FIEN2_0                    0U     /* 0 : Fault input is disabled.                                              */
#define  CFGTMR_FCTRL_FIEN2_1                    1U     /* 1 : Fault input is enabled.                                               */


/* ===============================================  CFGTMR FCTRL FIEN3 [3..3]  ================================================ */
                                 /* CFGTMR_FCTRL_FIEN3                                                         */
#define  CFGTMR_FCTRL_FIEN3_0                    0U     /* 0 : Fault input is disabled.                                              */
#define  CFGTMR_FCTRL_FIEN3_1                    1U     /* 1 : Fault input is enabled.                                               */


/* ===============================================  CFGTMR FCTRL FIFEN0 [4..4]  =============================================== */
                                 /* CFGTMR_FCTRL_FIFEN0                                                        */
#define  CFGTMR_FCTRL_FIFEN0_0                   0U     /* 0 : Fault input filter is disabled.                                       */
#define  CFGTMR_FCTRL_FIFEN0_1                   1U     /* 1 : Fault input filter is enabled.                                        */


/* ===============================================  CFGTMR FCTRL FIFEN1 [5..5]  =============================================== */
                                 /* CFGTMR_FCTRL_FIFEN1                                                        */
#define  CFGTMR_FCTRL_FIFEN1_0                   0U     /* 0 : Fault input filter is disabled.                                       */
#define  CFGTMR_FCTRL_FIFEN1_1                   1U     /* 1 : Fault input filter is enabled.                                        */


/* ===============================================  CFGTMR FCTRL FIFEN2 [6..6]  =============================================== */
                                 /* CFGTMR_FCTRL_FIFEN2                                                        */
#define  CFGTMR_FCTRL_FIFEN2_0                   0U     /* 0 : Fault input filter is disabled.                                       */
#define  CFGTMR_FCTRL_FIFEN2_1                   1U     /* 1 : Fault input filter is enabled.                                        */


/* ===============================================  CFGTMR FCTRL FIFEN3 [7..7]  =============================================== */
                                 /* CFGTMR_FCTRL_FIFEN3                                                        */
#define  CFGTMR_FCTRL_FIFEN3_0                   0U     /* 0 : Fault input filter is disabled.                                       */
#define  CFGTMR_FCTRL_FIFEN3_1                   1U     /* 1 : Fault input filter is enabled.                                        */


/* ==============================================  CFGTMR FCTRL FEOSTS [15..15]  ============================================== */
                                 /* CFGTMR_FCTRL_FEOSTS                                                        */
#define  CFGTMR_FCTRL_FEOSTS_0                   0U     /* 0 : CFGTMR outputs will be placed into safe values when fault events
                                                        in ongoing (defined by POL bits).                                         */
#define  CFGTMR_FCTRL_FEOSTS_1                   1U     /* 1 : CFGTMR outputs will be tri-stated when fault event is ongoing            */


/* ========================================================  QDCSTS  ========================================================= */
/* ===============================================  CFGTMR QDCSTS QDMEN [0..0]  =============================================== */
                                 /* CFGTMR_QDCSTS_QDMEN                                                        */
#define  CFGTMR_QDCSTS_QDMEN_0                   0U     /* 0 : Quadrature Decoder mode is disabled.                                  */
#define  CFGTMR_QDCSTS_QDMEN_1                   1U     /* 1 : Quadrature Decoder mode is enabled.                                   */


/* =============================================  CFGTMR QDCSTS TMRODSEL [1..1]  ============================================== */
                                 /* CFGTMR_QDCSTS_TMRODSEL                                                     */
#define  CFGTMR_QDCSTS_TMRODSEL_0                0U     /* 0 : TOF bit was set on the bottom of counting. There was an
                                                         CFGTMR counter decrement and CFGTMR counter changes from its
                                                     minimum value (CNTIN register) to its maximum value (MOD
                                                     register).                                                                */
#define  CFGTMR_QDCSTS_TMRODSEL_1                1U     /* 1 : TOF bit was set on the top of counting. There was an CFGTMR
                                                        counter increment and CFGTMR counter changes from its maximum
                                                     value (MOD register) to its minimum value (CNTIN register).               */


/* ==============================================  CFGTMR QDCSTS CNTDIR [2..2]  =============================================== */
                                 /* CFGTMR_QDCSTS_CNTDIR                                                       */
#define  CFGTMR_QDCSTS_CNTDIR_0                  0U     /* 0 : Counting direction is decreasing (CFGTMR counter decrement).             */
#define  CFGTMR_QDCSTS_CNTDIR_1                  1U     /* 1 : Counting direction is increasing (CFGTMR counter increment).             */


/* ===============================================  CFGTMR QDCSTS EMSEL [3..3]  =============================================== */
                                 /* CFGTMR_QDCSTS_EMSEL                                                        */
#define  CFGTMR_QDCSTS_EMSEL_0                   0U     /* 0 : Phase A and phase B encoding mode.                                    */
#define  CFGTMR_QDCSTS_EMSEL_1                   1U     /* 1 : Count and direction encoding mode.                                    */


/* ==============================================  CFGTMR QDCSTS PBISPOL [4..4]  ============================================== */
                                 /* CFGTMR_QDCSTS_PBISPOL                                                      */
#define  CFGTMR_QDCSTS_PBISPOL_0                 0U     /* 0 : Normal polarity. Phase B input signal is not inverted before
                                                        identifying the rising and falling edges of this signal.                  */
#define  CFGTMR_QDCSTS_PBISPOL_1                 1U     /* 1 : Inverted polarity. Phase B input signal is inverted before
                                                      identifying the rising and falling edges of this signal.                  */


/* ==============================================  CFGTMR QDCSTS PAISPOL [5..5]  ============================================== */
                                 /* CFGTMR_QDCSTS_PAISPOL                                                      */
#define  CFGTMR_QDCSTS_PAISPOL_0                 0U     /* 0 : Normal polarity. Phase A input signal is not inverted before
                                                         identifying the rising and falling edges of this signal.                  */
#define  CFGTMR_QDCSTS_PAISPOL_1                 1U     /* 1 : Inverted polarity. Phase A input signal is inverted before
                                                      identifying the rising and falling edges of this signal.                  */


/* ==============================================  CFGTMR QDCSTS PBIFEN [6..6]  =============================================== */
                                 /* CFGTMR_QDCSTS_PBIFEN                                                       */
#define  CFGTMR_QDCSTS_PBIFEN_0                  0U     /* 0 : Phase B input filter is disabled.                                     */
#define  CFGTMR_QDCSTS_PBIFEN_1                  1U     /* 1 : Phase B input filter is enabled.                                      */


/* ==============================================  CFGTMR QDCSTS PAIFEN [7..7]  =============================================== */
                                 /* CFGTMR_QDCSTS_PAIFEN                                                       */
#define  CFGTMR_QDCSTS_PAIFEN_0                  0U     /* 0 : Phase A input filter is disabled.                                     */
#define  CFGTMR_QDCSTS_PAIFEN_1                  1U     /* 1 : Phase A input filter is enabled.                                      */


/* ==========================================================  CFG  ========================================================== */
/* =============================================  CFGTMR CFG INITTRGRP [11..11]  ============================================== */
                                 /* CFGTMR_CFG_INITTRGRP                                                       */
#define  CFGTMR_CFG_INITTRGRP_0                  0U     /* 0 : Initialization trigger is generated on counter wrap events.           */
#define  CFGTMR_CFG_INITTRGRP_1                  1U     /* 1 : Initialization trigger is generated when a reload point
                                                     is reached.                                                               */


/* ==========================================================  FIPOLSEL  ========================================================== */
/* ==============================================  CFGTMR FIPOLSEL FIPOLSEL0 [0..0]  =============================================== */
                                 /* CFGTMR_FIPOLSEL_FIPOLSEL0                                                       */
#define  CFGTMR_FIPOLSEL_FIPOLSEL0_0                  0U     /* 0 : The fault input polarity is active high. A 1 at the fault
                                                    input indicates a fault.                                                  */
#define  CFGTMR_FIPOLSEL_FIPOLSEL0_1                  1U     /* 1 : The fault input polarity is active low. A 0 at the fault
                                                       input indicates a fault.                                                  */


/* ==============================================  CFGTMR FIPOLSEL FIPOLSEL1 [1..1]  =============================================== */
                                 /* CFGTMR_FIPOLSEL_FIPOLSEL1                                                       */
#define  CFGTMR_FIPOLSEL_FIPOLSEL1_0                  0U     /* 0 : The fault input polarity is active high. A 1 at the fault
                                                       input indicates a fault.                                                  */
#define  CFGTMR_FIPOLSEL_FIPOLSEL1_1                  1U     /* 1 : The fault input polarity is active low. A 0 at the fault
                                                       input indicates a fault.                                                  */


/* ==============================================  CFGTMR FIPOLSEL FIPOLSEL2 [2..2]  =============================================== */
                                 /* CFGTMR_FIPOLSEL_FIPOLSEL2                                                       */
#define  CFGTMR_FIPOLSEL_FIPOLSEL2_0                  0U     /* 0 : The fault input polarity is active high. A 1 at the fault
                                                        input indicates a fault.                                                  */
#define  CFGTMR_FIPOLSEL_FIPOLSEL2_1                  1U     /* 1 : The fault input polarity is active low. A 0 at the fault
                                                      input indicates a fault.                                                  */


/* ==============================================  CFGTMR FIPOLSEL FIPOLSEL3 [3..3]  =============================================== */
                                 /* CFGTMR_FIPOLSEL_FIPOLSEL3                                                       */
#define  CFGTMR_FIPOLSEL_FIPOLSEL3_0                  0U     /* 0 : The fault input polarity is active high. A 1 at the fault
                                                       input indicates a fault.                                                  */
#define  CFGTMR_FIPOLSEL_FIPOLSEL3_1                  1U     /* 1 : The fault input polarity is active low. A 0 at the fault
                                                         input indicates a fault.                                                  */


/* ========================================================  SYNCFG  ========================================================= */
/* ==============================================  CFGTMR SYNCFG HWTRGD [0..0]  =============================================== */
                                 /* CFGTMR_SYNCFG_HWTRGD                                                       */
#define  CFGTMR_SYNCFG_HWTRGD_0                  0U     /* 0 : CFGTMR clears the TRIGj bit when the hardware trigger j is
                                                      detectedU where j   0U 1U2.                                               */
#define  CFGTMR_SYNCFG_HWTRGD_1                  1U     /* 1 : CFGTMR does not clear the TRIGj bit when the hardware trigger
                                                    j is detectedU where j   0U 1U2.                                          */


/* =============================================  CFGTMR SYNCFG INITVSYN [2..2]  ============================================== */
                                 /* CFGTMR_SYNCFG_INITVSYN                                                     */
#define  CFGTMR_SYNCFG_INITVSYN_0                0U     /* 0 : CNTIN register is updated with its buffer value at all rising
                                                        edges of CFGTMR input clock.                                                 */
#define  CFGTMR_SYNCFG_INITVSYN_1                1U     /* 1 : CNTIN register is updated with its buffer value by the PWM
                                                        synchronization.                                                          */


/* =============================================  CFGTMR SYNCFG ICTRLSYN [4..4]  ============================================== */
                                 /* CFGTMR_SYNCFG_ICTRLSYN                                                     */
#define  CFGTMR_SYNCFG_ICTRLSYN_0                0U     /* 0 : INVCTRL register is updated with its buffer value at all
                                                       rising edges of CFGTMR input clock.                                          */
#define  CFGTMR_SYNCFG_ICTRLSYN_1                1U     /* 1 : INVCTRL register is updated with its buffer value by the
                                                       PWM synchronization.                                                      */


/* ============================================  CFGTMR SYNCFG SWOCTRLSYN [5..5]  ============================================= */
                                 /* CFGTMR_SYNCFG_SWOCTRLSYN                                                   */
#define  CFGTMR_SYNCFG_SWOCTRLSYN_0              0U     /* 0 : SWOCTRL register is updated with its buffer value at all
                                                        rising edges of CFGTMR input clock.                                          */
#define  CFGTMR_SYNCFG_SWOCTRLSYN_1              1U     /* 1 : SWOCTRL register is updated with its buffer value by the
                                                         PWM synchronization.                                                      */


/* ==============================================  CFGTMR SYNCFG SYNMSEL [7..7]  ============================================== */
                                 /* CFGTMR_SYNCFG_SYNMSEL                                                      */
#define  CFGTMR_SYNCFG_SYNMSEL_0                 0U     /* 0 : Legacy PWM synchronization is selected.                               */
#define  CFGTMR_SYNCFG_SYNMSEL_1                 1U     /* 1 : Enhanced PWM synchronization is selected.                             */


/* ===============================================  CFGTMR SYNCFG SWTAC [8..8]  =============================================== */
                                 /* CFGTMR_SYNCFG_SWTAC                                                        */
#define  CFGTMR_SYNCFG_SWTAC_0                   0U     /* 0 : The software trigger does not activate the CFGTMR counter synchronization. */
#define  CFGTMR_SYNCFG_SWTAC_1                   1U     /* 1 : The software trigger activates the CFGTMR counter synchronization.       */


/* =============================================  CFGTMR SYNCFG SWTAWRBUF [9..9]  ============================================= */
                                 /* CFGTMR_SYNCFG_SWTAWRBUF                                                    */
#define  CFGTMR_SYNCFG_SWTAWRBUF_0               0U     /* 0 : The software trigger does not activate MODU HCRU CNTINU
                                                       and CV registers synchronization.                                         */
#define  CFGTMR_SYNCFG_SWTAWRBUF_1               1U     /* 1 : The software trigger activates MODU HCRU CNTINU and CV registers
                                                       synchronization.                                                          */


/* =============================================  CFGTMR SYNCFG SWTAOM [10..10]  ============================================== */
                                 /* CFGTMR_SYNCFG_SWTAOM                                                       */
#define  CFGTMR_SYNCFG_SWTAOM_0                  0U     /* 0 : The software trigger does not activate the OUTMASK register
                                                       synchronization.                                                          */
#define  CFGTMR_SYNCFG_SWTAOM_1                  1U     /* 1 : The software trigger activates the OUTMASK register synchronization.  */


/* ============================================  CFGTMR SYNCFG SWTAICTRL [11..11]  ============================================ */
                                 /* CFGTMR_SYNCFG_SWTAICTRL                                                    */
#define  CFGTMR_SYNCFG_SWTAICTRL_0               0U     /* 0 : The software trigger does not activate the INVCTRL register
                                                        synchronization.                                                          */
#define  CFGTMR_SYNCFG_SWTAICTRL_1               1U     /* 1 : The software trigger activates the INVCTRL register synchronization.  */


/* =============================================  CFGTMR SYNCFG SWTASWO [12..12]  ============================================= */
                                 /* CFGTMR_SYNCFG_SWTASWO                                                      */
#define  CFGTMR_SYNCFG_SWTASWO_0                 0U     /* 0 : The software trigger does not activate the SWOCTRL register
                                                         synchronization.                                                          */
#define  CFGTMR_SYNCFG_SWTASWO_1                 1U     /* 1 : The software trigger activates the SWOCTRL register synchronization.  */


/* ==============================================  CFGTMR SYNCFG HWTAC [16..16]  ============================================== */
                                 /* CFGTMR_SYNCFG_HWTAC                                                        */
#define  CFGTMR_SYNCFG_HWTAC_0                   0U     /* 0 : A hardware trigger does not activate the CFGTMR counter synchronization. */
#define  CFGTMR_SYNCFG_HWTAC_1                   1U     /* 1 : A hardware trigger activates the CFGTMR counter synchronization.         */


/* ============================================  CFGTMR SYNCFG HWTAWRBUF [17..17]  ============================================ */
                                 /* CFGTMR_SYNCFG_HWTAWRBUF                                                    */
#define  CFGTMR_SYNCFG_HWTAWRBUF_0               0U     /* 0 : A hardware trigger does not activate MODU HCRU CNTINU and
                                                        CV registers synchronization.                                             */
#define  CFGTMR_SYNCFG_HWTAWRBUF_1               1U     /* 1 : A hardware trigger activates MODU HCRU CNTINU and CV registers
                                                        synchronization.                                                          */


/* =============================================  CFGTMR SYNCFG HWTAOM [18..18]  ============================================== */
                                 /* CFGTMR_SYNCFG_HWTAOM                                                       */
#define  CFGTMR_SYNCFG_HWTAOM_0                  0U     /* 0 : A hardware trigger does not activate the OUTMASK register
                                                         synchronization.                                                          */
#define  CFGTMR_SYNCFG_HWTAOM_1                  1U     /* 1 : A hardware trigger activates the OUTMASK register synchronization.    */


/* ============================================  CFGTMR SYNCFG HWTAICTRL [19..19]  ============================================ */
                                 /* CFGTMR_SYNCFG_HWTAICTRL                                                    */
#define  CFGTMR_SYNCFG_HWTAICTRL_0               0U     /* 0 : A hardware trigger does not activate the INVCTRL register
                                                         synchronization.                                                          */
#define  CFGTMR_SYNCFG_HWTAICTRL_1               1U     /* 1 : A hardware trigger activates the INVCTRL register synchronization.    */


/* =============================================  CFGTMR SYNCFG HWTASWO [20..20]  ============================================= */
                                 /* CFGTMR_SYNCFG_HWTASWO                                                      */
#define  CFGTMR_SYNCFG_HWTASWO_0                 0U     /* 0 : A hardware trigger does not activate the SWOCTRL register
                                                         synchronization.                                                          */
#define  CFGTMR_SYNCFG_HWTASWO_1                 1U     /* 1 : A hardware trigger activates the SWOCTRL register synchronization.    */


/* =========================================================  ICTRL  ========================================================= */
/* ==============================================  CFGTMR ICTRL CHPIEN0 [0..0]  =============================================== */
                                 /* CFGTMR_ICTRL_CHPIEN0                                                       */
#define  CFGTMR_ICTRL_CHPIEN0_0                  0U     /* 0 : Inverting is disabled.                                                */
#define  CFGTMR_ICTRL_CHPIEN0_1                  1U     /* 1 : Inverting is enabled.                                                 */


/* ==============================================  CFGTMR ICTRL CHPIEN1 [1..1]  =============================================== */
                                 /* CFGTMR_ICTRL_CHPIEN1                                                       */
#define  CFGTMR_ICTRL_CHPIEN1_0                  0U     /* 0 : Inverting is disabled.                                                */
#define  CFGTMR_ICTRL_CHPIEN1_1                  1U     /* 1 : Inverting is enabled.                                                 */


/* ==============================================  CFGTMR ICTRL CHPIEN2 [2..2]  =============================================== */
                                 /* CFGTMR_ICTRL_CHPIEN2                                                       */
#define  CFGTMR_ICTRL_CHPIEN2_0                  0U     /* 0 : Inverting is disabled.                                                */
#define  CFGTMR_ICTRL_CHPIEN2_1                  1U     /* 1 : Inverting is enabled.                                                 */


/* ==============================================  CFGTMR ICTRL CHPIEN3 [3..3]  =============================================== */
                                 /* CFGTMR_ICTRL_CHPIEN3                                                       */
#define  CFGTMR_ICTRL_CHPIEN3_0                  0U     /* 0 : Inverting is disabled.                                                */
#define  CFGTMR_ICTRL_CHPIEN3_1                  1U     /* 1 : Inverting is enabled.                                                 */


/* ========================================================  SWOCTRL  ======================================================== */
/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN0 [0..0]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN0                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN0_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN0_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN1 [1..1]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN1                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN1_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN1_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN2 [2..2]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN2                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN2_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN2_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN3 [3..3]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN3                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN3_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN3_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN4 [4..4]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN4                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN4_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN4_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN5 [5..5]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN5                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN5_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN5_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN6 [6..6]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN6                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN6_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN6_1            1U     /* 1 : The channel output is affected by software output control.            */

/* ===========================================  CFGTMR SWOCTRL CHSWOCTRLEN7 [7..7]  ============================================ */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLEN7                                                 */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN7_0            0U     /* 0 : The channel output is not affected by software output control.        */
#define  CFGTMR_SWOCTRL_CHSWOCTRLEN7_1            1U     /* 1 : The channel output is affected by software output control.            */


/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL0 [8..8]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL0                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL0_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL0_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL1 [9..9]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL1                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL1_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL1_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL2 [10..10]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL2                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL2_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL2_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL3 [11..11]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL3                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL3_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL3_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL4 [12..12]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL4                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL4_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL4_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL5 [13..13]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL5                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL5_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL5_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL6 [14..14]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL6                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL6_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL6_1              1U     /* 1 : The software output control forces 1 to the channel output.           */

/* ============================================  CFGTMR SWOCTRL CHSWOCTRLVSEL7 [15..15]  ============================================= */
                                 /* CFGTMR_SWOCTRL_CHSWOCTRLVSEL7                                                   */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL7_0              0U     /* 0 : The software output control forces 0 to the channel output.           */
#define  CFGTMR_SWOCTRL_CHSWOCTRLVSEL7_1              1U     /* 1 : The software output control forces 1 to the channel output.           */



/* =========================================================  PWMLD  ========================================================= */
/* ===============================================  CFGTMR PWMLD CHMSEL0 [0..0]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL0                                                        */
#define  CFGTMR_PWMLD_CHMSEL0_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL0_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL1 [1..1]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL1                                                        */
#define  CFGTMR_PWMLD_CHMSEL1_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL1_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL2 [2..2]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL2                                                        */
#define  CFGTMR_PWMLD_CHMSEL2_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL2_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL3 [3..3]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL3                                                        */
#define  CFGTMR_PWMLD_CHMSEL3_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL3_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL4 [4..4]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL4                                                        */
#define  CFGTMR_PWMLD_CHMSEL4_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL4_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL5 [5..5]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL5                                                        */
#define  CFGTMR_PWMLD_CHMSEL5_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL5_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL6 [6..6]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL6                                                        */
#define  CFGTMR_PWMLD_CHMSEL6_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL6_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */

/* ===============================================  CFGTMR PWMLD CHMSEL7 [7..7]  =============================================== */
                                 /* CFGTMR_PWMLD_CHMSEL7                                                        */
#define  CFGTMR_PWMLD_CHMSEL7_0                   0U     /* 0 : Channel match is not included as a reload opportunity.                */
#define  CFGTMR_PWMLD_CHMSEL7_1                   1U     /* 1 : Channel match is included as a reload opportunity.                    */



/* ===============================================  CFGTMR PWMLD HCREN [8..8]  ================================================ */
                                 /* CFGTMR_PWMLD_HCREN                                                         */
#define  CFGTMR_PWMLD_HCREN_0                    0U     /* 0 : Half cycle reload is disabled and it is not considered as
                                                        a reload opportunity.                                                     */
#define  CFGTMR_PWMLD_HCREN_1                    1U     /* 1 : Half cycle reload is enabled and it is considered as a reload
                                                        opportunity.                                                              */


/* ===============================================  CFGTMR PWMLD LUVEN [9..9]  ================================================ */
                                 /* CFGTMR_PWMLD_LUVEN                                                         */
#define  CFGTMR_PWMLD_LUVEN_0                    0U     /* 0 : Loading updated values is disabled.                                   */
#define  CFGTMR_PWMLD_LUVEN_1                    1U     /* 1 : Loading updated values is enabled.                                    */


/* ==============================================  CFGTMR PWMLD GLOKEN [10..10]  ============================================== */
                                 /* CFGTMR_PWMLD_GLOKEN                                                        */
#define  CFGTMR_PWMLD_GLOKEN_0                   0U     /* 0 : Global Load Ok disabled.                                              */
#define  CFGTMR_PWMLD_GLOKEN_1                   1U     /* 1 : Global Load OK enabled. A pulse event on the module global
                                                     load input sets the LDOK bit.                                             */


/* ===============================================  CFGTMR PWMLD GLOP [11..11]  =============================================== */
                                 /* CFGTMR_PWMLD_GLOP                                                          */
#define  CFGTMR_PWMLD_GLOP_0                     0U     /* 0 : No action.                                                            */
#define  CFGTMR_PWMLD_GLOP_1                     1U     /* 1 : LDOK bit is set.                                                      */


/* ==========================================================  HC  =========================================================== */
/* ========================================================  P0DCFG  ========================================================= */
/* ==============================================  CFGTMR P0DCFG PSCCFG [6..7]  =============================================== */
                                 /* CFGTMR_PDCFG_PDCFG_P0DCFG_PSCCFG                                           */
#define  CFGTMR_PDCFG_PDCFG_P0DCFG_PSCCFG_0x_0   0U     /* 0x_0 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P0DCFG_PSCCFG_0x_1   1U     /* 0x_1 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P0DCFG_PSCCFG_10     2U     /* 10 : Divide the CFGTMR input clock by 4.                                     */
#define  CFGTMR_PDCFG_PDCFG_P0DCFG_PSCCFG_11     3U     /* 11 : Divide the CFGTMR input clock by 16.                                    */


/* ========================================================  P1DCFG  ========================================================= */
/* ==============================================  CFGTMR P1DCFG PSCCFG [6..7]  =============================================== */
                                 /* CFGTMR_PDCFG_PDCFG_P1DCFG_PSCCFG                                           */
#define  CFGTMR_PDCFG_PDCFG_P1DCFG_PSCCFG_0x_0   0U     /* 0x_0 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P1DCFG_PSCCFG_0x_1   1U     /* 0x_1 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P1DCFG_PSCCFG_10     2U     /* 10 : Divide the CFGTMR input clock by 4.                                     */
#define  CFGTMR_PDCFG_PDCFG_P1DCFG_PSCCFG_11     3U     /* 11 : Divide the CFGTMR input clock by 16.                                    */


/* ========================================================  P2DCFG  ========================================================= */
/* ==============================================  CFGTMR P2DCFG PSCCFG [6..7]  =============================================== */
                                 /* CFGTMR_PDCFG_PDCFG_P2DCFG_PSCCFG                                           */
#define  CFGTMR_PDCFG_PDCFG_P2DCFG_PSCCFG_0x_0   0U     /* 0x_0 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P2DCFG_PSCCFG_0x_1   1U     /* 0x_1 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P2DCFG_PSCCFG_10     2U     /* 10 : Divide the CFGTMR input clock by 4.                                     */
#define  CFGTMR_PDCFG_PDCFG_P2DCFG_PSCCFG_11     3U     /* 11 : Divide the CFGTMR input clock by 16.                                    */


/* ========================================================  P3DCFG  ========================================================= */
/* ==============================================  CFGTMR P3DCFG PSCCFG [6..7]  =============================================== */
                                 /* CFGTMR_PDCFG_PDCFG_P3DCFG_PSCCFG                                           */
#define  CFGTMR_PDCFG_PDCFG_P3DCFG_PSCCFG_0x_0   0U     /* 0x_0 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P3DCFG_PSCCFG_0x_1   1U     /* 0x_1 : Divide the CFGTMR input clock by 1.                                   */
#define  CFGTMR_PDCFG_PDCFG_P3DCFG_PSCCFG_10     2U     /* 10 : Divide the CFGTMR input clock by 4.                                     */
#define  CFGTMR_PDCFG_PDCFG_P3DCFG_PSCCFG_11     3U     /* 11 : Divide the CFGTMR input clock by 16.                                    */


/* ==========================================================  MMV  ========================================================== */
/* =========================================================  MCH0M  ========================================================= */
/* =========================================================  MCH1M  ========================================================= */
/* =========================================================  MCH2M  ========================================================= */
/* =========================================================  MCH3M  ========================================================= */
/* =========================================================  MCH4M  ========================================================= */
/* =========================================================  MCH5M  ========================================================= */
/* =========================================================  MCH6M  ========================================================= */
/* =========================================================  MCH7M  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           ADC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CSTS1  ========================================================= */
/* ===============================================  ADC CSTS1 ICHSEL [0..5]  =============================================== */
                                    /* ADC_CSTS1_ICHSEL                                            */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000000      0     /*!< 000000 : Exernal channel 0 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000001      1     /*!< 000001 : Exernal channel 1 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000010      2     /*!< 000010 : Exernal channel 2 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000011      3     /*!< 000011 : Exernal channel 3 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000100      4     /*!< 000100 : Exernal channel 4 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000101      5     /*!< 000101 : Exernal channel 5 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000110      6     /*!< 000110 : Exernal channel 6 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_000111      7     /*!< 000111 : Exernal channel 7 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001000      8     /*!< 001000 : Exernal channel 8 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001001      9     /*!< 001001 : Exernal channel 9 is selected as input.                          */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001010      10    /*!< 001010 : Exernal channel 10 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001011      11    /*!< 001011 : Exernal channel 11 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001100      12    /*!< 001100 : Exernal channel 12 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001101      13    /*!< 001101 : Exernal channel 13 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001110      14    /*!< 001110 : Exernal channel 14 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_001111      15    /*!< 001111 : Exernal channel 15 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_010101      21    /*!< 010101 : Internal channel 0 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_010110      22    /*!< 010110 : Internal channel 1 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_010111      23    /*!< 010111 : Internal channel 2 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_011011      27    /*!< 011011 : Band Gap                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_011100      28    /*!< 011100 : Internal channel 3 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_011101      29    /*!< 011101 : VREFSH is selected as input. Voltage reference selected
                                                        is determined by CSTS2[REFSEL].                                                 */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_011110      30    /*!< 011110 : VREFSL is selected as input. Voltage reference selected
                                                        is determined by CSTS2[REFSEL].                                                 */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_011111      31    /*!< 011111 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100000      32    /*!< 100000 : Exernal channel 16 is selected as input.                        */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100001      33    /*!< 100001 : Exernal channel 17 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100010      34    /*!< 100010 : Exernal channel 18 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100011      35    /*!< 100011 : Exernal channel 19 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100100      36    /*!< 100100 : Exernal channel 20 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100101      37    /*!< 100101 : Exernal channel 21 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100110      38    /*!< 100110 : Exernal channel 22 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_100111      39    /*!< 100111 : Exernal channel 23 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101000      40    /*!< 101000 : Exernal channel 24 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101001      41    /*!< 101001 : Exernal channel 25 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101010      42    /*!< 101010 : Exernal channel 26 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101011      43    /*!< 101011 : Exernal channel 27 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101100      44    /*!< 101100 : Exernal channel 28 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101101      45    /*!< 101101 : Exernal channel 29 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101110      46    /*!< 101110 : Exernal channel 30 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_101111      47    /*!< 101111 : Exernal channel 31 is selected as input.                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110000      48    /*!< 110000 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110001      49    /*!< 110001 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110010      50    /*!< 110010 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110011      51    /*!< 110011 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110100      52    /*!< 110100 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110101      53    /*!< 110101 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110110      54    /*!< 110110 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_110111      55    /*!< 110111 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111000      56    /*!< 111000 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111001      57    /*!< 111001 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111010      58    /*!< 111010 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111011      59    /*!< 111011 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111100      60    /*!< 111100 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111101      61    /*!< 111101 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111110      62    /*!< 111110 : Reserved                                                         */
#define ADC0_CSTS1_CSTS1_CSTS1A_ICHSEL_111111      63    /*!< 111111 : Module is disabled                                               */

/* ===============================================  ADC CSTS1 CCIEN [6..6]  ================================================ */
                                    /* ADC_CSTS1_CCIEN                                             */
#define ADC_CSTS1_CCIEN_0        0U      /* 0 : Conversion complete interrupt is disabled.                     */
#define ADC_CSTS1_CCIEN_1        1U      /* 1 : Conversion complete interrupt is enabled.                      */

/* ===============================================  ADC CSTS1 CCFLG [7..7]  ================================================ */
                                    /* ADC_CSTS1_CCFLG                                             */
#define ADC_CSTS1_CCFLG_0        0U      /* 0 : Conversion is not completed.                                   */
#define ADC_CSTS1_CCFLG_1        1U      /* 1 : Conversion is completed.                                       */


/* =========================================================  CFG1  ========================================================== */
/* ==============================================  ADC CFG1 ICLKSSEL [0..1]  ============================================== */
                                    /* ADC_CFG1_ICLKSSEL                                                      */
#define ADC_CFG1_ICLKSSEL_00                0U      /* 00 : Alternate clock 1 (ADC_ALTCLK1)                               */
#define ADC_CFG1_ICLKSSEL_01                1U      /* 01 : Alternate clock 2 (ADC_ALTCLK2)                               */
#define ADC_CFG1_ICLKSSEL_10                2U      /* 10 : Alternate clock 3 (ADC_ALTCLK3)                               */
#define ADC_CFG1_ICLKSSEL_11                3U      /* 11 : Alternate clock 4 (ADC_ALTCLK4)                               */

/* ===============================================  ADC CFG1 CMODSEL [2..3]  ================================================ */
                                    /* ADC_CFG1_CMODSEL                                                         */
#define ADC_CFG1_CMODSEL_00                   0U      /* 00 : 8-bit conversion.                                             */
#define ADC_CFG1_CMODSEL_01                   1U      /* 01 : 12-bit conversion.                                            */
#define ADC_CFG1_CMODSEL_10                   2U      /* 10 : 10-bit conversion.                                            */

/* ==============================================  ADC CFG1 CLKDIVCFG [5..6]  =============================================== */
                                    /* ADC_CFG1_CLKDIVCFG                                                       */
#define ADC_CFG1_CLKDIVCFG_00                 0U      /* 00 : The divide ratio is 1 and the clock rate is input clock.      */
#define ADC_CFG1_CLKDIVCFG_01                 1U      /* 01 : The divide ratio is 2 and the clock rate is (input clock)/2.  */
#define ADC_CFG1_CLKDIVCFG_10                 2U      /* 10 : The divide ratio is 4 and the clock rate is (input clock)/4.  */
#define ADC_CFG1_CLKDIVCFG_11                 3U      /* 11 : The divide ratio is 8 and the clock rate is (input clock)/8.  */

/* =========================================================  CFG2  ========================================================== */
/* =========================================================  DATAA  ========================================================= */
/* =========================================================  DATAB  ========================================================= */
/* =========================================================  DATAC  ========================================================= */
/* =========================================================  DATAD  ========================================================= */
/* =========================================================  DATAE  ========================================================= */
/* =========================================================  DATAF  ========================================================= */
/* =========================================================  DATAG  ========================================================= */
/* =========================================================  DATAH  ========================================================= */
/* =========================================================  DATAI  ========================================================= */
/* =========================================================  DATAJ  ========================================================= */
/* =========================================================  DATAK  ========================================================= */
/* =========================================================  DATAL  ========================================================= */
/* =========================================================  DATAM  ========================================================= */
/* =========================================================  DATAN  ========================================================= */
/* =========================================================  DATAO  ========================================================= */
/* =========================================================  DATAP  ========================================================= */
/* ==========================================================  CV1  ========================================================== */
/* ==========================================================  CV2  ========================================================== */
/* =========================================================  CSTS2  ========================================================= */
/* ===============================================  ADC CSTS2 VREFSEL [0..1]  =============================================== */
                                    /* ADC_CSTS2_VREFSEL                                                        */
#define ADC_CSTS2_VREFSEL_00                  0U      /* 00 : Default voltage reference pin pair  that is  external pins
                                                     VREFH and VREFL                                                           */
#define ADC_CSTS2_VREFSEL_01                  1U      /* 01 : Alternate reference voltage  that is  VALTH. This voltage
                                                     may be additional external pin or internal source depending
                                                     on the MCU configuration. See the chip configuration information
                                                     for details specific to this MCU.                                         */

/* ================================================  ADC CSTS2 DMAEN [2..2]  ================================================ */
                                    /* ADC_CSTS2_DMAEN                                                          */
#define ADC_CSTS2_DMAEN_0                     0U      /* 0 : DMA is disabled.                                               */
#define ADC_CSTS2_DMAEN_1                     1U      /* 1 : DMA is enabled and will assert the ADC DMA request during
                                                     an ADC conversion complete event   which is indicated when
                                                     any SC1n[COCO] flag is asserted.                                          */

/* ===============================================  ADC CSTS2 COMPEN [5..5]  ================================================ */
                                    /* ADC_CSTS2_COMPEN                                                         */
#define ADC_CSTS2_COMPEN_0                    0U      /* 0 : Compare function disabled.                                     */
#define ADC_CSTS2_COMPEN_1                    1U      /* 1 : Compare function enabled.                                      */

/* ===============================================  ADC CSTS2 CTRGSEL [6..6]  =============================================== */
                                    /* ADC_CSTS2_CTRGSEL                                                        */
#define ADC_CSTS2_CTRGSEL_0                   0U      /* 0 : Software trigger selected.                                     */
#define ADC_CSTS2_CTRGSEL_1                   1U      /* 1 : Hardware trigger selected.                                     */

/* ================================================  ADC CSTS2 CFLAG [7..7]  ================================================ */
                                    /* ADC_CSTS2_CFLAG                                                   */
#define ADC_CSTS2_CFLAG_0                     0U      /* 0 : Conversion not in progress.                                    */
#define ADC_CSTS2_CFLAG_1                     1U      /* 1 : Conversion in progress.                                        */

/* ==============================================  ADC CSTS2 TRGSTS [16..19]  =============================================== */
                                    /* ADC_CSTS2_TRGSTS                                                  */
#define ADC_CSTS2_TRGSTS_0                    0U      /* 0 : No trigger request has been latched                            */
#define ADC_CSTS2_TRGSTS_1                    1U      /* 1 : A trigger request has been latched                             */

/* ==============================================  ADC CSTS2 TRGEFLG [24..27]  ============================================== */
                                    /* ADC_CSTS2_TRGEFLG                                                        */
#define ADC_CSTS2_TRGEFLG_0                   0U      /* 0 : No error has occurred                                          */
#define ADC_CSTS2_TRGEFLG_1                   1U      /* 1 : An error has occurred                                          */

/* =========================================================  CSTS3  ========================================================= */
/* ===============================================  ADC CSTS3 HAVGCFG [0..1]  =============================================== */
                                   /* ADC_CSTS3_HAVGCFG                                                        */
#define ADC_CSTS3_HAVGCFG_00                  0U      /* 00 : 4 samples averaged.                                           */
#define ADC_CSTS3_HAVGCFG_01                  1U      /* 01 : 8 samples averaged.                                           */
#define ADC_CSTS3_HAVGCFG_10                  2U      /* 10 : 16 samples averaged.                                          */
#define ADC_CSTS3_HAVGCFG_11                  3U      /* 11 : 32 samples averaged.                                          */

/* ===============================================  ADC CSTS3 HAVGEN [2..2]  ================================================ */
                                  /* ADC_CSTS3_HAVGEN                                                         */
#define ADC_CSTS3_HAVGEN_0                    0U      /* 0 : Hardware average function disabled.                            */
#define ADC_CSTS3_HAVGEN_1                    1U      /* 1 : Hardware average function enabled.                             */

/* ===============================================  ADC CSTS3 CONTCEN [3..3]  =============================================== */
                                  /* ADC_CSTS3_CONTCEN                                                        */
#define ADC_CSTS3_CONTCEN_0                   0U      /* 0 : One conversion will be performed (or one set of conversions
                                                     if AVGE is set) after a conversion is initiated.                          */
#define ADC_CSTS3_CONTCEN_1                   1U      /* 1 : Continuous conversions will be performed (or continuous
                                                     sets of conversions  if AVGE is set) after a conversion
                                                     is initiated.                                                             */

 /* ===============================================  ADC CSTS3 CAL [7..7]  =============================================== */
                                  /* ADC_CSTS3_CAL                                                        */
#define ADC_CSTS3_CAL_0                   0U      /* 0 : The calibration sequence is completed                              */
#define ADC_CSTS3_CAL_1                   1U      /* 1 : The ADC begins the calibration sequence                            */

/* =========================================================  BOEC  ========================================================== */
/* ==========================================================  OEC  ========================================================== */
/* =========================================================  UOEC  ========================================================== */
/* =========================================================  XOEC  ========================================================== */
/* =========================================================  YOEC  ========================================================== */
/* =========================================================  GEAF  ========================================================== */
/* =========================================================  UGEC  ========================================================= */
/* =========================================================  GCALS  ========================================================= */
/* ========================================================  PSGCAL3  ======================================================== */
/* ========================================================  PSGCAL2  ======================================================== */
/* ========================================================  PSGCAL1  ======================================================== */
/* ========================================================  PSGCAL0  ======================================================== */
/* ========================================================  PSGCALX  ======================================================== */
/* ========================================================  PSGCAL9  ======================================================== */
/* ========================================================  GCALOS  ========================================================= */
/* =======================================================  PSGCALOV3  ======================================================= */
/* =======================================================  PSGCALOV2  ======================================================= */
/* =======================================================  PSGCALOV1  ======================================================= */
/* =======================================================  PSGCALOV0  ======================================================= */
/* =======================================================  PSGCALOVX  ======================================================= */
/* =======================================================  PSGCALOV9  ======================================================= */
/* ===============================================  ADC ACSTS1 ICHSEL [0..5]  =============================================== */
                                    /* ADC_aSC1_ICHSEL                                            */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000000      0     /*!< 000000 : Exernal intput channel 0 is selected.                            */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000001      1     /*!< 000001 : Exernal channel 1 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000010      2     /*!< 000010 : Exernal channel 2 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000011      3     /*!< 000011 : Exernal channel 3 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000100      4     /*!< 000100 : Exernal channel 4 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000101      5     /*!< 000101 : Exernal channel 5 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000110      6     /*!< 000110 : Exernal channel 6 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_000111      7     /*!< 000111 : Exernal channel 7 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001000      8     /*!< 001000 : Exernal channel 8 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001001      9     /*!< 001001 : Exernal channel 9 is selected as input.                          */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001010      10    /*!< 001010 : Exernal channel 10 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001011      11    /*!< 001011 : Exernal channel 11 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001100      12    /*!< 001100 : Exernal channel 12 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001101      13    /*!< 001101 : Exernal channel 13 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001110      14    /*!< 001110 : Exernal channel 14 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_001111      15    /*!< 001111 : Exernal channel 15 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_010101      21    /*!< 010101 : Internal channel 0 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_010110      22    /*!< 010110 : Internal channel 1 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_010111      23    /*!< 010111 : Internal channel 2 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_011011      27    /*!< 011011 : Band Gap                                                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_011100      28    /*!< 011100 : Internal channel 3 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_011101      29    /*!< 011101 : VREFSH is selected as input. Voltage reference selected
                                                        is determined by CSTS2[REFSEL].                                                 */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_011110      30    /*!< 011110 : VREFSL is selected as input. Voltage reference selected
                                                        is determined by CSTS2[REFSEL].                                                 */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_011111      31    /*!< 011111 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100000      32    /*!< 100000 : Internal channel 16 is selected as input.                        */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100001      33    /*!< 100001 : Exernal channel 17 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100010      34    /*!< 100010 : Exernal channel 18 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100011      35    /*!< 100011 : Exernal channel 19 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100100      36    /*!< 100100 : Exernal channel 20 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100101      37    /*!< 100101 : Exernal channel 21 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100110      38    /*!< 100110 : Exernal channel 22 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_100111      39    /*!< 100111 : Exernal channel 23 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101000      40    /*!< 101000 : Exernal channel 24 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101001      41    /*!< 101001 : Exernal channel 25 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101010      42    /*!< 101010 : Exernal channel 26 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101011      43    /*!< 101011 : Exernal channel 27 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101100      44    /*!< 101100 : Exernal channel 28 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101101      45    /*!< 101101 : Exernal channel 29 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101110      46    /*!< 101110 : Exernal channel 30 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_101111      47    /*!< 101111 : Exernal channel 31 is selected as input.                         */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_48   48 /*!< 11xxxx_48 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_49   49 /*!< 11xxxx_49 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_50   50 /*!< 11xxxx_50 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_51   51 /*!< 11xxxx_51 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_52   52 /*!< 11xxxx_52 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_53   53 /*!< 11xxxx_53 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_54   54 /*!< 11xxxx_54 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_55   55 /*!< 11xxxx_55 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_56   56 /*!< 11xxxx_56 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_57   57 /*!< 11xxxx_57 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_58   58 /*!< 11xxxx_58 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_59   59 /*!< 11xxxx_59 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_60   60 /*!< 11xxxx_60 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_61   61 /*!< 11xxxx_61 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_62   62 /*!< 11xxxx_62 : Module is disabled                                               */
#define ADC0_aSC1_aSC1_aSC1A_ICHSEL_11xxxx_63   63 /*!< 11xxxx_63 : Module is disabled                                               */
/* ===============================================  ADC ACSTS1 CCIEN [6..6]  ================================================ */
                                    /* ADC_aSC1_CCIEN                                             */
#define ADC_aSC1_CCIEN_0        0U      /* 0 : Conversion complete interrupt is disabled.                     */
#define ADC_aSC1_CCIEN_1        1U      /* 1 : Conversion complete interrupt is enabled.                      */

/* ===============================================  ADC ACSTS1 CCFLG [7..7]  ================================================ */
                                    /* ADC_aSC1_CCFLG                                             */
#define ADC_aSC1_CCFLG_0        0U      /* 0 : Conversion is not completed.                                   */
#define ADC_aSC1_CCFLG_1        1U      /* 1 : Conversion is completed.                                       */
/* =======================================================  aRA-X  ======================================================= */


/* =========================================================================================================================== */
/* ================                                          LPSPI                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* =============================================  LPSPI VERID FEATURE [0..15]  ============================================== */
                                  /* LPSPI_VERID_FEATURE                                                      */
#define LPSPI_VERID_FEATURE_0000000000000100   4U     /* 0000000000000100 : Standard feature set supporting 32-bit shift
                                                     register.                                                                 */

/* =========================================================  PARA  ========================================================= */
/* =========================================================  CTRL  ========================================================== */
/* ================================================  LPSPI CTRL MEN [0..0]  ================================================= */
                                 /* LPSPI_CTRL_MEN                                                           */
#define LPSPI_CTRL_MEN_0                      0U      /* 0 : Module is disabled.                                            */
#define LPSPI_CTRL_MEN_1                      1U      /* 1 : Module is enabled.                                             */

/* ===============================================  LPSPI CTRL SWRST [1..1]  ================================================ */
                                  /* LPSPI_CTRL_SWRST                                                         */
#define LPSPI_CTRL_SWRST_0                    0U      /* 0 : Master logic is not reset.                                     */
#define LPSPI_CTRL_SWRST_1                    1U      /* 1 : Master logic is reset.                                         */

/* ==============================================  LPSPI CTRL DOZEDIS [2..2]  =============================================== */
                                 /* LPSPI_CTRL_DOZEDIS                                                       */
#define LPSPI_CTRL_DOZEDIS_0                  0U      /* 0 : Module is enabled in Doze mode.                                */
#define LPSPI_CTRL_DOZEDIS_1                  1U      /* 1 : Module is disabled in Doze mode.                               */

/* ===============================================  LPSPI CTRL DBGEN [3..3]  ================================================ */
                                  /* LPSPI_CTRL_DBGEN                                                         */
#define LPSPI_CTRL_DBGEN_0                    0U      /* 0 : Module is disabled in debug mode.                              */
#define LPSPI_CTRL_DBGEN_1                    1U      /* 1 : Module is enabled in debug mode.                               */

/* ===============================================  LPSPI CTRL TXFRST [8..8]  =============================================== */
                                 /* LPSPI_CTRL_TXFRST                                                        */
#define LPSPI_CTRL_TXFRST_0                   0U      /* 0 : No effect.                                                     */
#define LPSPI_CTRL_TXFRST_1                   1U      /* 1 : Transmit FIFO is reset.                                        */

/* ===============================================  LPSPI CTRL RXFRST [9..9]  =============================================== */
                                 /* LPSPI_CTRL_RXFRST                                                        */
#define LPSPI_CTRL_RXFRST_0                   0U      /* 0 : No effect.                                                     */
#define LPSPI_CTRL_RXFRST_1                   1U      /* 1 : Receive FIFO is reset.                                         */

/* ==========================================================  STS  ========================================================== */
/* ==============================================  LPSPI STS TXDATAFLG [0..0]  ============================================== */
                                 /* LPSPI_STS_TXDATAFLG                                                      */
#define LPSPI_STS_TXDATAFLG_0                 0U      /* 0 : Transmit data not requested.                                   */
#define LPSPI_STS_TXDATAFLG_1                 1U      /* 1 : Transmit data is requested.                                    */

/* ==============================================  LPSPI STS RXDATAFLG [1..1]  ============================================== */
                                  /* LPSPI_STS_RXDATAFLG                                                      */
#define LPSPI_STS_RXDATAFLG_0                 0U      /* 0 : Receive Data is not ready.                                     */
#define LPSPI_STS_RXDATAFLG_1                 1U      /* 1 : Receive data is ready.                                         */

/* ===============================================  LPSPI STS RXWCFLG [8..8]  =============================================== */
                                  /* LPSPI_STS_RXWCFLG                                                        */
#define LPSPI_STS_RXWCFLG_0                   0U      /* 0 : Transfer word not completed.                                   */
#define LPSPI_STS_RXWCFLG_1                   1U      /* 1 : Transfer word completed.                                       */

/* ===============================================  LPSPI STS FTXCFLG [9..9]  =============================================== */
                                  /* LPSPI_STS_FTXCFLG                                                        */
#define LPSPI_STS_FTXCFLG_0                   0U      /* 0 : Frame transfer has not completed.                              */
#define LPSPI_STS_FTXCFLG_1                   1U      /* 1 : Frame transfer has completed.                                  */

/* ==============================================  LPSPI STS TXCFLG [10..10]  =============================================== */
                                /* LPSPI_STS_TXCFLG                                                         */
#define LPSPI_STS_TXCFLG_0                    0U      /* 0 : All transfers have not completed.                              */
#define LPSPI_STS_TXCFLG_1                    1U      /* 1 : All transfers have completed.                                  */

/* ==============================================  LPSPI STS TXEFLG [11..11]  =============================================== */
                                  /* LPSPI_STS_TXEFLG                                                         */
#define LPSPI_STS_TXEFLG_0                    0U      /* 0 : Transmit FIFO underrun has not occurred.                       */
#define LPSPI_STS_TXEFLG_1                    1U      /* 1 : Transmit FIFO underrun has occurred                            */

/* ==============================================  LPSPI STS RXEFLG [12..12]  =============================================== */
                                 /* LPSPI_STS_RXEFLG                                                         */
#define LPSPI_STS_RXEFLG_0                    0U      /* 0 : Receive FIFO has not overflowed.                               */
#define LPSPI_STS_RXEFLG_1                    1U      /* 1 : Receive FIFO has overflowed.                                   */

/* ==============================================  LPSPI STS RXMFLG [13..13]  =============================================== */
                                  /* LPSPI_STS_RXMFLG                                                         */
#define LPSPI_STS_RXMFLG_0                    0U      /* 0 : Have not received matching data.                               */
#define LPSPI_STS_RXMFLG_1                    1U      /* 1 : Have received matching data.                                   */

/* ==============================================  LPSPI STS BSYFLG [24..24]  =============================================== */
                                  /* LPSPI_STS_BSYFLG                                                         */
#define LPSPI_STS_BSYFLG_0                    0U      /* 0 : LPSPI is idle.                                                 */
#define LPSPI_STS_BSYFLG_1                    1U      /* 1 : LPSPI is busy.                                                 */

/* =========================================================  IEN  ========================================================= */
/* ===============================================  LPSPI IEN TXIEN [0..0]  =============================================== */
                                  /* LPSPI_IEN_TXIEN                                                        */
#define LPSPI_IEN_TXIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_TXIEN_1                   1U      /* 1 : Interrupt enabled                                              */

/* ===============================================  LPSPI IEN RXIEN [1..1]  =============================================== */
                                  /* LPSPI_IEN_RXIEN                                                        */
#define LPSPI_IEN_RXIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_RXIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPSPI IEN RXWCIEN [8..8]  ============================================== */
                                  /* LPSPI_IEN_RXWCIEN                                                      */
#define LPSPI_IEN_RXWCIEN_0                 0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_RXWCIEN_1                 1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPSPI IEN FTCIEN [9..9]  =============================================== */
                                  /* LPSPI_IEN_FTCIEN                                                       */
#define LPSPI_IEN_FTCIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_FTCIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPSPI IEN TXCIEN [10..10]  ============================================== */
                                  /* LPSPI_IEN_TXCIEN                                                       */
#define LPSPI_IEN_TXCIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_TXCIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPSPI IEN TXEIEN [11..11]  ============================================== */
                                  /* LPSPI_IEN_TXEIEN                                                       */
#define LPSPI_IEN_TXEIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_TXEIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPSPI IEN RXEIEN [12..12]  ============================================== */
                                   /* LPSPI_IEN_RXEIEN                                                       */
#define LPSPI_IEN_RXEIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_RXEIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPSPI IEN RXMIEN [13..13]  ============================================== */
                                 /* LPSPI_IEN_RXMIEN                                                       */
#define LPSPI_IEN_RXMIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPSPI_IEN_RXMIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =========================================================  DMAEN  ========================================================= */
/* ==============================================  LPSPI DMAEN TXDMAEN [0..0]  ============================================== */
                                   /* LPSPI_DMAEN_TXDMAEN                                                      */
#define LPSPI_DMAEN_TXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPSPI_DMAEN_TXDMAEN_1                 1U      /* 1 : DMA request enabled                                            */

/* ==============================================  LPSPI DMAEN RXDMAEN [1..1]  ============================================== */
                               /* LPSPI_DMAEN_RXDMAEN                                                      */
#define LPSPI_DMAEN_RXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPSPI_DMAEN_RXDMAEN_1                 1U      /* 1 : DMA request enabled.                                           */

/* =========================================================  CFG0  ========================================================== */
/* ===============================================  LPSPI CFG0 HREQEN [0..0]  =============================================== */
                                    /* LPSPI_CFG0_MREQEN                                                        */
#define LPSPI_CFG0_MREQEN_0                   0U      /* 0 : Host request is disabled.                                      */
#define LPSPI_CFG0_MREQEN_1                   1U      /* 1 : Host request is enabled.                                       */

/* ==============================================  LPSPI CFG0 HREQPCFG [1..1]  ============================================== */
                                  /* LPSPI_CFG0_MREQPCFG                                                      */
#define LPSPI_CFG0_MREQPCFG_0                 0U      /* 0 : Active low.                                                    */
#define LPSPI_CFG0_MREQPCFG_1                 1U      /* 1 : Active high.                                                   */

/* ==============================================  LPSPI CFG0 HREQISEL [2..2]  ============================================== */
                                  /* LPSPI_CFG0_MREQISEL                                               */
#define LPSPI_CFG0_MREQISEL_0                 0U      /* 0 : Host request input is pin LPSPI_HREQ.                          */
#define LPSPI_CFG0_MREQISEL_1                 1U      /* 1 : Host request input is input trigger.                           */

/* ===============================================  LPSPI CFG0 CIRFEN [8..8]  =============================================== */
                                  /* LPSPI_CFG0_CIRFEN                                                        */
#define LPSPI_CFG0_CIRFEN_0                   0U      /* 0 : Circular FIFO is disabled.                                     */
#define LPSPI_CFG0_CIRFEN_1                   1U      /* 1 : Circular FIFO is enabled.                                      */

/* ===============================================  LPSPI CFG0 RXMOEN [9..9]  =============================================== */
                                   /* LPSPI_CFG0_RXMOEN                                                        */
#define LPSPI_CFG0_RXMOEN_0                   0U      /* 0 : Received data is stored in the receive FIFO as normal.         */
#define LPSPI_CFG0_RXMOEN_1                   1U      /* 1 : Received data is discarded unless the DMF is set.              */

/* =========================================================  CFG1  ========================================================== */
/* ===============================================  LPSPI CFG1 MSCFG [0..0]  ================================================ */
                              /* LPSPI_CFG1_MSCFG                                                         */
#define LPSPI_CFG1_MSCFG_0                    0U      /* 0 : Slave mode.                                                    */
#define LPSPI_CFG1_MSCFG_1                    1U      /* 1 : Master mode.                                                   */

/* ==============================================  LPSPI CFG1 IDSPCFG [1..1]  =============================================== */
                                /* LPSPI_CFG1_IDSPCFG                                                       */
#define LPSPI_CFG1_IDSPCFG_0                  0U      /* 0 : Input data sampled on SCK edge.                                */
#define LPSPI_CFG1_IDSPCFG_1                  1U      /* 1 : Input data sampled on delayed SCK edge.                        */

/* ===============================================  LPSPI CFG1 APCSEN [2..2]  =============================================== */
                                  /* LPSPI_CFG1_APCSEN                                                        */
#define LPSPI_CFG1_APCSEN_0                   0U      /* 0 : Automatic PCS generation disabled.                             */
#define LPSPI_CFG1_APCSEN_1                   1U      /* 1 : Automatic PCS generation enabled.                              */

/* ===============================================  LPSPI CFG1 DISTXS [3..3]  =============================================== */
                                  /* LPSPI_CFG1_DISTXS                                                        */
#define LPSPI_CFG1_DISTXS_0                   0U      /* 0 : Transfers will stall when transmit FIFO is empty or receive
                                                     FIFO is full.                                                             */
#define LPSPI_CFG1_DISTXS_1                   1U      /* 1 : Transfers will not stall  allowing transmit FIFO underrun
                                                     or receive FIFO overrun to occur.                                         */

/* =============================================  LPSPI CFG1 PCSPPCFG [8..11]  ============================================== */
                                /* LPSPI_CFG1_PCSPPCFG                                                      */
#define LPSPI_CFG1_PCSPPCFG_0000              0U      /* 0000 : The PCSx is active low.                                     */
#define LPSPI_CFG1_PCSPPCFG_0001              1U      /* 0001 : The PCSx is active high.                                    */

/* ===============================================  LPSPI CFG1 MCFG [16..18]  =============================================== */
                                  /* LPSPI_CFG1_MCFG                                                          */
#define LPSPI_CFG1_MCFG_000                   0U      /* 000 : Match is disabled.                                           */
#define LPSPI_CFG1_MCFG_010                   2U      /* 010 : 010b - Match is enabled  if 1st data word equals MATCH0
                                                     OR MATCH1  i.e.  (1st data word = MATCH0 + MATCH1)                        */
#define LPSPI_CFG1_MCFG_011                   3U      /* 011 : 011b - Match is enabled  if any data word equals MATCH0
                                                     OR MATCH1  i.e.  (any data word = MATCH0 + MATCH1)                        */
#define LPSPI_CFG1_MCFG_100                   4U      /* 100 : 100b - Match is enabled  if 1st data word equals MATCH0
                                                     AND 2nd data word equals MATCH1  i.e.  [(1st data word
                                                     = MATCH0) * (2nd data word = MATCH1)]                                     */
#define LPSPI_CFG1_MCFG_101                   5U      /* 101 : 101b - Match is enabled  if any data word equals MATCH0
                                                     AND the next data word equals MATCH1  i.e.  [(any data
                                                     word = MATCH0) * (next data word = MATCH1)]                               */
#define LPSPI_CFG1_MCFG_110                   6U      /* 110 : 110b - Match is enabled  if(1st data word AND MATCH1)
                                                     equals (MATCH0 AND MATCH1)  i.e.  [(1st data word * MATCH1)
                                                     = (MATCH0 * MATCH1)]                                                      */
#define LPSPI_CFG1_MCFG_111                   7U      /* 111 : 111b - Match is enabled  if(any data word AND MATCH1)
                                                     equals (MATCH0 AND MATCH1)  i.e.  [(any data word * MATCH1)
                                                     = (MATCH0 * MATCH1)]                                                      */

/* ==============================================  LPSPI CFG1 IOPCFG [24..25]  ============================================== */
                                   /* LPSPI_CFG1_IOPCFG                                                        */
#define LPSPI_CFG1_IOPCFG_00                  0U      /* 00 : SIN is used for input data and SOUT for output data.          */
#define LPSPI_CFG1_IOPCFG_01                  1U      /* 01 : SIN is used for both input and output data.                   */
#define LPSPI_CFG1_IOPCFG_10                  2U      /* 10 : SOUT is used for both input and output data.                  */
#define LPSPI_CFG1_IOPCFG_11                  3U      /* 11 : SOUT is used for input data and SIN for output data.          */

/* ==============================================  LPSPI CFG1 ODCFG [26..26]  =============================================== */
                                  /* LPSPI_CFG1_ODCFG                                                         */
#define LPSPI_CFG1_ODCFG_0                    0U      /* 0 : Output data retains last value when chip select is negated.    */
#define LPSPI_CFG1_ODCFG_1                    1U      /* 1 : Output data is tristated when chip select is negated.          */

/* =============================================  LPSPI CFG1 PCSELCFG [27..27]  ============================================= */
                                  /* LPSPI_CFG1_PCSELCFG                                                      */
#define LPSPI_CFG1_PCSELCFG_0                 0U      /* 0 : PCS[3:2] are enabled.                                          */
#define LPSPI_CFG1_PCSELCFG_1                 1U      /* 1 : PCS[3:2] are disabled.                                         */

/* ========================================================  DATAM0  ========================================================= */
/* ========================================================  DATAM1  ========================================================= */
/* ========================================================  CLKCFG  ========================================================= */
/* =========================================================  FCTRL  ========================================================= */
/* =========================================================  FSTS  ========================================================== */
/* =========================================================  TXCMD  ========================================================= */
/* ============================================  LPSPI TXCMD TXWIDCFG [16..17]  ============================================= */
                                  /* LPSPI_TXCMD_TXWIDCFG                                                     */
#define LPSPI_TXCMD_TXWIDCFG_00               0U      /* 00 : Single bit transfer.                                          */
#define LPSPI_TXCMD_TXWIDCFG_01               1U      /* 01 : Two bit transfer.                                             */
#define LPSPI_TXCMD_TXWIDCFG_10               2U      /* 10 : Four bit transfer.                                            */

/* ===========================================  LPSPI TXCMD TXDATAMASK [18..18]  ============================================ */
                                 /* LPSPI_TXCMD_TXDATAMASK                                                   */
#define LPSPI_TXCMD_TXDATAMASK_0              0U      /* 0 : Normal transfer.                                               */
#define LPSPI_TXCMD_TXDATAMASK_1              1U      /* 1 : Mask transmit data.                                            */

/* ===========================================  LPSPI TXCMD RXDATAMASK [19..19]  ============================================ */
                                   /* LPSPI_TXCMD_RXDATAMASK                                                   */
#define LPSPI_TXCMD_RXDATAMASK_0              0U      /* 0 : Normal transfer.                                               */
#define LPSPI_TXCMD_RXDATAMASK_1              1U      /* 1 : Receive data is masked.                                        */

/* =============================================  LPSPI TXCMD CTXCMDW [20..20]  ============================================= */
                                 /* LPSPI_TXCMD_CTXCMDW                                                      */
#define LPSPI_TXCMD_CTXCMDW_0                 0U      /* 0 : Command word for start of new transfer.                        */
#define LPSPI_TXCMD_CTXCMDW_1                 1U      /* 1 : Command word for continuing transfer.                          */

/* ==============================================  LPSPI TXCMD CTXEN [21..21]  ============================================== */
                                  /* LPSPI_TXCMD_CTXEN                                                        */
#define LPSPI_TXCMD_CTXEN_0                   0U      /* 0 : Continuous transfer disabled.                                  */
#define LPSPI_TXCMD_CTXEN_1                   1U      /* 1 : Continuous transfer enabled.                                   */

/* ==============================================  LPSPI TXCMD BSEN [22..22]  =============================================== */
                                  /* LPSPI_TXCMD_BSEN                                                         */
#define LPSPI_TXCMD_BSEN_0                    0U      /* 0 : Byte swap disabled.                                            */
#define LPSPI_TXCMD_BSEN_1                    1U      /* 1 : Byte swap enabled.                                             */

/* ============================================  LPSPI TXCMD DATAFSEL [23..23]  ============================================= */
                                  /* LPSPI_TXCMD_DATAFSEL                                                     */
#define LPSPI_TXCMD_DATAFSEL_0                0U      /* 0 : Data is transferred MSB first.                                 */
#define LPSPI_TXCMD_DATAFSEL_1                1U      /* 1 : Data is transferred LSB first.                                 */

/* ==============================================  LPSPI TXCMD PCSEL [24..25]  ============================================== */
                                  /* LPSPI_TXCMD_PCSEL                                                        */
#define LPSPI_TXCMD_PCSEL_00                  0U      /* 00 : Transfer using LPSPI_PCS[0]                                   */
#define LPSPI_TXCMD_PCSEL_01                  1U      /* 01 : Transfer using LPSPI_PCS[1]                                   */
#define LPSPI_TXCMD_PCSEL_10                  2U      /* 10 : Transfer using LPSPI_PCS[2]                                   */
#define LPSPI_TXCMD_PCSEL_11                  3U      /* 11 : Transfer using LPSPI_PCS[3]                                   */

/* =============================================  LPSPI TXCMD PVALCFG [27..29]  ============================================= */
                                   /* LPSPI_TXCMD_PVALCFG                                                      */
#define LPSPI_TXCMD_PVALCFG_000               0U      /* 000 : Divide by 1.                                                 */
#define LPSPI_TXCMD_PVALCFG_001               1U      /* 001 : Divide by 2.                                                 */
#define LPSPI_TXCMD_PVALCFG_010               2U      /* 010 : Divide by 4.                                                 */
#define LPSPI_TXCMD_PVALCFG_011               3U      /* 011 : Divide by 8.                                                 */
#define LPSPI_TXCMD_PVALCFG_100               4U      /* 100 : Divide by 16.                                                */
#define LPSPI_TXCMD_PVALCFG_101               5U      /* 101 : Divide by 32.                                                */
#define LPSPI_TXCMD_PVALCFG_110               6U      /* 110 : Divide by 64.                                                */
#define LPSPI_TXCMD_PVALCFG_111               7U      /* 111 : Divide by 128.                                               */

/* =============================================  LPSPI TXCMD CLKPHA [30..30]  ============================================== */
                                  /* LPSPI_TXCMD_CLKPHA                                                       */
#define LPSPI_TXCMD_CLKPHA_0                  0U      /* 0 : Data is captured on the leading edge of SCK and changed
                                                     on the following edge.                                                    */
#define LPSPI_TXCMD_CLKPHA_1                  1U      /* 1 : Data is changed on the leading edge of SCK and captured
                                                     on the following edge.                                                    */

/* =============================================  LPSPI TXCMD CLKPOL [31..31]  ============================================== */
                                /* LPSPI_TXCMD_CLKPOL                                                       */
#define LPSPI_TXCMD_CLKPOL_0                  0U      /* 0 : The inactive state value of SCK is low.                        */
#define LPSPI_TXCMD_CLKPOL_1                  1U      /* 1 : The inactive state value of SCK is high.                       */

/* ========================================================  TXDATA  ========================================================= */
/* =========================================================  RXSTS  ========================================================= */
/* =============================================  LPSPI RXSTS FDATAWCFG [0..0]  ============================================= */
                                /* LPSPI_RXSTS_FDATAWCFG                                                    */
#define LPSPI_RXSTS_FDATAWCFG_0               0U      /* 0 : Subsequent data word received after LPSPI_PCS assertion.       */
#define LPSPI_RXSTS_FDATAWCFG_1               1U      /* 1 : First data word received after LPSPI_PCS assertion.            */

/* ===============================================  LPSPI RXSTS RXFE [1..1]  ================================================ */
                                 /* LPSPI_RXSTS_RXFE                                                         */
#define LPSPI_RXSTS_RXFE_0                    0U      /* 0 : RX FIFO is not empty.                                          */
#define LPSPI_RXSTS_RXFE_1                    1U      /* 1 : RX FIFO is empty.                                              */

/* ========================================================  RXDATA  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           PDU                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CSTS  ========================================================== */
/* ================================================  PDU CSTS LDSUS [0..0]  ================================================ */
                                  /* PDU_CSTS_LDSUS                                                          */
#define PDU_CSTS_LDSUS_0                     0U      /* 0 : PDU LDSUS                                 */
#define PDU_CSTS_LDSUS_1                     1U      /* 1 : PDU LDSUS                               */


/* ================================================  PDU CSTS CMODEN [1..1]  ================================================ */
                                  /* PDU_CSTS_CMODEN                                                          */
#define PDU_CSTS_CMODEN_0                     0U      /* 0 : PDU operation in One-Shot mode                                 */
#define PDU_CSTS_CMODEN_1                     1U      /* 1 : PDU operation in Continuous mode                               */

/* ==============================================  PDU CSTS MULPSCCFG [2..3]  =============================================== */
                                  /* PDU_CSTS_MULPSCCFG                                                       */
#define PDU_CSTS_MULPSCCFG_00                 0U      /* 00 : Multiplication factor is 1.                                   */
#define PDU_CSTS_MULPSCCFG_01                 1U      /* 01 : Multiplication factor is 10.                                  */
#define PDU_CSTS_MULPSCCFG_10                 2U      /* 10 : Multiplication factor is 20.                                  */
#define PDU_CSTS_MULPSCCFG_11                 3U      /* 11 : Multiplication factor is 40.                                  */

/* =================================================  PDU CSTS IEN [5..5]  ================================================== */
                                  /* PDU_CSTS_IEN                                                             */
#define PDU_CSTS_IEN_0                        0U      /* 0 : PDU interrupt disabled.                                        */
#define PDU_CSTS_IEN_1                        1U      /* 1 : PDU interrupt enabled.                                         */

/* =================================================  PDU CSTS IFLG [6..6]  ================================================== */
                                  /* PDU_CSTS_IFLG                                                             */
#define PDU_CSTS_IFLG_0                        0U      /* 0 : PDU interrupt flag.                                        */
#define PDU_CSTS_IFLG_1                        1U      /* 1 : PDU interrupt flag.                                         */


/* ================================================  PDU CSTS PDUEN [7..7]  ================================================= */
                                  /* PDU_CSTS_PDUEN                                                           */
#define PDU_CSTS_PDUEN_0                      0U      /* 0 : PDU disabled. Counter is off.                                  */
#define PDU_CSTS_PDUEN_1                      1U      /* 1 : PDU enabled.                                                   */

/* ==============================================  PDU CSTS TRGINTSEL [8..11]  ============================================== */
                                   /* PDU_CSTS_TRGINTSEL                                                       */
#define PDU_CSTS_TRGINTSEL_0000               0U      /* 0000 : Trigger-In 0 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0001               1U      /* 0001 : Trigger-In 1 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0010               2U      /* 0010 : Trigger-In 2 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0011               3U      /* 0011 : Trigger-In 3 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0100               4U      /* 0100 : Trigger-In 4 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0101               5U      /* 0101 : Trigger-In 5 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0110               6U      /* 0110 : Trigger-In 6 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_0111               7U      /* 0111 : Trigger-In 7 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_1000               8U      /* 1000 : Trigger-In 8 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_1001               9U      /* 1001 : Trigger-In 9 is selected.                                   */
#define PDU_CSTS_TRGINTSEL_1010               10U     /* 1010 : Trigger-In 10 is selected.                                  */
#define PDU_CSTS_TRGINTSEL_1011               11U     /* 1011 : Trigger-In 11 is selected.                                  */
#define PDU_CSTS_TRGINTSEL_1100               12U     /* 1100 : Trigger-In 12 is selected.                                  */
#define PDU_CSTS_TRGINTSEL_1101               13U     /* 1101 : Trigger-In 13 is selected.                                  */
#define PDU_CSTS_TRGINTSEL_1110               14U     /* 1110 : Trigger-In 14 is selected.                                  */
#define PDU_CSTS_TRGINTSEL_1111               15U     /* 1111 : Software trigger is selected.                               */

/* =============================================  PDU CSTS PSCDIVCFG [12..14]  ============================================== */
                                   /* PDU_CSTS_PSCDIVCFG                                                       */
#define PDU_CSTS_PSCDIVCFG_000                0U      /* 000 : Counting uses the peripheral clock divided by MULT (the
                                                     multiplication factor).                                                   */
#define PDU_CSTS_PSCDIVCFG_001                1U      /* 001 : Counting uses the peripheral clock divided by 2 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_010                2U      /* 010 : Counting uses the peripheral clock divided by 4 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_011                3U      /* 011 : Counting uses the peripheral clock divided by 8 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_100                4U      /* 100 : Counting uses the peripheral clock divided by 16 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_101                5U      /* 101 : Counting uses the peripheral clock divided by 32 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_110                6U      /* 110 : Counting uses the peripheral clock divided by 64 x MULT
                                                     (the multiplication factor).                                              */
#define PDU_CSTS_PSCDIVCFG_111                7U      /* 111 : Counting uses the peripheral clock divided by 128 x MULT
                                                     (the multiplication factor).                                              */

/* ===============================================  PDU CSTS DMAEN [15..15]  ================================================ */
                                   /* PDU_CSTS_DMAEN                                                           */
#define PDU_CSTS_DMAEN_0                      0U      /* 0 : DMA disabled.                                                  */
#define PDU_CSTS_DMAEN_1                      1U      /* 1 : DMA enabled.                                                   */

/* ============================================  PDU CSTS SWTRGSEL [16..16]  ================================================ */
                                   /* PDU_CSTS_DMAEN                                                           */
#define PDU_CSTS_SWTRGSEL_0                   0U      /* 0 : DMA disabled.                                                  */
#define PDU_CSTS_SWTRGSEL_1                   1U      /* 1 : DMA enabled.                                                   */

/* ==============================================  PDU CSTS SEQEIEN [17..17]  =============================================== */
                                  /* PDU_CSTS_SEQEIEN                                                         */
#define PDU_CSTS_SEQEIEN_0                    0U      /* 0 : PDU sequence error interrupt disabled.                         */
#define PDU_CSTS_SEQEIEN_1                    1U      /* 1 : PDU sequence error interrupt enabled.                          */

/* ==============================================  PDU CSTS LDMODSEL [18..19]  ============================================== */
                                  /* PDU_CSTS_LDMODSEL                                                        */
#define PDU_CSTS_LDMODSEL_00                  0U      /* 00 : The internal registers are loaded with the values from
                                                     their buffers  immediately after 1 is written to LDOK.                    */
#define PDU_CSTS_LDMODSEL_01                  1U      /* 01 : The internal registers are loaded with the values from
                                                     their buffers when the PDU counter (CNT) = MOD + 1 CNT
                                                     delay elapsed  after 1 is written to LDOK.                                */
#define PDU_CSTS_LDMODSEL_10                  2U      /* 10 : The internal registers are loaded with the values from
                                                     their buffers when a trigger input event is detected  after
                                                     1 is written to LDOK.                                                     */
#define PDU_CSTS_LDMODSEL_11                  3U      /* 11 : The internal registers are loaded with the values from
                                                     their buffers when either the PDU counter (CNT) = MOD +
                                                     1 CNT delay elapsed  or a trigger input event is detected
                                                     after 1 is written to LDOK.                                               */

/* ==========================================================  CNTPRD  ========================================================== */
/* ==========================================================  CNTCUR  ========================================================== */
/* =========================================================  SINTDLY  ========================================================== */
/* =======================================================  CHnCTRL1  ======================================================== */
/* =============================================  PDU CHnCTRL1 CHPTOEN [0..7]  ============================================== */
                                   /* PDU_CHnCTRL1_CHPTOEN                                     */
#define PDU_CHnCTRL1_CHPTOEN_0   0U   /* 0 : PDU channels corresponding pre-trigger disabled.               */
#define PDU_CHnCTRL1_CHPTOEN_1   1U   /* 1 : PDU channels corresponding pre-trigger enabled.                */

/* ============================================  PDU CHnCTRL1 CHPTOSEL [8..15]  ============================================= */
                                   /* PDU_CHnCTRL1_CHPTOSEL                                    */
#define PDU_CHnCTRL1_CHPTOSEL_0   0U  /* 0 : PDU channels corresponding pre-trigger is in bypassed mode.
                                                     The pre-trigger asserts one peripheral clock cycle after
                                                     a rising edge is detected on selected trigger input source
                                                     or software trigger is selected and SWTRIG is written with
                                                     1.                                                                        */
#define PDU_CHnCTRL1_CHPTOSEL_1   1U  /* 1 : PDU channels corresponding pre-trigger asserts when the
                                                     counter reaches the channel delay register and one peripheral
                                                     clock cycle after a rising edge is detected on selected
                                                     trigger input source or software trigger is selected and
                                                     SWTRIG is written with 1.                                                 */

/* =============================================  PDU CHnCTRL1 PTBBEN [16..23]  ============================================= */
                                  /* PDU_CHnCTRL1_PTBBEN                                      */
#define PDU_CHnCTRL1_PTBBEN_0   0U    /* 0 : PDU channels corresponding pre-trigger back-to-back operation
                                                     disabled.                                                                 */
#define PDU_CHnCTRL1_PTBBEN_1   1U    /* 1 : PDU channels corresponding pre-trigger back-to-back operation
                                                     enabled.                                                                  */

/* ========================================================  CHnSTS  ========================================================= */
/* ==============================================  PDU CHnSTS CHPTEFLG [0..7]  ============================================== */
#define PDU_CHnSTS_CHPTEFLG_0     0U      /* 0 : Sequence error not detected on PDU channels corresponding
                                                     pre-trigger.                                                              */
#define PDU_CHnSTS_CHPTEFLG_1     1U      /* 1 : Sequence error detected on PDU channels corresponding pre-trigger.
                                                     ADCn block can be triggered for a conversion by one pre-trigger
                                                     from PDU channel n. When one conversion  which is triggered
                                                     by one of the pre-triggers from PDU channel n  is in progress
                                                     new trigger from PDU channels corresponding pre-trigger
                                                     m cannot be accepted by ADCn  and ERR[m] is set. Writing
                                                     0s to clear the sequence error flags.                                     */

/* =========================================================  CHnD0  ========================================================= */
/* =========================================================  CHnD1  ========================================================= */
/* =========================================================  CHnD2  ========================================================= */
/* =========================================================  CHnD3  ========================================================= */
/* =========================================================  CHnD4  ========================================================= */
/* =========================================================  CHnD5  ========================================================= */
/* =========================================================  CHnD6  ========================================================= */
/* =========================================================  CHnD7  ========================================================= */
/* =================================================  PDU POEN POEN [0..7]  ================================================= */
                                   /* PDU_POEN_POEN                                                            */
#define PDU_POEN_POEN_0                       0U      /* 0 : PDU Pulse-Out disabled                                         */
#define PDU_POEN_POEN_1                       1U      /* 1 : PDU Pulse-Out enabled                                          */

/* =========================================================  PODLY  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  DATA  ========================================================== */
/* ==========================================================  POLY  ========================================================== */
/* =========================================================  CTRL  ========================================================== */
/* ===============================================  CRC CTRL WIDCRCP [24..24]  =============================================== */
                                  /* CRC_CTRL_WIDCRCP                                                          */
#define CRC_CTRL_WIDCRCP_0                     0U      /* 0 : 16-bit CRC protocol.                                           */
#define CRC_CTRL_WIDCRCP_1                     1U      /* 1 : 32-bit CRC protocol.                                           */

/* ===============================================  CRC CTRL WASVAL [25..25]  ================================================ */
                                  /* CRC_CTRL_WASVAL                                                    */
#define CRC_CTRL_WASVAL_0                      0U      /* 0 : Writes to the CRC data register are data values.               */
#define CRC_CTRL_WASVAL_1                      1U      /* 1 : Writes to the CRC data register are seed values.               */

/* ==============================================  CRC CTRL XOR_RDATA [26..26]  ============================================== */
                                 /* CRC_CTRL_XOR_RDATA                                                 */
#define CRC_CTRL_XOR_RDATA_0                   0U      /* 0 : No XOR on reading.                                             */
#define CRC_CTRL_XOR_RDATA_1                   1U      /* 1 : Invert or complement the read value of the CRC Data register.  */

/* ===============================================  CRC CTRL TTRSEL [28..29]  ================================================ */
                                   /* CRC_CTRL_TTRSEL                                                    */
#define CRC_CTRL_TTRSEL_00                     0U      /* 00 : No transposition.                                             */
#define CRC_CTRL_TTRSEL_01                     1U      /* 01 : Bits in bytes are transposed; bytes are not transposed.       */
#define CRC_CTRL_TTRSEL_10                     2U      /* 10 : Both bits in bytes and bytes are transposed.                  */
#define CRC_CTRL_TTRSEL_11                     3U      /* 11 : Only bytes are transposed; no bits in a byte are transposed.  */

/* ===============================================  CRC CTRL TTWSEL [30..31]  ================================================ */
                                   /* CRC_CTRL_TTWSEL                                                    */
#define CRC_CTRL_TTWSEL_00                     0U      /* 00 : No transposition.                                             */
#define CRC_CTRL_TTWSEL_01                     1U      /* 01 : Bits in bytes are transposed; bytes are not transposed.       */
#define CRC_CTRL_TTWSEL_10                     2U      /* 10 : Both bits in bytes and bytes are transposed.                  */
#define CRC_CTRL_TTWSEL_11                     3U      /* 11 : Only bytes are transposed; no bits in a byte are transposed.  */



/* =========================================================================================================================== */
/* ================                                          LPITMR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* =========================================================  PARA  ========================================================= */
/* =========================================================  MCTRL  ========================================================= */
/* =============================================  LPITMR MCTRL PCLKTMREN [0..0]  ============================================= */
                                 /* LPITMR_MCTRL_PCLKTMREN                                                    */
#define LPITMR_MCTRL_PCLKTMREN_0               0U      /* 0 : Peripheral clock to timers is disabled                         */
#define LPITMR_MCTRL_PCLKTMREN_1               1U      /* 1 : Peripheral clock to timers is enabled                          */

/* ===============================================  LPITMR MCTRL SWRET [1..1]  =============================================== */
                                 /* LPITMR_MCTRL_SWRET                                                 */
#define LPITMR_MCTRL_SWRET_0                   0U      /* 0 : Timer channels and registers are not reset                     */
#define LPITMR_MCTRL_SWRET_1                   1U      /* 1 : Timer channels and registers are reset                         */

/* ==============================================  LPITMR MCTRL DOZEEN [2..2]  =============================================== */
                                  /* LPITMR_MCTRL_DOZEEN                                               */
#define LPITMR_MCTRL_DOZEEN_0                  0U      /* 0 : Timer channels are stopped in DOZE mode                        */
#define LPITMR_MCTRL_DOZEEN_1                  1U      /* 1 : Timer channels continue to run in DOZE mode                    */

/* ===============================================  LPITMR MCTRL DBGEN [3..3]  =============================================== */
                                  /* LPITMR_MCTRL_DBGEN                                                 */
#define LPITMR_MCTRL_DBGEN_0                   0U      /* 0 : Timer channels are stopped in Debug mode                       */
#define LPITMR_MCTRL_DBGEN_1                   1U      /* 1 : Timer channels continue to run in Debug mode                   */

/* =========================================================  MSTS  ========================================================== */
/* ==============================================  LPITMR MSTS TITFLG0 [0..0]  =============================================== */
                                  /* LPITMR_MSTS_TITFLG0                                                */
#define LPITMR_MSTS_TITFLG0_0                  0U      /* 0 : Timer has not timed out                                        */
#define LPITMR_MSTS_TITFLG0_1                  1U      /* 1 : Timeout has occurred                                           */

/* ==============================================  LPITMR MSTS TITFLG1 [1..1]  =============================================== */
                                 /* LPITMR_MSTS_TITFLG1                                                */
#define LPITMR_MSTS_TITFLG1_0                  0U      /* 0 : Timer has not timed out                                        */
#define LPITMR_MSTS_TITFLG1_1                  1U      /* 1 : Timeout has occurred                                           */

/* ==============================================  LPITMR MSTS TITFLG2 [2..2]  =============================================== */
                                  /* LPITMR_MSTS_TITFLG2                                                */
#define LPITMR_MSTS_TITFLG2_0                  0U      /* 0 : Timer has not timed out                                        */
#define LPITMR_MSTS_TITFLG2_1                  1U      /* 1 : Timeout has occurred                                           */

/* ==============================================  LPITMR MSTS TITFLG3 [3..3]  =============================================== */
                                  /* LPITMR_MSTS_TITFLG3                                                */
#define LPITMR_MSTS_TITFLG3_0                  0U      /* 0 : Timer has not timed out                                        */
#define LPITMR_MSTS_TITFLG3_1                  1U      /* 1 : Timeout has occurred                                           */

/* =========================================================  MIEN  ========================================================== */
/* ===============================================  LPITMR MIEN TIEN0 [0..0]  ================================================ */
                                 /* LPITMR_MIEN_TIEN0                                                  */
#define LPITMR_MIEN_TIEN0_0                    0U      /* 0 : Interrupt generation is disabled                               */
#define LPITMR_MIEN_TIEN0_1                    1U      /* 1 : Interrupt generation is enabled                                */

/* ===============================================  LPITMR MIEN TIEN1 [1..1]  ================================================ */
                                   /* LPITMR_MIEN_TIEN1                                                  */
#define LPITMR_MIEN_TIEN1_0                    0U      /* 0 : Interrupt generation is disabled                               */
#define LPITMR_MIEN_TIEN1_1                    1U      /* 1 : Interrupt generation is enabled                                */

/* ===============================================  LPITMR MIEN TIEN2 [2..2]  ================================================ */
                                 /* LPITMR_MIEN_TIEN2                                                  */
#define LPITMR_MIEN_TIEN2_0                    0U      /* 0 : Interrupt generation is disabled                               */
#define LPITMR_MIEN_TIEN2_1                    1U      /* 1 : Interrupt generation is enabled                                */

/* ===============================================  LPITMR MIEN TIEN3 [3..3]  ================================================ */
                                  /* LPITMR_MIEN_TIEN3                                                  */
#define LPITMR_MIEN_TIEN3_0                    0U      /* 0 : Interrupt generation is disabled                               */
#define LPITMR_MIEN_TIEN3_1                    1U      /* 1 : Interrupt generation is enabled                                */

/* ========================================================  STMREN  ========================================================= */
/* ==============================================  LPITMR STMREN TENCH0 [0..0]  ============================================== */
                                  /* LPITMR_STMREN_TENCH0                                               */
#define LPITMR_STMREN_TENCH0_0                 0U      /* 0 : No effect                                                      */
#define LPITMR_STMREN_TENCH0_1                 1U      /* 1 : Enables the Timer Channel 0                                    */

/* ==============================================  LPITMR STMREN TENCH1 [1..1]  ============================================== */
                                  /* LPITMR_STMREN_TENCH1                                               */
#define LPITMR_STMREN_TENCH1_0                 0U      /* 0 : No Effect                                                      */
#define LPITMR_STMREN_TENCH1_1                 1U      /* 1 : Enables the Timer Channel 1                                    */

/* ==============================================  LPITMR STMREN TENCH2 [2..2]  ============================================== */
                                 /* LPITMR_STMREN_TENCH2                                               */
#define LPITMR_STMREN_TENCH2_0                 0U      /* 0 : No Effect                                                      */
#define LPITMR_STMREN_TENCH2_1                 1U      /* 1 : Enables the Timer Channel 2                                    */

/* ==============================================  LPITMR STMREN TENCH3 [3..3]  ============================================== */
                                  /* LPITMR_STMREN_TENCH3                                               */
#define LPITMR_STMREN_TENCH3_0                 0U      /* 0 : No effect                                                      */
#define LPITMR_STMREN_TENCH3_1                 1U      /* 1 : Enables the Timer Channel 3                                    */

/* =======================================================  CLRTMREN  ======================================================== */
/* ===========================================  LPITMR CLRTMREN CLRTMREN0 [0..0]  ============================================ */
                                  /* LPITMR_CLRTMREN_CLRTMREN0                                          */
#define LPITMR_CLRTMREN_CLRTMREN0_0            0U      /* 0 : No action                                                      */
#define LPITMR_CLRTMREN_CLRTMREN0_1            1U      /* 1 : Clear T_EN bit for Timer Channel 0                             */

/* ===========================================  LPITMR CLRTMREN CLRTMREN1 [1..1]  ============================================ */
                                  /* LPITMR_CLRTMREN_CLRTMREN1                                          */
#define LPITMR_CLRTMREN_CLRTMREN1_0            0U      /* 0 : No Action                                                      */
#define LPITMR_CLRTMREN_CLRTMREN1_1            1U      /* 1 : Clear T_EN bit for Timer Channel 1                             */

/* ===========================================  LPITMR CLRTMREN CLRTMREN2 [2..2]  ============================================ */
                                 /* LPITMR_CLRTMREN_CLRTMREN2                                          */
#define LPITMR_CLRTMREN_CLRTMREN2_0            0U      /* 0 : No Action                                                      */
#define LPITMR_CLRTMREN_CLRTMREN2_1            1U      /* 1 : Clear T_EN bit for Timer Channel 2                             */

/* ===========================================  LPITMR CLRTMREN CLRTMREN3 [3..3]  ============================================ */
                                  /* LPITMR_CLRTMREN_CLRTMREN3                                          */
#define LPITMR_CLRTMREN_CLRTMREN3_0            0U      /* 0 : No Action                                                      */
#define LPITMR_CLRTMREN_CLRTMREN3_1            1U      /* 1 : Clear T_EN bit for Timer Channel 3                             */

/* ========================================================  TMRV  ======================================================== */
/* ==============================================  LPITMR TMRV TMRV [0..31]  ============================================== */
                                  /* LPITMR_TMRV_TMRV                                                */
#define LPITMR_TMRV_TMRV_0                  0U      /* 0 : Invalid load value in compare modes.                           */
#define LPITMR_TMRV_TMRV_1                  1U      /* 1 : Invalid load value in compare modes.                           */

/* =======================================================  CTMRV  ======================================================== */
/* =======================================================  TMRCTRL  ======================================================== */
/* =============================================  LPITMR TMRCTRL TMREN [0..0]  ============================================== */
                                  /* LPITMR_TMRCTRL_TMREN                                              */
#define LPITMR_TMRCTRL_TMREN_0                0U      /* 0 : Timer Channel is disabled                                      */
#define LPITMR_TMRCTRL_TMREN_1                1U      /* 1 : Timer Channel is enabled                                       */

/* ============================================  LPITMR TMRCTRL CHAINEN [1..1]  ============================================= */
                                  /* LPITMR_TMRCTRL_CHAINEN                                            */
#define LPITMR_TMRCTRL_CHAINEN_0              0U      /* 0 : Channel Chaining is disabled. Channel Timer runs independently.*/
#define LPITMR_TMRCTRL_CHAINEN_1              1U      /* 1 : Channel Chaining is enabled. Timer decrements on previous
                                                     channels timeout                                            */

/* ============================================  LPITMR TMRCTRL TMROMCFG [2..3]  ============================================ */
                                   /* LPITMR_TMRCTRL_TMROMCFG                                           */
#define LPITMR_TMRCTRL_TMROMCFG_0             0U      /* 0 : 32-bit Periodic Counter                                        */
#define LPITMR_TMRCTRL_TMROMCFG_1             1U      /* 1 : Dual 16-bit Periodic Counter                                   */
#define LPITMR_TMRCTRL_TMROMCFG_10            2U      /* 10 : 32-bit Trigger Accumulator                                    */
#define LPITMR_TMRCTRL_TMROMCFG_11            3U      /* 11 : 32-bit Trigger Input Capture                                  */

/* ===========================================  LPITMR TMRCTRL TMRDCTRL [16..16]  =========================================== */
                                  /* LPITMR_TMRCTRL_TMRDCTRL                                           */
#define LPITMR_TMRCTRL_TMRDCTRL_0             0U      /* 0 : Timer starts to decrement immediately based on restart condition
                                                     (controlled by TSOI bit)                                           */
#define LPITMR_TMRCTRL_TMRDCTRL_1             1U      /* 1 : Timer starts to decrement when rising edge on selected trigger
                                                     is detected                                                        */

/* ==========================================  LPITMR TMRCTRL TMRTOSCTRL [17..17]  ========================================== */
                                   /* LPITMR_TMRCTRL_TMRTOSCTRL                                         */
#define LPITMR_TMRCTRL_TMRTOSCTRL_0           0U      /* 0 : The channel timer does not stop after timeout.                 */
#define LPITMR_TMRCTRL_TMRTOSCTRL_1           1U      /* 1 : The channel timer will stop after a timeout  and the channel
                                                     timer will restart based on TSOT. When TSOT = 0  the channel
                                                     timer will restart after a rising edge on the T_EN bit
                                                     is detected (which means that the timer channel is disabled
                                                     and then enabled); when TSOT = 1  the channel timer will
                                                     restart after a rising edge on the selected trigger is
                                                     detected.                                                          */

/* ===========================================  LPITMR TMRCTRL TMRRCTRL [18..18]  =========================================== */
                                  /* LPITMR_TMRCTRL_TMRRCTRL                                           */
#define LPITMR_TMRCTRL_TMRRCTRL_0             0U      /* 0 : Timer will not reload on selected trigger                      */
#define LPITMR_TMRCTRL_TMRRCTRL_1             1U      /* 1 : Timer will reload on selected trigger                          */

/* ===========================================  LPITMR TMRCTRL TRGSSEL [23..23]  ============================================ */
                                  /* LPITMR_TMRCTRL_TRGSSEL                                            */
#define LPITMR_TMRCTRL_TRGSSEL_0              0U      /* 0 : Trigger source selected in external                            */
#define LPITMR_TMRCTRL_TRGSSEL_1              1U      /* 1 : Trigger source selected is the internal trigger                */




/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  TIMSEC  ========================================================= */
/* ========================================================  TIMPSC  ========================================================= */
/* ========================================================  TIMALR  ========================================================= */
/* =========================================================  TIMC  ========================================================== */
/* ================================================  RTC TIMC TIMCCFG [0..7]  ================================================ */
                                  /* RTC_TIMC_TIMCCFG                                                   */
#define RTC_TIMC_TIMCCFG_10000000              128U    /* 10000000 : Time Prescaler Register overflows every 32896 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_10000001              129U    /* 10000001 : Time Prescaler Register overflows every 32895 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_11111111              255U    /* 11111111 : Time Prescaler Register overflows every 32769 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_00000000              0U      /* 00000000 : Time Prescaler Register overflows every 32768 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_00000001              1U      /* 00000001 : Time Prescaler Register overflows every 32767 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_01111110              126U    /* 01111110 : Time Prescaler Register overflows every 32642 clock
                                                     cycles.                                                            */
#define RTC_TIMC_TIMCCFG_01111111              127U    /* 01111111 : Time Prescaler Register overflows every 32641 clock
                                                     cycles.                                                            */

/* =========================================================  CTRL  ========================================================== */
/* =================================================  RTC CTRL SWREN [0..0]  ================================================= */
                                  /* RTC_CTRL_SWREN                                                     */
#define RTC_CTRL_SWREN_0                       0U      /* 0 : No effect.                                                     */


/* ===============================================  RTC CTRL SACCCTRL [2..2]  ================================================ */
                                 /* RTC_CTRL_SACCCTRL                                                  */
#define RTC_CTRL_SACCCTRL_0                    0U      /* 0 : Non-supervisor mode write accesses are not supported and
                                                     generate a bus error.                                              */
#define RTC_CTRL_SACCCTRL_1                    1U      /* 1 : Non-supervisor mode write accesses are supported.              */

/* =================================================  RTC CTRL UMEN [3..3]  ================================================== */
                                  /* RTC_CTRL_UMEN                                                      */
#define RTC_CTRL_UMEN_0                        0U      /* 0 : Registers cannot be written when locked.                       */
#define RTC_CTRL_UMEN_1                        1U      /* 1 : Registers can be written when locked under limited conditions. */

/* ===============================================  RTC CTRL CLKPOSEL [5..5]  ================================================ */
                                 /* RTC_CTRL_CLKPOSEL                                                  */
#define RTC_CTRL_CLKPOSEL_0                    0U      /* 0 : The prescaler output clock (as configured by TSIC) is output
                                                     on RTC_CLKOUT.                                                     */
#define RTC_CTRL_CLKPOSEL_1                    1U      /* 1 : The RTC 32.768 kHz clock is output on RTC_CLKOUT  provided
                                                     it is output to other peripherals.                                 */

/* ================================================  RTC CTRL LPOCSEL [7..7]  ================================================ */
                                 /* RTC_CTRL_LPOCSEL                                                   */
#define RTC_CTRL_LPOCSEL_0                     0U      /* 0 : RTC prescaler increments using 32.768 kHz clock.               */
#define RTC_CTRL_LPOCSEL_1                     1U      /* 1 : RTC prescaler increments using 1 kHz LPO  bits [4:0] of
                                                     the prescaler are ignored.                                         */

/* ===============================================  RTC CTRL CLKOOUTEN [9..9]  =============================================== */
                                  /* RTC_CTRL_CLKOOUTEN                                                 */
#define RTC_CTRL_CLKOOUTEN_0                   0U      /* 0 : The 32 kHz clock is output to other peripherals.               */
#define RTC_CTRL_CLKOOUTEN_1                   1U      /* 1 : The 32 kHz clock is not output to other peripherals.           */

/* ===============================================  RTC CTRL CLKPEN [24..24]  ================================================ */
                                  /* RTC_CTRL_CLKPEN                                                    */
#define RTC_CTRL_CLKPEN_0                      0U      /* 0 : The RTC_CLKOUT function is disabled.                           */
#define RTC_CTRL_CLKPEN_1                      1U      /* 1 : Enable RTC_CLKOUT function.                                    */

/* ==========================================================  STS  ========================================================== */
/* ===============================================  RTC STS TIMINVFLG [0..0]  ================================================ */
                                  /* RTC_STS_TIMINVFLG                                                  */
#define RTC_STS_TIMINVFLG_0                    0U      /* 0 : Time is valid.                                                 */
#define RTC_STS_TIMINVFLG_1                    1U      /* 1 : Time is invalid and time counter is read as zero.              */

/* ===============================================  RTC STS TIMOVRFLG [1..1]  ================================================ */
                                  /* RTC_STS_TIMOVRFLG                                                  */
#define RTC_STS_TIMOVRFLG_0                    0U      /* 0 : Time overflow has not occurred.                                */
#define RTC_STS_TIMOVRFLG_1                    1U      /* 1 : Time overflow has occurred and time counter is read as zero.   */

/* ===============================================  RTC STS TIMALRFLG [2..2]  ================================================ */
                                   /* RTC_STS_TIMALRFLG                                                  */
#define RTC_STS_TIMALRFLG_0                    0U      /* 0 : Time alarm has not occurred.                                   */
#define RTC_STS_TIMALRFLG_1                    1U      /* 1 : Time alarm has occurred.                                       */

/* ================================================  RTC STS TIMCNTEN [4..4]  ================================================ */
                                   /* RTC_STS_TIMCNTEN                                                   */
#define RTC_STS_TIMCNTEN_0                     0U      /* 0 : Time counter is disabled.                                      */
#define RTC_STS_TIMCNTEN_1                     1U      /* 1 : Time counter is enabled.                                       */

/* =========================================================  LOCK  ========================================================== */
/* ================================================  RTC LOCK TIMCPRO [3..3]  ================================================ */
                               /* RTC_LOCK_TIMCPRO                                                   */
#define RTC_LOCK_TIMCPRO_0                     0U      /* 0 : Time Compensation Register is locked and writes are ignored.   */
#define RTC_LOCK_TIMCPRO_1                     1U      /* 1 : Time Compensation Register is not locked and writes complete
                                                     as normal.                                                         */

/* ================================================  RTC LOCK CTRLPRO [4..4]  ================================================ */
                                 /* RTC_LOCK_CTRLPRO                                                   */
#define RTC_LOCK_CTRLPRO_0                     0U      /* 0 : Control Register is locked and writes are ignored.             */
#define RTC_LOCK_CTRLPRO_1                     1U      /* 1 : Control Register is not locked and writes complete as normal.  */

/* ================================================  RTC LOCK STSPRO [5..5]  ================================================= */
                                  /* RTC_LOCK_STSPRO                                                    */
#define RTC_LOCK_STSPRO_0                      0U      /* 0 : Status Register is locked and writes are ignored.              */
#define RTC_LOCK_STSPRO_1                      1U      /* 1 : Status Register is not locked and writes complete as normal.   */

/* ================================================  RTC LOCK LOCKPRO [6..6]  ================================================ */
                                  /* RTC_LOCK_LOCKPRO                                                   */
#define RTC_LOCK_LOCKPRO_0                     0U      /* 0 : Lock Register is locked and writes are ignored.                */
#define RTC_LOCK_LOCKPRO_1                     1U      /* 1 : Lock Register is not locked and writes complete as normal.     */

/* =========================================================  IEN  ========================================================= */
/* ================================================  RTC IEN INVIEN [0..0]  ================================================ */
                                  /* RTC_IEN_INVIEN                                                   */
#define RTC_IEN_INVIEN_0                     0U      /* 0 : Time invalid flag does not generate an interrupt.              */
#define RTC_IEN_INVIEN_1                     1U      /* 1 : Time invalid flag does generate an interrupt.                  */

/* ================================================  RTC IEN OVRIEN [1..1]  ================================================ */
                                  /* RTC_IEN_OVRIEN                                                   */
#define RTC_IEN_OVRIEN_0                     0U      /* 0 : Time overflow flag does not generate an interrupt.             */
#define RTC_IEN_OVRIEN_1                     1U      /* 1 : Time overflow flag does generate an interrupt.                 */

/* ================================================  RTC IEN ALRIEN [2..2]  ================================================ */
                                  /* RTC_IEN_ALRIEN                                                   */
#define RTC_IEN_ALRIEN_0                     0U      /* 0 : Time alarm flag does not generate an interrupt.                */
#define RTC_IEN_ALRIEN_1                     1U      /* 1 : Time alarm flag does generate an interrupt.                    */

/* ================================================  RTC IEN SECIEN [4..4]  ================================================ */
                                  /* RTC_IEN_SECIEN                                                   */
#define RTC_IEN_SECIEN_0                     0U      /* 0 : Seconds interrupt is disabled.                                 */
#define RTC_IEN_SECIEN_1                     1U      /* 1 : Seconds interrupt is enabled.                                  */

/* =============================================  RTC IEN TSECICFG [16..18]  ============================================= */
                                   /* RTC_IEN_TSECICFG                                               */
#define RTC_IEN_TSECICFG_000               0U      /* 000 : 1 Hz.                                                        */
#define RTC_IEN_TSECICFG_001               1U      /* 001 : 2 Hz.                                                        */
#define RTC_IEN_TSECICFG_010               2U      /* 010 : 4 Hz.                                                        */
#define RTC_IEN_TSECICFG_011               3U      /* 011 : 8 Hz.                                                        */
#define RTC_IEN_TSECICFG_100               4U      /* 100 : 16 Hz.                                                       */
#define RTC_IEN_TSECICFG_101               5U      /* 101 : 32 Hz.                                                       */
#define RTC_IEN_TSECICFG_110               6U      /* 110 : 64 Hz.                                                       */
#define RTC_IEN_TSECICFG_111               7U      /* 111 : 128 Hz.                                                      */



/* =========================================================================================================================== */
/* ================                                           LPTMR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CSTS  ========================================================== */
/* ===============================================  LPTMR CSTS LPTMREN [0..0]  =============================================== */
                                   /* LPTMR_CSTS_LPTMREN                                                 */
#define LPTMR_CSTS_LPTMREN_0                   0U      /* 0 : LPTMR is disabled and internal logic is reset.                 */
#define LPTMR_CSTS_LPTMREN_1                   1U      /* 1 : LPTMR is enabled.                                              */

/* ===============================================  LPTMR CSTS TMRMCFG [1..1]  =============================================== */
                                   /* LPTMR_CSTS_TMRMCFG                                                 */
#define LPTMR_CSTS_TMRMCFG_0                   0U      /* 0 : Time Counter mode.                                             */
#define LPTMR_CSTS_TMRMCFG_1                   1U      /* 1 : Pulse Counter mode.                                            */

/* ================================================  LPTMR CSTS FRCNT [2..2]  ================================================ */
                                   /* LPTMR_CSTS_FRCNT                                                   */
#define LPTMR_CSTS_FRCNT_0                     0U      /* 0 : CNR is reset whenever TCF is set.                              */
#define LPTMR_CSTS_FRCNT_1                     1U      /* 1 : CNR is reset on overflow.                                      */

/* ===============================================  LPTMR CSTS TPIMSEL [3..3]  =============================================== */
                                  /* LPTMR_CSTS_TPIMSEL                                                 */
#define LPTMR_CSTS_TPIMSEL_0                   0U      /* 0 : Pulse Counter input source is active-high  and the CNR will
                                                     increment on the rising-edge.                                      */
#define LPTMR_CSTS_TPIMSEL_1                   1U      /* 1 : Pulse Counter input source is active-low  and the CNR will
                                                     increment on the falling-edge.                                     */

/* ===============================================  LPTMR CSTS TPISEL [4..5]  ================================================ */
                                  /* LPTMR_CSTS_TPISEL                                                  */
#define LPTMR_CSTS_TPISEL_00                   0U      /* 00 : Pulse counter input 0 is selected.                            */
#define LPTMR_CSTS_TPISEL_01                   1U      /* 01 : Pulse counter input 1 is selected.                            */
#define LPTMR_CSTS_TPISEL_10                   2U      /* 10 : Pulse counter input 2 is selected.                            */
#define LPTMR_CSTS_TPISEL_11                   3U      /* 11 : Pulse counter input 3 is selected.                            */

/* =================================================  LPTMR CSTS IEN [6..6]  ================================================= */
                                  /* LPTMR_CSTS_IEN                                                     */
#define LPTMR_CSTS_IEN_0                       0U      /* 0 : Timer interrupt disabled.                                      */
#define LPTMR_CSTS_IEN_1                       1U      /* 1 : Timer interrupt enabled.                                       */

/* ===============================================  LPTMR CSTS COMFLG [7..7]  ================================================ */
                                   /* LPTMR_CSTS_COMFLG                                                  */
#define LPTMR_CSTS_COMFLG_0                    0U      /* 0 : The value of CNR is not equal to CMR and increments.           */
#define LPTMR_CSTS_COMFLG_1                    1U      /* 1 : The value of CNR is equal to CMR and increments.               */

/* ===============================================  LPTMR CSTS DMAREN [8..8]  ================================================ */
                                   /* LPTMR_CSTS_DMAREN                                                  */
#define LPTMR_CSTS_DMAREN_0                    0U      /* 0 : Timer DMA Request disabled.                                    */
#define LPTMR_CSTS_DMAREN_1                    1U      /* 1 : Timer DMA Request enabled.                                     */

/* ==========================================================  PSC  ========================================================== */
/* ===============================================  LPTMR PSC PCLKSEL [0..1]  ================================================ */
                                   /* LPTMR_PSC_PCLKSEL                                                  */
#define LPTMR_PSC_PCLKSEL_00                   0U      /* 00 : Prescaler/glitch filter clock 0 selected.                     */
#define LPTMR_PSC_PCLKSEL_01                   1U      /* 01 : Prescaler/glitch filter clock 1 selected.                     */
#define LPTMR_PSC_PCLKSEL_10                   2U      /* 10 : Prescaler/glitch filter clock 2 selected.                     */
#define LPTMR_PSC_PCLKSEL_11                   3U      /* 11 : Prescaler/glitch filter clock 3 selected.                     */

/* ================================================  LPTMR PSC PBYPEN [2..2]  ================================================ */
                                   /* LPTMR_PSC_PBYPEN                                                   */
#define LPTMR_PSC_PBYPEN_0                     0U      /* 0 : Prescaler/glitch filter is enabled.                            */
#define LPTMR_PSC_PBYPEN_1                     1U      /* 1 : Prescaler/glitch filter is bypassed.                           */

/* ================================================  LPTMR PSC PVCFG [3..6]  ================================================= */
                                  /* LPTMR_PSC_PVCFG                                                    */
#define LPTMR_PSC_PVCFG_0000                   0U      /* 0000 : Prescaler divides the prescaler clock by 2; glitch filter
                                                     does not support this configuration.                               */
#define LPTMR_PSC_PVCFG_0001                   1U      /* 0001 : Prescaler divides the prescaler clock by 4; glitch filter
                                                     recognizes change on input pin after 2 rising clock edges.         */
#define LPTMR_PSC_PVCFG_0010                   2U      /* 0010 : Prescaler divides the prescaler clock by 8; glitch filter
                                                     recognizes change on input pin after 4 rising clock edges.         */
#define LPTMR_PSC_PVCFG_0011                   3U      /* 0011 : Prescaler divides the prescaler clock by 16; glitch filter
                                                     recognizes change on input pin after 8 rising clock edges.         */
#define LPTMR_PSC_PVCFG_0100                   4U      /* 0100 : Prescaler divides the prescaler clock by 32; glitch filter
                                                     recognizes change on input pin after 16 rising clock edges.        */
#define LPTMR_PSC_PVCFG_0101                   5U      /* 0101 : Prescaler divides the prescaler clock by 64; glitch filter
                                                     recognizes change on input pin after 32 rising clock edges.        */
#define LPTMR_PSC_PVCFG_0110                   6U      /* 0110 : Prescaler divides the prescaler clock by 128; glitch
                                                     filter recognizes change on input pin after 64 rising clock
                                                     edges.                                                             */
#define LPTMR_PSC_PVCFG_0111                   7U      /* 0111 : Prescaler divides the prescaler clock by 256; glitch
                                                     filter recognizes change on input pin after 128 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1000                   8U      /* 1000 : Prescaler divides the prescaler clock by 512; glitch
                                                     filter recognizes change on input pin after 256 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1001                   9U      /* 1001 : Prescaler divides the prescaler clock by 1024; glitch
                                                     filter recognizes change on input pin after 512 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1010                   10U     /* 1010 : Prescaler divides the prescaler clock by 2048; glitch
                                                     filter recognizes change on input pin after 1024 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1011                   11U     /* 1011 : Prescaler divides the prescaler clock by 4096; glitch
                                                     filter recognizes change on input pin after 2048 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1100                   12U     /* 1100 : Prescaler divides the prescaler clock by 8192; glitch
                                                     filter recognizes change on input pin after 4096 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1101                   13U     /* 1101 : Prescaler divides the prescaler clock by 16 384; glitch
                                                     filter recognizes change on input pin after 8192 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1110                   14U     /* 1110 : Prescaler divides the prescaler clock by 32 768; glitch
                                                     filter recognizes change on input pin after 16 384 rising
                                                     clock edges.                                                       */
#define LPTMR_PSC_PVCFG_1111                   15U     /* 1111 : Prescaler divides the prescaler clock by 65 536; glitch
                                                     filter recognizes change on input pin after 32 768 rising
                                                     clock edges.                                                       */


/* =========================================================  COMP  ========================================================== */
/* ==========================================================  CNT  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            SIM                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  CHIPCTRL  ======================================================== */
/* =============================================  SIM CHIPCTRL ADCIPSEL [0..3]  ============================================== */
                                  /* SIM_CHIPCTRL_ADCIPSEL                                              */
#define SIM_CHIPCTRL_ADCIPSEL_0000             0U      /* 0000 : Interleaving disabled. No channel pair interleaved. Interleaved
                                                     channels are individually connected to pins. PTC0 is connected
                                                     to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected
                                                     to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is
                                                     connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13
                                                     is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9.          */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_8           8U      /* 1xxx_8 : PTB14 to ADC1_SE9 and ADC0_SE9                */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_9           9U      /* 1xxx_9 : PTB14 to ADC1_SE9 and ADC0_SE9                            */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_10          10U     /* 1xxx_10 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_11          11U     /* 1xxx_11 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_12          12U     /* 1xxx_12 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_13          13U     /* 1xxx_13 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_14          14U     /* 1xxx_14 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_1xxx_15          15U     /* 1xxx_15 : PTB14 to ADC1_SE9 and ADC0_SE9                           */
#define SIM_CHIPCTRL_ADCIPSEL_x1xx_4           4U      /* x1xx_4 : PTB13 to ADC1_SE8 and ADC0_SE8                            */
#define SIM_CHIPCTRL_ADCIPSEL_x1xx_5           5U      /* x1xx_5 : PTB13 to ADC1_SE8 and ADC0_SE8                            */
#define SIM_CHIPCTRL_ADCIPSEL_x1xx_6           6U      /* x1xx_6 : PTB13 to ADC1_SE8 and ADC0_SE8                            */
#define SIM_CHIPCTRL_ADCIPSEL_x1xx_7           7U      /* x1xx_7 : PTB13 to ADC1_SE8 and ADC0_SE8                            */
#define SIM_CHIPCTRL_ADCIPSEL_xx1x_2           2U      /* xx1x_2 : PTB1 to ADC0_SE5 and ADC1_SE15                            */
#define SIM_CHIPCTRL_ADCIPSEL_xx1x_3           3U      /* xx1x_3 : PTB1 to ADC0_SE5 and ADC1_SE15                            */
#define SIM_CHIPCTRL_ADCIPSEL_xxx1_1           1U      /* xxx1_1 : PTB0 to ADC0_SE4 and ADC1_SE14                            */

/* =============================================  SIM CHIPCTRL CLKOUTSEL [4..7]  ============================================= */
                                  /* SIM_CHIPCTRL_CLKOUTSEL                                             */
#define SIM_CHIPCTRL_CLKOUTSEL_0000            0U      /* 0000 : SCG CLKOUT                                                  */
#define SIM_CHIPCTRL_CLKOUTSEL_0010            2U      /* 0010 : SYSOSC DIV2 CLK                                               */
#define SIM_CHIPCTRL_CLKOUTSEL_0100            4U      /* 0100 : LSI DIV2 CLK                                               */
#define SIM_CHIPCTRL_CLKOUTSEL_0101            5U      /* 0101 :  QSPI SFIF_CLK_HYP: Divide by 2 clock (configured
                                                     through SCLKCONFIG[5]) for HyperRAM going to sfif clock
                                                     to QSPI; For others: Reserved                                      */
#define SIM_CHIPCTRL_CLKOUTSEL_0110            6U      /* 0110 : HSI DIV2 CLK                                               */
#define SIM_CHIPCTRL_CLKOUTSEL_0111            7U      /* 0111 : HCLK                                                        */
#define SIM_CHIPCTRL_CLKOUTSEL_1000            8U      /* 1000 : SYSPLL DIV2 CLK                                               */
#define SIM_CHIPCTRL_CLKOUTSEL_1001            9U      /* 1001 : BUS_CLK                                                     */
#define SIM_CHIPCTRL_CLKOUTSEL_1010            10U     /* 1010 : LPO128K_CLK                                                 */
#define SIM_CHIPCTRL_CLKOUTSEL_1011            11U     /* 1011 :  QSPI IPG_CLK; For others: Reserved             */
#define SIM_CHIPCTRL_CLKOUTSEL_1100            12U     /* 1100 : LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]               */
#define SIM_CHIPCTRL_CLKOUTSEL_1101            13U     /* 1101 :  QSPI IPG_CLK_SFIF; For others: Reserved        */
#define SIM_CHIPCTRL_CLKOUTSEL_1110            14U     /* 1110 : RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]               */
#define SIM_CHIPCTRL_CLKOUTSEL_1111            15U     /* 1111 :  QSPI IPG_CLK_2XSFIF; For others: Reserved      */

/* ===========================================  SIM CHIPCTRL CLKOUTDIVCFG [8..10]  =========================================== */
                                   /* SIM_CHIPCTRL_CLKOUTDIVCFG                                          */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_000          0U      /* 000 : Divide by 1                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_001          1U      /* 001 : Divide by 2                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_010          2U      /* 010 : Divide by 3                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_011          3U      /* 011 : Divide by 4                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_100          4U      /* 100 : Divide by 5                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_101          5U      /* 101 : Divide by 6                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_110          6U      /* 110 : Divide by 7                                                  */
#define SIM_CHIPCTRL_CLKOUTDIVCFG_111          7U      /* 111 : Divide by 8                                                  */

/* ============================================  SIM CHIPCTRL CLKOUTEN [11..11]  ============================================ */
                                  /* SIM_CHIPCTRL_CLKOUTEN                                             */
#define SIM_CHIPCTRL_CLKOUTEN_0               0U      /* 0 : Clockout disable                                               */
#define SIM_CHIPCTRL_CLKOUTEN_1               1U      /* 1 : Clockout enable                                                */

/* ===========================================  SIM CHIPCTRL TRACECLKSEL [12..12]  =========================================== */
                                   /* SIM_CHIPCTRL_TRACECLKSEL                                           */
#define SIM_CHIPCTRL_TRACECLKSEL_0             0U      /* 0 : Core clock                                                     */
#define SIM_CHIPCTRL_TRACECLKSEL_1             1U      /* 1 : Platform clock                                                 */

/* ============================================  SIM CHIPCTRL PDUBBMSEL [13..13]  ============================================ */
                                 /* SIM_CHIPCTRL_PDUBBMSEL                                             */
#define SIM_CHIPCTRL_PDUBBMSEL_0               0U      /* 0 : PDU0 channel 0 back-to-back operation with ADC0 COCO[7:0]
                                                     and PDU1 channel 0 back-to-back operation with ADC1 COCO[7:0]      */
#define SIM_CHIPCTRL_PDUBBMSEL_1               1U      /* 1 : Channel 0 of PDU0 and PDU1 back-to-back operation with COCO[7:0]
                                                     of ADC0 and ADC1.                                                  */

/* =============================================  SIM CHIPCTRL ADCSSEL [16..18]  ============================================= */
                                  /* SIM_CHIPCTRL_ADCSSEL                                               */
#define SIM_CHIPCTRL_ADCSSEL_000             = 0U      /* 000 : 5 V input VDD supply (VDD)                                   */
#define SIM_CHIPCTRL_ADCSSEL_001             = 1U      /* 001 : 5 V input analog supply (VDDA)                               */
#define SIM_CHIPCTRL_ADCSSEL_010             = 2U      /* 010 : ADC Reference Supply (VREFH)                                 */
#define SIM_CHIPCTRL_ADCSSEL_011             = 3U      /* 011 : 3.3 V Oscillator Regulator Output (VDD_3V)                   */
#define SIM_CHIPCTRL_ADCSSEL_100             = 4U      /* 100 : 3.3 V flash regulator output (VDD_flash_3V)                  */
#define SIM_CHIPCTRL_ADCSSEL_101             = 5U      /* 101 : 1.2 V core regulator output (VDD_LV)                         */

/* ============================================  SIM CHIPCTRL ADCISMEN [19..19]  ============================================= */
                                /* SIM_CHIPCTRL_ADCISMEN                                              */
#define SIM_CHIPCTRL_ADCISMEN_0                0U      /* 0 : Disable internal supply monitoring                             */
#define SIM_CHIPCTRL_ADCISMEN_1                1U      /* 1 : Enable internal supply monitoring                              */

/* ============================================  SIM CHIPCTRL SRAMHREN [20..20]  ============================================= */
                                  /* SIM_CHIPCTRL_SRAMUREN                                              */
#define SIM_CHIPCTRL_SRAMUREN_0                0U      /* 0 : SRAMU contents are retained across resets                      */
#define SIM_CHIPCTRL_SRAMUREN_1                1U      /* 1 : No SRAMU retention                                             */

/* ============================================  SIM CHIPCTRL SRAMLREN [21..21]  ============================================= */
                                 /* SIM_CHIPCTRL_SRAMLREN                                              */
#define SIM_CHIPCTRL_SRAMLREN_0                0U      /* 0 : SRAML contents are retained across resets                      */
#define SIM_CHIPCTRL_SRAMLREN_1                1U      /* 1 : No SRAML retention                                             */

/* =======================================================  CFGTMROPT0  ======================================================== */
/* ============================================  SIM CFGTMROPT0 CFGTMR0FSxSEL [0..2]  ============================================= */
                                  /* SIM_CFGTMROPT0_CFGTMR0FSxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR0FSxSEL_000            0U      /* 000 : CFGTMR0_FLTx pin                                                */
#define SIM_CFGTMROPT0_CFGTMR0FSxSEL_001            1U      /* 001 : TRGMUX_CFGTMR0 out                                              */

/* ============================================  SIM CFGTMROPT0 CFGTMR1FSxSEL [4..6]  ============================================= */
                                  /* SIM_CFGTMROPT0_CFGTMR1FSxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR1FSxSEL_000            0U      /* 000 : CFGTMR1_FLTx pin                                                */
#define SIM_CFGTMROPT0_CFGTMR1FSxSEL_001            1U      /* 001 : TRGMUX_CFGTMR1 out                                              */

/* ============================================  SIM CFGTMROPT0 CFGTMR2FSxSEL [8..10]  ============================================ */
                                  /* SIM_CFGTMROPT0_CFGTMR2FSxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR2FSxSEL_000            0U      /* 000 : CFGTMR2_FLTx pin                                                */
#define SIM_CFGTMROPT0_CFGTMR2FSxSEL_001            1U      /* 001 : TRGMUX_CFGTMR2 out                                              */

/* ===========================================  SIM CFGTMROPT0 CFGTMR3FSxSEL [12..14]  ============================================ */
                                 /* SIM_CFGTMROPT0_CFGTMR3FSxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR3FSxSEL_000            0U      /* 000 : CFGTMR3_FLTx pin                                                */
#define SIM_CFGTMROPT0_CFGTMR3FSxSEL_001            1U      /* 001 : TRGMUX_CFGTMR3 out                                              */

/* ===========================================  SIM CFGTMROPT0 CFGTMR4TCLKxSEL [12..14]  ============================================ */
                                 /* SIM_CFGTMROPT0_CFGTMR4TCLKxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR4TCLKxSEL_000            0U      /* 000 : CFGTMR4 external clock driven by TCLK0 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR4TCLKxSEL_001            1U      /* 001 : CFGTMR4 external clock driven by TCLK1 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR4TCLKxSEL_010            0U      /* 000 : CFGTMR4 external clock driven by TCLK2 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR4TCLKxSEL_011            1U      /* 001 : No clock input                                                */

/* ===========================================  SIM CFGTMROPT0 CFGTMR5TCLKxSEL [12..14]  ============================================ */
                                 /* SIM_CFGTMROPT0_CFGTMR5TCLKxSEL                                            */
#define SIM_CFGTMROPT0_CFGTMR5TCLKxSEL_000            0U      /* 000 : CFGTMR5 external clock driven by TCLK0 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR5TCLKxSEL_001            1U      /* 001 : CFGTMR5 external clock driven by TCLK1 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR5TCLKxSEL_010            0U      /* 000 : CFGTMR5 external clock driven by TCLK2 pin.                     */
#define SIM_CFGTMROPT0_CFGTMR5TCLKxSEL_011            1U      /* 001 : No clock input                                                */

/* ========================================  SIM CFGTMROPT0 CFGTMR0EXCLKPINSEL [24..25]  ========================================= */
                                   /* SIM_CFGTMROPT0_CFGTMR0EXCLKPINSEL                                      */
#define SIM_CFGTMROPT0_CFGTMR0EXCLKPINSEL_00       0U      /* 00 : CFGTMR0 external clock driven by TCLK0 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR0EXCLKPINSEL_01       1U      /* 01 : CFGTMR0 external clock driven by TCLK1 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR0EXCLKPINSEL_10       2U      /* 10 : CFGTMR0 external clock driven by TCLK2 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR0EXCLKPINSEL_11       3U      /* 11 : No clock input                                                */

/* ========================================  SIM CFGTMROPT0 CFGTMR1EXCLKPINSEL [26..27]  ========================================= */
                                  /* SIM_CFGTMROPT0_CFGTMR1EXCLKPINSEL                                      */
#define SIM_CFGTMROPT0_CFGTMR1EXCLKPINSEL_00       0U      /* 00 : CFGTMR1 external clock driven by TCLK0 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR1EXCLKPINSEL_01       1U      /* 01 : CFGTMR1 external clock driven by TCLK1 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR1EXCLKPINSEL_10       2U      /* 10 : CFGTMR1 external clock driven by TCLK2 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR1EXCLKPINSEL_11       3U      /* 11 : No clock input                                                */

/* ========================================  SIM CFGTMROPT0 CFGTMR2EXCLKPINSEL [28..29]  ========================================= */
                                  /* SIM_CFGTMROPT0_CFGTMR2EXCLKPINSEL                                      */
#define SIM_CFGTMROPT0_CFGTMR2EXCLKPINSEL_00       0U      /* 00 : CFGTMR2 external clock driven by TCLK0 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR2EXCLKPINSEL_01       1U      /* 01 : CFGTMR2 external clock driven by TCLK1 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR2EXCLKPINSEL_10       2U      /* 10 : CFGTMR2 external clock driven by TCLK2 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR2EXCLKPINSEL_11       3U      /* 11 : No clock input                                                */

/* ========================================  SIM CFGTMROPT0 CFGTMR3EXCLKPINSEL [30..31]  ========================================= */
                                  /* SIM_CFGTMROPT0_CFGTMR3EXCLKPINSEL                                      */
#define SIM_CFGTMROPT0_CFGTMR3EXCLKPINSEL_00       0U      /* 00 : CFGTMR3 external clock driven by TCLK0 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR3EXCLKPINSEL_01       1U      /* 01 : CFGTMR3 external clock driven by TCLK1 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR3EXCLKPINSEL_10       2U      /* 10 : CFGTMR3 external clock driven by TCLK2 pin.                      */
#define SIM_CFGTMROPT0_CFGTMR3EXCLKPINSEL_11       3U      /* 11 : No clock input                                                */

/* =======================================================  LPOCLKSEL  ======================================================= */
/* ===========================================  SIM LPOCLKSEL LPO1KCLKOEN [0..0]  ============================================ */
                                 /* SIM_LPOCLKSEL_LPO1KCLKOEN                                          */
#define SIM_LPOCLKSEL_LPO1KCLKOEN_0            0U      /* 0 : Disable 1 kHz LPO_CLK output                                   */
#define SIM_LPOCLKSEL_LPO1KCLKOEN_1            1U      /* 1 : Enable 1 kHz LPO_CLK output                                    */

/* ===========================================  SIM LPOCLKSEL LPO32KCLKOEN [1..1]  =========================================== */
                                   /* SIM_LPOCLKSEL_LPO32KCLKOEN                                         */
#define SIM_LPOCLKSEL_LPO32KCLKOEN_0           0U      /* 0 : Disable 32 kHz LPO_CLK output                                  */
#define SIM_LPOCLKSEL_LPO32KCLKOEN_1           1U      /* 1 : Enable 32 kHz LPO_CLK output                                   */

/* ============================================  SIM LPOCLKSEL CLKLPOSSEL [2..3]  ============================================ */
                                  /* SIM_LPOCLKSEL_CLKLPOSSEL                                           */
#define SIM_LPOCLKSEL_CLKLPOSSEL_00            0U      /* 00 : 128 kHz LPO_CLK                                               */
#define SIM_LPOCLKSEL_CLKLPOSSEL_01            1U      /* 01 : No clock                                                      */
#define SIM_LPOCLKSEL_CLKLPOSSEL_10            2U      /* 10 : 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK      */
#define SIM_LPOCLKSEL_CLKLPOSSEL_11            3U      /* 11 : 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK       */

/* ============================================  SIM LPOCLKSEL CLK32KSSEL [4..5]  ============================================ */
                                  /* SIM_LPOCLKSEL_CLK32KSSEL                                           */
#define SIM_LPOCLKSEL_CLK32KSSEL_00            0U      /* 00 : SYSOSCDIV1_CLK                                                  */
#define SIM_LPOCLKSEL_CLK32KSSEL_01            1U      /* 01 : 32 kHz LPO_CLK                                                */
#define SIM_LPOCLKSEL_CLK32KSSEL_10            2U      /* 10 : RTC_CLKIN clock                                               */
#define SIM_LPOCLKSEL_CLK32KSSEL_11            3U      /* 11 : HSIDIV1_CLK                                                  */

/* ========================================================  ADCOPT  ========================================================= */
/* =============================================  SIM ADCOPT ADC0TRGSSEL [0..0]  ============================================= */
                                   /* SIM_ADCOPT_ADC0TRGSSEL                                             */
#define SIM_ADCOPT_ADC0TRGSSEL_0               0U      /* 0 : PDU output                                                     */
#define SIM_ADCOPT_ADC0TRGSSEL_1               1U      /* 1 : TRGMUX output                                                  */

/* =============================================  SIM ADCOPT ADC0SWPTSEL [1..3]  ============================================= */
                                   /* SIM_ADCOPT_ADC0SWPTSEL                                             */
#define SIM_ADCOPT_ADC0SWPTSEL_000             0U      /* 000 : Software pretrigger disabled                                 */
#define SIM_ADCOPT_ADC0SWPTSEL_001             1U      /* 001 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_010             2U      /* 010 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_011             3U      /* 011 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_100             4U      /* 100 : Software pretrigger 0                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_101             5U      /* 101 : Software pretrigger 1                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_110             6U      /* 110 : Software pretrigger 2                                        */
#define SIM_ADCOPT_ADC0SWPTSEL_111             7U      /* 111 : Software pretrigger 3                                        */

/* =============================================  SIM ADCOPT ADC0PTSSEL [4..5]  ============================================== */
                                  /* SIM_ADCOPT_ADC0PTSSEL                                              */
#define SIM_ADCOPT_ADC0PTSSEL_00               0U      /* 00 : PDU pretrigger (default)                                      */
#define SIM_ADCOPT_ADC0PTSSEL_01               1U      /* 01 : TRGMUX pretrigger                                             */
#define SIM_ADCOPT_ADC0PTSSEL_10               2U      /* 10 : Software pretrigger                                           */

/* =============================================  SIM ADCOPT ADC1TRGSSEL [8..8]  ============================================= */
                                  /* SIM_ADCOPT_ADC1TRGSSEL                                             */
#define SIM_ADCOPT_ADC1TRGSSEL_0               0U      /* 0 : PDU output                                                     */
#define SIM_ADCOPT_ADC1TRGSSEL_1               1U      /* 1 : TRGMUX output                                                  */

/* ============================================  SIM ADCOPT ADC1SWPTSEL [9..11]  ============================================= */
                                /* SIM_ADCOPT_ADC1SWPTSEL                                             */
#define SIM_ADCOPT_ADC1SWPTSEL_000             0U      /* 000 : Software pretrigger disabled                                 */
#define SIM_ADCOPT_ADC1SWPTSEL_001             1U      /* 001 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_010             2U      /* 010 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_011             3U      /* 011 : Reserved (do not use)                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_100             4U      /* 100 : Software pretrigger 0                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_101             5U      /* 101 : Software pretrigger 1                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_110             6U      /* 110 : Software pretrigger 2                                        */
#define SIM_ADCOPT_ADC1SWPTSEL_111             7U      /* 111 : Software pretrigger 3                                        */

/* ============================================  SIM ADCOPT ADC1PTSSEL [12..13]  ============================================= */
                                   /* SIM_ADCOPT_ADC1PTSSEL                                              */
#define SIM_ADCOPT_ADC1PTSSEL_00               0U      /* 00 : PDU pretrigger (default)                                      */
#define SIM_ADCOPT_ADC1PTSSEL_01               1U      /* 01 : TRGMUX pretrigger                                             */
#define SIM_ADCOPT_ADC1PTSSEL_10               2U      /* 10 : Software pretrigger                                           */

/* =======================================================  CFGTMROPT1  ======================================================== */
/* ===========================================  SIM CFGTMROPT1 CFGTMR1CH0ISEL [4..5]  ============================================ */
                                  /* SIM_CFGTMROPT1_CFGTMR1CH0ISEL                                          */
#define SIM_CFGTMROPT1_CFGTMR1CH0ISEL_00           0U      /* 00 : CFGTMR1_CH0 input                                                */
#define SIM_CFGTMROPT1_CFGTMR1CH0ISEL_01           1U      /* 01 : CMP0 output                                                   */

/* ===========================================  SIM CFGTMROPT1 CFGTMR2CH0ISEL [6..7]  ============================================ */
                                /* SIM_CFGTMROPT1_CFGTMR2CH0ISEL                                          */
#define SIM_CFGTMROPT1_CFGTMR2CH0ISEL_00           0U      /* 00 : CFGTMR2_CH0 input                                                */
#define SIM_CFGTMROPT1_CFGTMR2CH0ISEL_01           1U      /* 01 : CMP0 output                                                   */

/* ===========================================  SIM CFGTMROPT1 CFGTMR2CH1ISEL [8..8]  ============================================ */
                                  /* SIM_CFGTMROPT1_CFGTMR2CH1ISEL                                          */
#define SIM_CFGTMROPT1_CFGTMR2CH1ISEL_0            0U      /* 0 : CFGTMR2_CH1 input                                                 */
#define SIM_CFGTMROPT1_CFGTMR2CH1ISEL_1            1U      /* 1 : exclusive OR of CFGTMR2_CH0 CFGTMR2_CH1 and CFGTMR1_CH1                 */

/* ===========================================  SIM CFGTMROPT1 CFGTMRGLDMEN [15..15]  ============================================ */
                                 /* SIM_CFGTMROPT1_CFGTMRGLDMEN                                            */
#define SIM_CFGTMROPT1_CFGTMRGLDMEN_0              0U      /* 0 : CFGTMR Global load mechanism disabled.                            */
#define SIM_CFGTMROPT1_CFGTMRGLDMEN_1              1U      /* 1 : CFGTMR Global load mechanism enabled                              */

/* ============================================  SIM CFGTMROPT1 CFGTMR0MEN [16..23]  ============================================= */
                                   /* SIM_CFGTMROPT1_CFGTMR0MEN                                              */
#define SIM_CFGTMROPT1_CFGTMR0MEN_00000000         0U      /* 00000000 : No modulation with CFGTMR1_CH1                             */
#define SIM_CFGTMROPT1_CFGTMR0MEN_00000001         1U      /* 00000001 : Modulation with CFGTMR1_CH1                                */

/* ============================================  SIM CFGTMROPT1 CFGTMR3MEN [24..31]  ============================================= */
                                   /* SIM_CFGTMROPT1_CFGTMR3MEN                                              */
#define SIM_CFGTMROPT1_CFGTMR3MEN_00000000         0U      /* 00000000 : No modulation with CFGTMR2_CH1                             */
#define SIM_CFGTMROPT1_CFGTMR3MEN_00000001         1U      /* 00000001 : Modulation with CFGTMR2_CH1                                */

/* ========================================================  MCTRL0  ========================================================= */
/* ==============================================  SIM MCTRL0 STOP1MON [9..9]  =============================================== */
                                  /* SIM_MCTRL0_STOP1MON                                                */
#define SIM_MCTRL0_STOP1MON_0                  0U      /* 0 : Bus clock enabled or STOP1 entry aborted                       */
#define SIM_MCTRL0_STOP1MON_1                  1U      /* 1 : STOP1 entry successful                                         */

/* =============================================  SIM MCTRL0 STOP2MON [10..10]  ============================================== */
                                  /* SIM_MCTRL0_STOP2MON                                                */
#define SIM_MCTRL0_STOP2MON_0                  0U      /* 0 : System clock enabled or STOP2 entry aborted                    */
#define SIM_MCTRL0_STOP2MON_1                  1U      /* 1 : STOP2 entry successful                                         */

/* ============================================  SIM MCTRL0 CFGTMRSTBEN_D [14..14]  ============================================ */
                                 /* SIM_MCTRL0_CFGTMRSTBEN_D                                             */
#define SIM_MCTRL0_CFGTMRSTBEN_D_0               0U      /* 0 : All the CFGTMRs have a single global time-base                    */
#define SIM_MCTRL0_CFGTMRSTBEN_D_1               1U      /* 1 : CFGTMR0-3 have a common time-base and others have a different
                                                     common time-base                                                   */

/* ===========================================  SIM MCTRL0 CFGTMR0OBECTRL [16..16]  ============================================ */
                                   /* SIM_MCTRL0_CFGTMR0OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR0OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR0OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */

/* ===========================================  SIM MCTRL0 CFGTMR1OBECTRL [17..17]  ============================================ */
                                  /* SIM_MCTRL0_CFGTMR1OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR1OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR1OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */

/* ===========================================  SIM MCTRL0 CFGTMR2OBECTRL [18..18]  ============================================ */
                               /* SIM_MCTRL0_CFGTMR2OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR2OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR2OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */

/* ===========================================  SIM MCTRL0 CFGTMR3OBECTRL [19..19]  ============================================ */
                                  /* SIM_MCTRL0_CFGTMR3OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR3OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR3OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */

/* ===========================================  SIM MCTRL0 CFGTMR4OBECTRL [20..20]  ============================================ */
                                  /* SIM_MCTRL0_CFGTMR3OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR4OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR4OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */

/* ===========================================  SIM MCTRL0 CFGTMR5OBECTRL [21..21]  ============================================ */
                                  /* SIM_MCTRL0_CFGTMR5OBECTRL                                            */
#define SIM_MCTRL0_CFGTMR5OBECTRL_0              0U      /* 0 : The CFGTMR channel output is put to safe state when the CFGTMR
                                                     counter is enabled and the CFGTMR channel output is enabled
                                                     by Fault Control (CFGTMR_FMSEL[FCTRLMSEL]!=2b00 and CFGTMR_FCTRL[FEOSTS]=1b0)
                                                     and PWM is enabled (CFGTMR_CSTS[PWMOENCHn] = 1b1). Otherwise the
                                                     channel output is tristated.                                       */
#define SIM_MCTRL0_CFGTMR5OBECTRL_1              1U      /* 1 : The CFGTMR channel output state is retained when the channel
                                                     is in output mode. The output channel is tristated when
                                                     the channel is in input capture [DECMEN=1b0  CHCM=1b0
                                                     MSnB:MSnA=2b00] or dual edge capture mode [DECMEN=1b1].           */


/* =======================================================  SYSDEVID  ======================================================== */
/* ===============================================  SIM SYSDEVID APOC [8..11]  =============================================== */
                                   /* SIM_SYSDEVID_APOC                                                  */
#define SIM_SYSDEVID_APOC_0010                 2U      /* 0010 : 48 LQFP                                                     */
#define SIM_SYSDEVID_APOC_0011                 3U      /* 0011 : 64 LQFP                                                     */
#define SIM_SYSDEVID_APOC_0100                 4U      /* 0100 : 100 LQFP                                                    */
#define SIM_SYSDEVID_APOC_0110                 6U      /* 0110 : 144 LQFP                                                    */
#define SIM_SYSDEVID_APOC_0111                 7U      /* 0111 : 176 LQFP                                                    */
#define SIM_SYSDEVID_APOC_1000                 8U      /* 1000 : 100 MAP BGA                                                 */

/* =======================================================  PCLKGCTRL  ======================================================= */
/* =============================================  SIM PCLKGCTRL MSCCLKEN [0..0]  ============================================= */
                                   /* SIM_PCLKGCTRL_MSCCLKEN                                             */
#define SIM_PCLKGCTRL_MSCCLKEN_0               0U      /* 0 : Clock disabled                                                 */
#define SIM_PCLKGCTRL_MSCCLKEN_1               1U      /* 1 : Clock enabled                                                  */

/* =============================================  SIM PCLKGCTRL MPUCLKEN [1..1]  ============================================= */
                                  /* SIM_PCLKGCTRL_MPUCLKEN                                             */
#define SIM_PCLKGCTRL_MPUCLKEN_0               0U      /* 0 : Clock disabled                                                 */
#define SIM_PCLKGCTRL_MPUCLKEN_1               1U      /* 1 : Clock enabled                                                  */

/* =============================================  SIM PCLKGCTRL DMACLKEN [2..2]  ============================================= */
                                  /* SIM_PCLKGCTRL_DMACLKEN                                             */
#define SIM_PCLKGCTRL_DMACLKEN_0               0U      /* 0 : Clock disabled                                                 */
#define SIM_PCLKGCTRL_DMACLKEN_1               1U      /* 1 : Clock enabled                                                  */

/* ============================================  SIM PCLKGCTRL EREPCLKEN [3..3]  ============================================= */
                                  /* SIM_PCLKGCTRL_EREPCLKEN                                            */
#define SIM_PCLKGCTRL_EREPCLKEN_0              0U      /* 0 : Clock disabled                                                 */
#define SIM_PCLKGCTRL_EREPCLKEN_1              1U      /* 1 : Clock enabled                                                  */

/* =============================================  SIM PCLKGCTRL EINJCLKEN [4..4]  ============================================= */
                                  /* SIM_PCLKGCTRL_EINJCLKEN                                             */
#define SIM_PCLKGCTRL_EINJCLKEN_0               0U      /* 0 : Clock disabled                                                 */
#define SIM_PCLKGCTRL_EINJCLKEN_1               1U      /* 1 : Clock enabled                                                  */

/* =======================================================  FLASHCFG1  ======================================================= */
/* ============================================  SIM FLASHCFG1 EEERAMDS [16..19]  ============================================ */
                                  /* SIM_FLASHCFG1_EEERAMDS                                             */
#define SIM_FLASHCFG1_EEERAMDS_0010            2U      /* 0010 : 4 KB                                                        */
#define SIM_FLASHCFG1_EEERAMDS_0011            3U      /* 0011 : 2 KB                                                        */
#define SIM_FLASHCFG1_EEERAMDS_0100            4U      /* 0100 : 1 KB                                                        */
#define SIM_FLASHCFG1_EEERAMDS_0101            5U      /* 0101 : 512 Bytes                                                   */
#define SIM_FLASHCFG1_EEERAMDS_0110            6U      /* 0110 : 256 Bytes                                                   */
#define SIM_FLASHCFG1_EEERAMDS_0111            7U      /* 0111 : 128 Bytes                                                   */
#define SIM_FLASHCFG1_EEERAMDS_1000            8U      /* 1000 : 64 Bytes                                                    */
#define SIM_FLASHCFG1_EEERAMDS_1001            9U      /* 1001 : 32 Bytes                                                    */
#define SIM_FLASHCFG1_EEERAMDS_1111            15U     /* 1111 : 0 Bytes                                                     */

/* =======================================================  UID127_96  ======================================================= */
/* =======================================================  UID95_64  ======================================================== */
/* =======================================================  UID63_32  ======================================================== */
/* ========================================================  UID31_0  ======================================================== */
/* ======================================================  SYSCLKDIV4  ======================================================= */
/* ===========================================  SIM SYSCLKDIV4 DTRACEDEN [28..28]  =========================================== */
                                   /* SIM_SYSCLKDIV4_DTRACEDEN                                           */
#define SIM_SYSCLKDIV4_DTRACEDEN_0             0U      /* 0 : Debug trace divider disabled                                   */
#define SIM_SYSCLKDIV4_DTRACEDEN_1             1U      /* 1 : Debug trace divider enabled                                    */

/* ========================================================  MCTRL1  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            PM                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  PINCTRL  ======================================================== */
/* =======================================================  GPINCTRLL  ======================================================= */
/* =============================================  PM GPINCTRLL PINEN [16..31]  ============================================== */
                                  /* PM_GPINCTRLL_PINEN                                                       */
#define PM_GPINCTRLL_PINEN_0                0U      /* 0 : Corresponding Pin Control Register is not updated with the
                                                     value in GPWD.                                                            */
#define PM_GPINCTRLL_PINEN_1                1U      /* 1 : Corresponding Pin Control Register is updated with the value
                                                     in GPWD.                                                                  */


/* =======================================================  GPINCTRLH  ======================================================= */
/* =============================================  PM GPINCTRLH PINEN [16..31]  ============================================== */
                                  /* PM_GPINCTRLH_PINEN                                                       */
#define PM_GPINCTRLH_PINEN_0                0U      /* 0 : Corresponding Pin Control Register is not updated with the
                                                     value in GPWD.                                                            */
#define PM_GPINCTRLH_PINEN_1                1U      /* 1 : Corresponding Pin Control Register is updated with the value
                                                     in GPWD.                                                                  */


/* =======================================================  GINTCTRLL  ======================================================= */
/* ==============================================  PM GINTCTRLL INTW [0..15]  =============================================== */
                                  /* PM_GINTCTRLL_INTW                                                        */
#define PM_GINTCTRLL_INTW_0                 0U      /* 0 : Corresponding Pin Control Register is not updated with the
                                                     value in GPWD.                                                            */
#define PM_GINTCTRLL_INTW_1                 1U      /* 1 : Corresponding Pin Control Register is updated with the value
                                                     in GPWD.                                                                  */


/* =======================================================  GINTCTRLH  ======================================================= */
/* ==============================================  PM GINTCTRLH INTEN [0..15]  ============================================== */
                                  /* PM_GINTCTRLH_INTEN                                                       */
#define PM_GINTCTRLH_INTEN_0                0U      /* 0 : Corresponding Pin Control Register is not updated with the
                                                     value in GPWD.                                                            */
#define PM_GINTCTRLH_INTEN_1                1U      /* 1 : Corresponding Pin Control Register is updated with the value
                                                     in GPWD.                                                                  */


/* ========================================================  INTSTS  ========================================================= */
/* ==============================================  PM INTSTS INTFLG [0..31]  =============================================== */
                                  /* PM_INTSTS_INTSFLG                                                        */
#define PM_INTSTS_INTSFLG_0                 0U      /* 0 : Configured interrupt is not detected.                                 */
#define PM_INTSTS_INTSFLG_1                 1U      /* 1 : Configured interrupt is detected. If the pin is configured
                                                     to generate a DMA request, then the corresponding flag
                                                     will be cleared automatically at the completion of the
                                                     requested DMA transfer. Otherwise, the flag remains set
                                                     until a logic 1 is written to the flag. If the pin is configured
                                                     for a level sensitive interrupt and the pin remains asserted,
                                                     then the flag is set again immediately after it is cleared.               */


/* =========================================================  DFEN  ========================================================== */
/* ================================================  PM DFEN DOFEN [0..31]  ================================================= */
                                  /* PM_DFEN_DOFEN                                                            */
#define PM_DFEN_DOFEN_0                     0U      /* 0 : Digital filter is disabled on the corresponding pin and
                                                     output of the digital filter is reset to zero.                            */
#define PM_DFEN_DOFEN_1                     1U      /* 1 : Digital filter is enabled on the corresponding pin, if the
                                                     pin is configured as a digital input.                                     */


/* =========================================================  DFCLKS  ========================================================= */
/* =================================================  PM DFCLKS DFCLKSS [0..0]  ================================================= */
                                  /* PM_DFCLKS_DFCLKSS                                                            */
#define PM_DFCLKS_DFCLKSS_0                     0U      /* 0 : Digital filters are clocked by the bus clock.                         */
#define PM_DFCLKS_DFCLKSS_1                     1U      /* 1 : Digital filters are clocked by the LPO clock.                         */


/* =========================================================  DFWID  ========================================================= */



/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CSTS  ========================================================== */
/* ================================================  WDT CSTS STOPEN [0..0]  ================================================= */
                                 /* WDT_CSTS_STOPEN                                                    */
#define WDT_CSTS_STOPEN_0                      0U      /* 0 : Watchdog disabled in chip stop mode.                           */
#define WDT_CSTS_STOPEN_1                      1U      /* 1 : Watchdog enabled in chip stop mode.                            */

/* ==================================================  WDT CSTS WEN [1..1]  ================================================== */
                                  /* WDT_CSTS_WEN                                                       */
#define WDT_CSTS_WEN_0                         0U      /* 0 : Watchdog disabled in chip wait mode.                           */
#define WDT_CSTS_WEN_1                         1U      /* 1 : Watchdog enabled in chip wait mode.                            */

/* =================================================  WDT CSTS DBGEN [2..2]  ================================================= */
                                 /* WDT_CSTS_DBGEN                                                     */
#define WDT_CSTS_DBGEN_0                       0U      /* 0 : Watchdog disabled in chip debug mode.                          */
#define WDT_CSTS_DBGEN_1                       1U      /* 1 : Watchdog enabled in chip debug mode.                           */

/* =================================================  WDT CSTS FTEN [3..4]  ================================================== */
                                /* WDT_CSTS_FTEN                                                      */
#define WDT_CSTS_FTEN_00                       0U      /* 00 : Watchdog test mode disabled.                                  */
#define WDT_CSTS_FTEN_01                       1U      /* 01 : Watchdog user mode enabled. (Watchdog test mode disabled.)
                                                     After testing the watchdog  software should use this setting
                                                     to indicate that the watchdog is functioning normally in
                                                     user mode.                                                                */
#define WDT_CSTS_FTEN_10                       2U      /* 10 : Watchdog test mode enabled  only the low byte is used.
                                                     CNT[CNTLOW] is compared with TOVAL[TOVALLOW].                             */
#define WDT_CSTS_FTEN_11                       3U      /* 11 : Watchdog test mode enabled  only the high byte is used.
                                                     CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].                           */

/* ================================================  WDT CSTS RECFGEN [5..5]  ================================================ */
                                  /* WDT_CSTS_RECFGEN                                                          */
#define WDT_CSTS_RECFGEN_0                     0U      /* 0 : Updates not allowed. After the initial configuration  the
                                                     watchdog cannot be later modified without forcing a reset.                */
#define WDT_CSTS_RECFGEN_1                     1U      /* 1 : Updates allowed. Software can modify the watchdog configuration
                                                     registers within 8d128 bus clocks after performing the
                                                     unlock write sequence.                                                    */

/* ================================================  WDT CSTS WDTIEN [6..6]  ================================================= */
                                   /* WDT_CSTS_WDTIEN                                                           */
#define WDT_CSTS_WDTIEN_0                      0U      /* 0 : Watchdog interrupts are disabled. Watchdog resets are not
                                                     delayed.                                                                  */
#define WDT_CSTS_WDTIEN_1                      1U      /* 1 : Watchdog interrupts are enabled. Watchdog resets are delayed
                                                     by 8d128 bus clocks from the interrupt vector fetch.                      */

/* =================================================  WDT CSTS CNTEN [7..7]  ================================================= */
                                 /* WDT_CSTS_CNTEN                                                            */
#define WDT_CSTS_CNTEN_0                       0U      /* 0 : Watchdog disabled.                                             */
#define WDT_CSTS_CNTEN_1                       1U      /* 1 : Watchdog enabled.                                              */

/* ===============================================  WDT CSTS CLKSRCSEL [8..9]  =============================================== */
                                   /* WDT_CSTS_CLKSRCSEL                                                 */
#define WDT_CSTS_CLKSRCSEL_00                  0U      /* 00 : Bus clock                                                     */
#define WDT_CSTS_CLKSRCSEL_01                  1U      /* 01 : LPO clock                                                     */
#define WDT_CSTS_CLKSRCSEL_10                  2U      /* 10 : INTCLK (internal clock)                                       */
#define WDT_CSTS_CLKSRCSEL_11                  3U      /* 11 : ERCLK (external reference clock)                              */

/* ==============================================  WDT CSTS RCSUSFLG [10..10]  =============================================== */
                                   /* WDT_CSTS_RCSUSFLG                                                  */
#define WDT_CSTS_RCSUSFLG_0                    0U      /* 0 : Reconfiguring WDOG.                                            */
#define WDT_CSTS_RCSUSFLG_1                    1U      /* 1 : Reconfiguration is successful.                                 */

/* ================================================  WDT CSTS ULFLG [11..11]  ================================================ */
                                   /* WDT_CSTS_ULFLG                                                     */
#define WDT_CSTS_ULFLG_0                       0U      /* 0 : WDOG is locked.                                                */
#define WDT_CSTS_ULFLG_1                       1U      /* 1 : WDOG is unlocked.                                              */

/* ================================================  WDT CSTS PSCEN [12..12]  ================================================ */
                                 /* WDT_CSTS_PSCEN                                                     */
#define WDT_CSTS_PSCEN_0                       0U      /* 0 : 256 prescaler disabled.                                        */
#define WDT_CSTS_PSCEN_1                       1U      /* 1 : 256 prescaler enabled.                                         */

/* ===============================================  WDT CSTS CMDEN32 [13..13]  =============================================== */
                                  /* WDT_CSTS_CMDEN32                                                   */
#define WDT_CSTS_CMDEN32_0                     0U      /* 0 : Disables support for 32-bit refresh/unlock command write
                                                     words. Only 16-bit or 8-bit is supported.                          */
#define WDT_CSTS_CMDEN32_1                     1U      /* 1 : Enables support for 32-bit refresh/unlock command write
                                                     words. 16-bit or 8-bit is NOT supported.                           */

/* ===============================================  WDT CSTS WDTIFLG [14..14]  =============================================== */
                                  /* WDT_CSTS_WDTIFLG                                                   */
#define WDT_CSTS_WDTIFLG_0                     0U      /* 0 : No interrupt occurred.                                         */
#define WDT_CSTS_WDTIFLG_1                     1U      /* 1 : An interrupt occurred.                                         */

/* ===============================================  WDT CSTS WINMEN [15..15]  ================================================ */
                                  /* WDT_CSTS_WINMEN                                                    */
#define WDT_CSTS_WINMEN_0                      0U      /* 0 : Window mode disabled.                                          */
#define WDT_CSTS_WINMEN_1                      1U      /* 1 : Window mode enabled.                                           */

/* ==========================================================  CNT  ========================================================== */
/* =========================================================  TOVAL  ========================================================= */
/* ==========================================================  WIN  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            CFGIO                                             ================ */
/* =========================================================================================================================== */

/* ========================================================  VERID  ======================================================== */
/* ==============================================  CFGIO VERID FEATURE [0..15]  =============================================== */
                                   /* CFGIO_VERID_FEATURE                                                 */
#define CFGIO_VERID_FEATURE_0000000000000000    0U      /* 0000000000000000 : Standard features implemented.                  */
#define CFGIO_VERID_FEATURE_0000000000000001    1U      /* 0000000000000001 : Supports state  logic and parallel modes.       */

/* =========================================================  PARA  ========================================================= */
/* =========================================================  CTRL  ========================================================== */
/* ==================================================  CFGIO CTRL CFGIOEN [0..0]  ================================================== */
                                  /* CFGIO_CTRL_CFGIOEN                                                       */
#define CFGIO_CTRL_CFGIOEN_0                         0U      /* 0 : CFGIO module is disabled.                                     */
#define CFGIO_CTRL_CFGIOEN_1                         1U      /* 1 : CFGIO module is enabled.                                      */

/* ================================================  CFGIO CTRL SWRSTEN [1..1]  ================================================= */
                                  /* CFGIO_CTRL_SWRSTEN                                                    */
#define CFGIO_CTRL_SWRSTEN_0                      0U      /* 0 : Software reset is disabled                                     */
#define CFGIO_CTRL_SWRSTEN_1                      1U      /* 1 : Software reset is enabled  all CFGIO registers except the
                                                     Control Register are reset.                                        */

/* ================================================  CFGIO CTRL FRACCEN [2..2]  ================================================= */
                                 /* CFGIO_CTRL_FRACCEN                                                    */
#define CFGIO_CTRL_FRACCEN_0                      0U      /* 0 : Configures for normal register accesses to CFGIO              */
#define CFGIO_CTRL_FRACCEN_1                      1U      /* 1 : Configures for fast register accesses to CFGIO                */

/* ================================================  CFGIO CTRL DBGEN [30..30]  ================================================= */
                                  /* CFGIO_CTRL_DBGEN                                                      */
#define CFGIO_CTRL_DBGEN_0                        0U      /* 0 : CFGIO is disabled in debug modes.                             */
#define CFGIO_CTRL_DBGEN_1                        1U      /* 1 : CFGIO is enabled in debug modes                               */

/* ===============================================  CFGIO CTRL DOZEEN [31..31]  ================================================ */
                                  /* CFGIO_CTRL_DOZEEN                                                    */
#define CFGIO_CTRL_DOZEEN_0                      0U      /* 0 : CFGIO enabled in Doze modes.                                  */
#define CFGIO_CTRL_DOZEEN_1                      1U      /* 1 : CFGIO disabled in Doze modes.                                 */

/* ========================================================  PIDATA  ======================================================== */
/* =========================================================  SSTS  ========================================================== */
/* ========================================================  SERRFLG  ======================================================== */
/* ========================================================  TMRSTS  ========================================================= */
/* ========================================================  SSTSIEN  ======================================================== */
/* ========================================================  SEFIEN  ========================================================= */
/* =======================================================  TMRSTSIEN  ======================================================= */
/* =======================================================  DMAREQEN  ======================================================== */
/* ========================================================  SCTRL  ========================================================= */
/* ================================================  CFGIO SCTRL SMCFG [0..2]  ================================================= */
                                   /* CFGIO_SCTRL_SMCFG                                                    */
#define CFGIO_SCTRL_SMCFG_0                      0U      /* 0 : Disabled.                                                      */
#define CFGIO_SCTRL_SMCFG_1                      1U      /* 1 : Receive mode. Captures the current Shifter content into
                                                     the SHIFTBUF on expiration of the Timer.                           */
#define CFGIO_SCTRL_SMCFG_10                     2U      /* 10 : Transmit mode. Load SHIFTBUF contents into the Shifter
                                                     on expiration of the Timer.                                        */
#define CFGIO_SCTRL_SMCFG_100                    4U      /* 100 : Match Store mode. Shifter data is compared to SHIFTBUF
                                                     content on expiration of the Timer.                                */
#define CFGIO_SCTRL_SMCFG_101                    5U      /* 101 : Match Continuous mode. Shifter data is continuously compared
                                                     to SHIFTBUF contents.                                              */

/* ===============================================  CFGIO SCTRL SPPOLCFG [7..7]  =============================================== */
                                  /* CFGIO_SCTRL_SPPOLCFG                                                 */
#define CFGIO_SCTRL_SPPOLCFG_0                   0U      /* 0 : Pin is active high                                             */
#define CFGIO_SCTRL_SPPOLCFG_1                   1U      /* 1 : Pin is active low                                              */

/* ==============================================  CFGIO SCTRL SUPSEL [8..10]  ============================================== */
                                /* CFGIO_SCTRL_SUPSEL                                                 */
#define CFGIO_SCTRL_SUPSEL_000                   0U      /* 0 : Select CFGIO_D0                                                  */
#define CFGIO_SCTRL_SUPSEL_001                   1U      /* 1 : Select CFGIO_D1                                                  */
#define CFGIO_SCTRL_SUPSEL_010                   2U      /* 2 : Select CFGIO_D2                                                  */
#define CFGIO_SCTRL_SUPSEL_011                   3U      /* 3 : Select CFGIO_D3                                                  */
#define CFGIO_SCTRL_SUPSEL_100                   4U      /* 0 : Select CFGIO_D4                                                  */
#define CFGIO_SCTRL_SUPSEL_101                   5U      /* 1 : Select CFGIO_D5                                                  */
#define CFGIO_SCTRL_SUPSEL_110                   6U      /* 2 : Select CFGIO_D6                                                  */
#define CFGIO_SCTRL_SUPSEL_111                   7U      /* 3 : Select CFGIO_D7                                                  */

/* ===============================================  CFGIO SCTRL SOPCFG [16..17]  =============================================== */
                                 /* CFGIO_SCTRL_SOPCFG                                                   */
#define CFGIO_SCTRL_SOPCFG_0                     0U      /* 0 : Shifter pin output disabled                                    */
#define CFGIO_SCTRL_SOPCFG_1                     1U      /* 1 : Shifter pin open drain or bidirectional output enable          */
#define CFGIO_SCTRL_SOPCFG_10                    2U      /* 10 : Shifter pin bidirectional output data                         */
#define CFGIO_SCTRL_SOPCFG_11                    3U      /* 11 : Shifter pin output                                            */

/* ==============================================  CFGIO SCTRL SCLKLCFG [23..23]  ============================================== */
                                /* CFGIO_SCTRL_SCLKLCFG                                                 */
#define CFGIO_SCTRL_SCLKLCFG_0                   0U      /* 0 : Shift on posedge of Shift clock                                */
#define CFGIO_SCTRL_SCLKLCFG_1                   1U      /* 1 : Shift on negedge of Shift clock                                */

/* ==============================================  CFGIO SCTRL TMRSEL [24..25]  ============================================== */
                                /* CFGIO_SCTRL_TMRSEL                                                 */
#define CFGIO_SCTRL_TMRSEL_00                   0U      /* 0 : Select TIMER0                                                  */
#define CFGIO_SCTRL_TMRSEL_01                   1U      /* 1 : Select TIMER1                                                  */
#define CFGIO_SCTRL_TMRSEL_10                   2U      /* 2 : Select TIMER2                                                  */
#define CFGIO_SCTRL_TMRSEL_11                   3U      /* 3 : Select TIMER3                                                  */

/* =========================================================  SCFG  ========================================================= */
/* ===============================================  CFGIO SCFG SSTAFSEL [0..1]  ================================================ */
                                 /* CFGIO_SCFG_SSTAFSEL                                                  */
#define CFGIO_SCFG_SSTAFSEL_0                    0U      /* 0 : Start bit disabled for transmitter/receiver/match store
                                                     transmitter loads data on enable                                   */
#define CFGIO_SCFG_SSTAFSEL_1                    1U      /* 1 : Start bit disabled for transmitter/receiver/match store
                                                     transmitter loads data on first shift                              */
#define CFGIO_SCFG_SSTAFSEL_10                   2U      /* 10 : Transmitter outputs start bit value 0 before loading data
                                                     on first shift  receiver/match store sets error flag if
                                                     start bit is not 0                                                 */
#define CFGIO_SCFG_SSTAFSEL_11                   3U      /* 11 : Transmitter outputs start bit value 1 before loading data
                                                     on first shift  receiver/match store sets error flag if
                                                     start bit is not 1                                                 */

/* ===============================================  CFGIO SCFG SSTOPFSEL [4..5]  =============================================== */
                                  /* CFGIO_SCFG_SSTOPFSEL                                                 */
#define CFGIO_SCFG_SSTOPFSEL_0                   0U      /* 0 : Stop bit disabled for transmitter/receiver/match store         */
#define CFGIO_SCFG_SSTOPFSEL_1                   1U      /* 1 : Reserved for transmitter/receiver/match store                  */
#define CFGIO_SCFG_SSTOPFSEL_10                  2U      /* 10 : Transmitter outputs stop bit value 0 on store  receiver/match
                                                     store sets error flag if stop bit is not 0                         */
#define CFGIO_SCFG_SSTOPFSEL_11                  3U      /* 11 : Transmitter outputs stop bit value 1 on store  receiver/match
                                                     store sets error flag if stop bit is not 1                         */

/* ================================================  CFGIO SCFG ISRCSEL [8..8]  ================================================ */
                                  /* CFGIO_SCFG_ISRCSEL                                                   */
#define CFGIO_SCFG_ISRCSEL_0                     0U      /* 0 : Pin                                                            */
#define CFGIO_SCFG_ISRCSEL_1                     1U      /* 1 : Shifter N+1 Output                                             */

/* =========================================================  SBUF  ========================================================= */
/* =======================================================  SBUFBITSWA  ======================================================= */
/* =======================================================  SBUFBYTSWA  ======================================================= */
/* ========================================================  SBUFBSWA  ======================================================== */
/* ========================================================  TMRCTRL  ======================================================== */
/* ===============================================  CFGIO TMRCTRL TMRMCFG [0..1]  =============================================== */
                                  /* CFGIO_TMRCTRL_TMRMCFG                                                 */
#define CFGIO_TMRCTRL_TMRMCFG_0                   0U      /* 0 : Timer Disabled.                                                */
#define CFGIO_TMRCTRL_TMRMCFG_1                   1U      /* 1 : Dual 8-bit counters baud/bit mode.                             */
#define CFGIO_TMRCTRL_TMRMCFG_10                  2U      /* 10 : Dual 8-bit counters PWM mode.                                 */
#define CFGIO_TMRCTRL_TMRMCFG_11                  3U      /* 11 : Single 16-bit counter mode.                                   */

/* ==============================================  CFGIO TMRCTRL TMRPPOLCFG [7..7]  =============================================== */
                                   /* CFGIO_TMRCTRL_TMRPPOLCFG                                                */
#define CFGIO_TMRCTRL_TMRPPOLCFG_0                  0U      /* 0 : Pin is active high                                             */
#define CFGIO_TMRCTRL_TMRPPOLCFG_1                  1U      /* 1 : Pin is active low                                              */

/* ==============================================  CFGIO TMRCTRL TMROPCFG [16..17]  =============================================== */
                                  /* CFGIO_TMRCTRL_TMROPCFG                                                  */
#define CFGIO_TMRCTRL_TMROPCFG_0                    0U      /* 0 : Timer pin output disabled                                      */
#define CFGIO_TMRCTRL_TMROPCFG_1                    1U      /* 1 : Timer pin open drain or bidirectional output enable            */
#define CFGIO_TMRCTRL_TMROPCFG_10                   2U      /* 10 : Timer pin bidirectional output data                           */
#define CFGIO_TMRCTRL_TMROPCFG_11                   3U      /* 11 : Timer pin output                                              */

/* =============================================  CFGIO TMRCTRL TRGSSEL [22..22]  ============================================= */
                                   /* CFGIO_TMRCTRL_TRGSSEL                                               */
#define CFGIO_TMRCTRL_TRGSSEL_0                 0U      /* 0 : External trigger selected                                      */
#define CFGIO_TMRCTRL_TRGSSEL_1                 1U      /* 1 : Internal trigger selected                                      */

/* =============================================  CFGIO TMRCTRL TRGPOLCFG [23..23]  ============================================= */
                                 /* CFGIO_TMRCTRL_TRGPOLCFG                                               */
#define CFGIO_TMRCTRL_TRGPOLCFG_0                 0U      /* 0 : Trigger active high                                            */
#define CFGIO_TMRCTRL_TRGPOLCFG_1                 1U      /* 1 : Trigger active low                                             */

/* ========================================================  TMRCFG  ======================================================== */
/* ==============================================  CFGIO TMRCFG TMRSTAEN [1..1]  =============================================== */
                                 /* CFGIO_TMRCFG_TMRSTAEN                                                */
#define CFGIO_TMRCFG_TMRSTAEN_0                  0U      /* 0 : Start bit disabled                                             */
#define CFGIO_TMRCFG_TMRSTAEN_1                  1U      /* 1 : Start bit enabled                                              */

/* =============================================  CFGIO TMRCFG TMRSTOPFSEL [4..5]  ============================================= */
                                   /* CFGIO_TMRCFG_TMRSTOPFSEL                                             */
#define CFGIO_TMRCFG_TMRSTOPFSEL_0               0U      /* 0 : Stop bit disabled                                              */
#define CFGIO_TMRCFG_TMRSTOPFSEL_1               1U      /* 1 : Stop bit is enabled on timer compare                           */
#define CFGIO_TMRCFG_TMRSTOPFSEL_10              2U      /* 10 : Stop bit is enabled on timer disable                          */
#define CFGIO_TMRCFG_TMRSTOPFSEL_11              3U      /* 11 : Stop bit is enabled on timer compare and timer disable        */

/* ==============================================  CFGIO TMRCFG TMRENCFG [8..10]  ============================================== */
                                  /* CFGIO_TMRCFG_TMRENCFG                                                */
#define CFGIO_TMRCFG_TMRENCFG_0                  0U      /* 0 : Timer always enabled                                           */
#define CFGIO_TMRCFG_TMRENCFG_1                  1U      /* 1 : Timer enabled on Timer N-1 enable                              */
#define CFGIO_TMRCFG_TMRENCFG_10                 2U      /* 10 : Timer enabled on Trigger high                                 */
#define CFGIO_TMRCFG_TMRENCFG_11                 3U      /* 11 : Timer enabled on Trigger high and Pin high                    */
#define CFGIO_TMRCFG_TMRENCFG_100                4U      /* 100 : Timer enabled on Pin rising edge                             */
#define CFGIO_TMRCFG_TMRENCFG_101                5U      /* 101 : Timer enabled on Pin rising edge and Trigger high            */
#define CFGIO_TMRCFG_TMRENCFG_110                6U      /* 110 : Timer enabled on Trigger rising edge                         */
#define CFGIO_TMRCFG_TMRENCFG_111                7U      /* 111 : Timer enabled on Trigger rising or falling edge              */

/* =============================================  CFGIO TMRCFG TMRDISCFG [12..14]  ============================================= */
                                   /* CFGIO_TMRCFG_TMRDISCFG                                               */
#define CFGIO_TMRCFG_TMRDISCFG_0                 0U      /* 0 : Timer never disabled                                           */
#define CFGIO_TMRCFG_TMRDISCFG_1                 1U      /* 1 : Timer disabled on Timer N-1 disable                            */
#define CFGIO_TMRCFG_TMRDISCFG_10                2U      /* 10 : Timer disabled on Timer compare                               */
#define CFGIO_TMRCFG_TMRDISCFG_11                3U      /* 11 : Timer disabled on Timer compare and Trigger Low               */
#define CFGIO_TMRCFG_TMRDISCFG_100               4U      /* 100 : Timer disabled on Pin rising or falling edge                 */
#define CFGIO_TMRCFG_TMRDISCFG_101               5U      /* 101 : Timer disabled on Pin rising or falling edge provided
                                                     Trigger is high                                                    */
#define CFGIO_TMRCFG_TMRDISCFG_110               6U      /* 110 : Timer disabled on Trigger falling edge                       */

/* =============================================  CFGIO TMRCFG TMRRSTCFG [16..18]  ============================================= */
                                   /* CFGIO_TMRCFG_TMRRSTCFG                                               */
#define CFGIO_TMRCFG_TMRRSTCFG_0                 0U      /* 0 : Timer never reset                                              */
#define CFGIO_TMRCFG_TMRRSTCFG_10                2U      /* 10 : Timer reset on Timer Pin equal to Timer Output                */
#define CFGIO_TMRCFG_TMRRSTCFG_11                3U      /* 11 : Timer reset on Timer Trigger equal to Timer Output            */
#define CFGIO_TMRCFG_TMRRSTCFG_100               4U      /* 100 : Timer reset on Timer Pin rising edge                         */
#define CFGIO_TMRCFG_TMRRSTCFG_110               6U      /* 110 : Timer reset on Trigger rising edge                           */
#define CFGIO_TMRCFG_TMRRSTCFG_111               7U      /* 111 : Timer reset on Trigger rising or falling edge                */

/* ==============================================  CFGIO TMRCFG TMRDCFG [20..21]  ============================================== */
                                  /* CFGIO_TMRCFG_TMRDCFG                                                 */
#define CFGIO_TMRCFG_TMRDCFG_0                   0U      /* 0 : Decrement counter on CFGIO clock  Shift clock equals Timer
                                                     output.                                                            */
#define CFGIO_TMRCFG_TMRDCFG_1                   1U      /* 1 : Decrement counter on Trigger input (both edges)  Shift clock
                                                     equals Timer output.                                               */
#define CFGIO_TMRCFG_TMRDCFG_10                  2U      /* 10 : Decrement counter on Pin input (both edges)  Shift clock
                                                     equals Pin input.                                                  */
#define CFGIO_TMRCFG_TMRDCFG_11                  3U      /* 11 : Decrement counter on Trigger input (both edges)  Shift
                                                     clock equals Trigger input.                                        */

/* ==============================================  CFGIO TMRCFG TMROCFG [24..25]  ============================================== */
                                  /* CFGIO_TMRCFG_TMROCFG                                                 */
#define CFGIO_TMRCFG_TMROCFG_0                   0U      /* 0 : Timer output is logic one when enabled and is not affected
                                                     by timer reset                                                     */
#define CFGIO_TMRCFG_TMROCFG_1                   1U      /* 1 : Timer output is logic zero when enabled and is not affected
                                                     by timer reset                                                     */
#define CFGIO_TMRCFG_TMROCFG_10                  2U      /* 10 : Timer output is logic one when enabled and on timer reset     */
#define CFGIO_TMRCFG_TMROCFG_11                  3U      /* 11 : Timer output is logic zero when enabled and on timer reset    */

/* =======================================================  TMRCOMP  ======================================================== */


/* =========================================================================================================================== */
/* ================                                           EWDT                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
/* ================================================  EWDT CTRL EWDTEN [0..0]  ================================================ */
                                  /* EWDT_CTRL_EWDTEN                                                          */
#define  EWDT_CTRL_EWDTEN_0                  0U     /* 0 : Disable External Watchdog Timer.                                      */
#define  EWDT_CTRL_EWDTEN_1                  1U     /* 1 : Enable External Watchdog Timer.                                       */


/* ===============================================  EWDT CTRL INSIGSEL [1..1]  =============================================== */
                                  /* EWDT_CTRL_INSIGSEL                                                        */
#define  EWDT_CTRL_INSIGSEL_0                0U     /* 0 : EWM_in's Assertion State is logic zero.                               */
#define  EWDT_CTRL_INSIGSEL_1                1U     /* 1 : EWM_in's Assertion State is logic one.                                */


/* ================================================  EWDT CTRL INPEN [2..2]  ================================================= */
                                  /* EWDT_CTRL_INPEN                                                           */
#define  EWDT_CTRL_INPEN_0                   0U     /* 0 : Disable the EWM_in port.                                              */
#define  EWDT_CTRL_INPEN_1                   1U     /* 1 : Enables the EWM_in port.                                              */


/* ===============================================  EWDT CTRL INTREQEN [3..3]  =============================================== */
                                  /* EWDT_CTRL_INTREQEN                                                        */
#define  EWDT_CTRL_INTREQEN_0                0U     /* 0 : Disable External Watchdog Timer Interrupt.                            */
#define  EWDT_CTRL_INTREQEN_1                1U     /* 1 : Enable External Watchdog Timer Interrupt.                             */

/* ==========================================================  SEQ  ========================================================== */
/* =========================================================  COMPL  ========================================================= */
/* =========================================================  COMPH  ========================================================= */
/* ========================================================  CLKPSC  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            TMC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  DMACHM0CFG  ======================================================== */
/* ===============================================  TMC DMACHM0CFG LOCK [31..31]  =============================================== */
                                  /* TMC_DMAMUX0CFG_LOCK                                                   */
#define TMC_DMACHM0CFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_DMACHM0CFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  EXTOUT0CFG  ======================================================== */
/* ===============================================  TMC EXTOUT0CFG LOCK [31..31]  =============================================== */
                                  /* TMC_EXTOUT0CFG_LOCK                                                   */
#define TMC_EXTOUT0CFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_EXTOUT0CFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  EXTOUT1CFG  ======================================================== */
/* ===============================================  TMC EXTOUT1CFG LOCK [31..31]  =============================================== */
                                   /* TMC_EXTOUT1CFG_LOCK                                                   */
#define TMC_EXTOUT1CFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_EXTOUT1CFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  ADC0CFG  ========================================================== */
/* ================================================  TMC ADC0CFG LOCK [31..31]  ================================================= */
                                  /* TMC_ADC0CFG_LOCK                                                      */
#define TMC_ADC0CFG_LOCK_0                        0U      /* 0 : Register can be written.                                       */
#define TMC_ADC0CFG_LOCK_1                        1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  ADC1CFG  ========================================================== */
/* ================================================  TMC ADC1CFG LOCK [31..31]  ================================================= */
                                 /* TMC_ADC1CFG_LOCK                                                      */
#define TMC_ADC1CFG_LOCK_0                        0U      /* 0 : Register can be written.                                       */
#define TMC_ADC1CFG_LOCK_1                        1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  COMPCFG  ========================================================= */
/* ================================================  TMC COMPCFG LOCK [31..31]  ================================================ */
                                  /* TMC_COMPCFG_LOCK                                                     */
#define TMC_COMPCFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_COMPCFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR0CFG  ========================================================= */
/* ================================================  TMC CFGTMR0CFG LOCK [31..31]  ================================================ */
                                   /* TMC_CFGTMR0CFG_LOCK                                                     */
#define TMC_CFGTMR0CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR0CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR1CFG  ========================================================= */
/* ================================================  TMC CFGTMR1CFG LOCK [31..31]  ================================================ */
                                 /* TMC_CFGTMR1CFG_LOCK                                                     */
#define TMC_CFGTMR1CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR1CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR2CFG  ========================================================= */
/* ================================================  TMC CFGTMR2CFG LOCK [31..31]  ================================================ */
                                   /* TMC_CFGTMR2CFG_LOCK                                                     */
#define TMC_CFGTMR2CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR2CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR3CFG  ========================================================= */
/* ================================================  TMC CFGTMR3CFG LOCK [31..31]  ================================================ */
                                  /* TMC_CFGTMR3CFG_LOCK                                                     */
#define TMC_CFGTMR3CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR3CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  PRD0CFG  ========================================================== */
/* ================================================  TMC PRD0CFG LOCK [31..31]  ================================================= */
                                  /* TMC_PRD0CFG_LOCK                                                      */
#define TMC_PRD0CFG_LOCK_0                        0U      /* 0 : Register can be written.                                       */
#define TMC_PRD0CFG_LOCK_1                        1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  PRD1CFG  ========================================================== */
/* ================================================  TMC PRD1CFG LOCK [31..31]  ================================================= */
                                  /* TMC_PRD1CFG_LOCK                                                      */
#define TMC_PRD1CFG_LOCK_0                        0U      /* 0 : Register can be written.                                       */
#define TMC_PRD1CFG_LOCK_1                        1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ==========================================================  CFGIOCFG  =========================================================== */
/* =================================================  TMC CFGIOCFG LOCK [31..31]  ================================================== */
                                  /* TMC_CFGIOCFG_LOCK                                                        */
#define TMC_CFGIOCFG_LOCK_0                          0U      /* 0 : Register can be written.                                       */
#define TMC_CFGIOCFG_LOCK_1                          1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPITMRCFG  ======================================================== */
/* ===============================================  TMC LPITMRCFG LOCK [31..31]  =============================================== */
                                   /* TMC_LPITMRCFG_LOCK                                                   */
#define TMC_LPITMRCFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_LPITMRCFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPUART0CFG  ======================================================== */
/* ===============================================  TMC LPUART0CFG LOCK [31..31]  =============================================== */
                                  /* TMC_LPUART0CFG_LOCK                                                   */
#define TMC_LPUART0CFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_LPUART0CFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPUART1CFG  ======================================================== */
/* ===============================================  TMC LPUART1CFG LOCK [31..31]  =============================================== */
                                  /* TMC_LPUART1CFG_LOCK                                                   */
#define TMC_LPUART1CFG_LOCK_0                     0U      /* 0 : Register can be written.                                       */
#define TMC_LPUART1CFG_LOCK_1                     1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPI2CCFG  ========================================================= */
/* ===============================================  TMC LPI2CCFG LOCK [31..31]  ================================================ */
                                   /* TMC_LPI2CCFG_LOCK                                                    */
#define TMC_LPI2CCFG_LOCK_0                      0U      /* 0 : Register can be written.                                       */
#define TMC_LPI2CCFG_LOCK_1                      1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPSPI0CFG  ========================================================= */
/* ===============================================  TMC LPSPI0CFG LOCK [31..31]  ================================================ */
                                   /* TMC_LPSPI0CFG_LOCK                                                    */
#define TMC_LPSPI0CFG_LOCK_0                      0U      /* 0 : Register can be written.                                       */
#define TMC_LPSPI0CFG_LOCK_1                      1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPSPI1CFG  ========================================================= */
/* ===============================================  TMC LPSPI1CFG LOCK [31..31]  ================================================ */
                                  /* TMC_LPSPI1CFG_LOCK                                                    */
#define TMC_LPSPI1CFG_LOCK_0                      0U      /* 0 : Register can be written.                                       */
#define TMC_LPSPI1CFG_LOCK_1                      1U      /* 1 : Register cannot be written until the next system Reset.        */

/* ========================================================  LPTMRCFG  ========================================================= */
/* ===============================================  TMC LPTMRCFG LOCK [31..31]  ================================================ */
                                   /* TMC_LPTMRCFG_LOCK                                                    */
#define TMC_LPTMRCFG_LOCK_0                      0U      /* 0 : Register can be written.                                       */
#define TMC_LPTMRCFG_LOCK_1                      1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR4CFG  ========================================================= */
/* ================================================  TMC CFGTMR4CFG LOCK [31..31]  ================================================ */
                                  /* TMC_CFGTMR4CFG_LOCK                                                     */
#define TMC_CFGTMR4CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR4CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */

/* =========================================================  CFGTMR5CFG  ========================================================= */
/* ================================================  TMC CFGTMR5CFG LOCK [31..31]  ================================================ */
                                  /* TMC_CFGTMR5CFG_LOCK                                                     */
#define TMC_CFGTMR5CFG_LOCK_0                       0U      /* 0 : Register can be written.                                       */
#define TMC_CFGTMR5CFG_LOCK_1                       1U      /* 1 : Register cannot be written until the next system Reset.        */


/* =========================================================================================================================== */
/* ================                                            SCG                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* =========================================================  PARA  ========================================================== */
/* ========================================================  CLKCFG  ========================================================= */
/* =============================================  SCG CLKCFG SCLKDIVRCFG [0..3]  ============================================= */
                                  /* SCG_CLKCFG_SCLKDIVRCFG                                                    */
#define SCG_CLKCFG_SCLKDIVRCFG_0000         0U    /* 0000 : Divide-by-1                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0001         1U    /* 0001 : Divide-by-2                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0010         2U    /* 0010 : Divide-by-3                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0011         3U    /* 0011 : Divide-by-4                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0100         4U    /* 0100 : Divide-by-5                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0101         5U    /* 0101 : Divide-by-6                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0110         6U    /* 0110 : Divide-by-7                                                        */
#define SCG_CLKCFG_SCLKDIVRCFG_0111         7U    /* 0111 : Divide-by-8                                                        */


/* =============================================  SCG CLKCFG BCLKDIVRCFG [4..7]  ============================================= */
                                  /* SCG_CLKCFG_BCLKDIVRCFG                                                    */
#define SCG_CLKCFG_BCLKDIVRCFG_0000         0U    /* 0000 : Divide-by-1                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0001         1U    /* 0001 : Divide-by-2                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0010         2U    /* 0010 : Divide-by-3                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0011         3U    /* 0011 : Divide-by-4                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0100         4U    /* 0100 : Divide-by-5                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0101         5U    /* 0101 : Divide-by-6                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0110         6U    /* 0110 : Divide-by-7                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_0111         7U    /* 0111 : Divide-by-8                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_1000         8U    /* 1000 : Divide-by-9                                                        */
#define SCG_CLKCFG_BCLKDIVRCFG_1001         9U    /* 1001 : Divide-by-10                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1010         10U   /* 1010 : Divide-by-11                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1011         11U   /* 1011 : Divide-by-12                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1100         12U   /* 1100 : Divide-by-13                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1101         13U   /* 1101 : Divide-by-14                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1110         14U   /* 1110 : Divide-by-15                                                       */
#define SCG_CLKCFG_BCLKDIVRCFG_1111         15U   /* 1111 : Divide-by-16                                                       */


/* ============================================  SCG CLKCFG CCLKDIVRCFG [16..19]  ============================================ */
                                  /* SCG_CLKCFG_CCLKDIVRCFG                                                    */
#define SCG_CLKCFG_CCLKDIVRCFG_0000         0U    /* 0000 : Divide-by-1                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0001         1U    /* 0001 : Divide-by-2                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0010         2U    /* 0010 : Divide-by-3                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0011         3U    /* 0011 : Divide-by-4                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0100         4U    /* 0100 : Divide-by-5                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0101         5U    /* 0101 : Divide-by-6                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0110         6U    /* 0110 : Divide-by-7                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_0111         7U    /* 0111 : Divide-by-8                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_1000         8U    /* 1000 : Divide-by-9                                                        */
#define SCG_CLKCFG_CCLKDIVRCFG_1001         9U    /* 1001 : Divide-by-10                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1010         10U   /* 1010 : Divide-by-11                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1011         11U   /* 1011 : Divide-by-12                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1100         12U   /* 1100 : Divide-by-13                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1101         13U   /* 1101 : Divide-by-14                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1110         14U   /* 1110 : Divide-by-15                                                       */
#define SCG_CLKCFG_CCLKDIVRCFG_1111         15U   /* 1111 : Divide-by-16                                                       */


/* ============================================  SCG CLKCFG SYSCLKSSEL [24..27]  ============================================= */
                                  /* SCG_CLKCFG_SYSCLKSSEL                                                     */
#define SCG_CLKCFG_SYSCLKSSEL_0001          1U    /* 0001 : System OSC (SYSOSC_CLK)                                              */
#define SCG_CLKCFG_SYSCLKSSEL_0010          2U    /* 0010 : Low speed internal oscillator (LSI_CLK)                                                */
#define SCG_CLKCFG_SYSCLKSSEL_0011          3U    /* 0011 : High speed internal oscillator (HSI_CLK)                                                */
#define SCG_CLKCFG_SYSCLKSSEL_0110          6U    /* 0110 : System PLL (SYSPLL_CLK)                                              */


/* ======================================================  RUNCLKCTRL  ======================================================= */
/* ===========================================  SCG RUNCLKCTRL SCLKDIVRCFG [0..3]  =========================================== */
                                  /* SCG_RUNCLKCTRL_SCLKDIVRCFG                                                */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0000     0U    /* 0000 : Divide-by-1                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0001     1U    /* 0001 : Divide-by-2                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0010     2U    /* 0010 : Divide-by-3                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0011     3U    /* 0011 : Divide-by-4                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0100     4U    /* 0100 : Divide-by-5                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0101     5U    /* 0101 : Divide-by-6                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0110     6U    /* 0110 : Divide-by-7                                                        */
#define SCG_RUNCLKCTRL_SCLKDIVRCFG_0111     7U    /* 0111 : Divide-by-8                                                        */


/* ===========================================  SCG RUNCLKCTRL BCLKDIVRCFG [4..7]  =========================================== */
                                  /* SCG_RUNCLKCTRL_BCLKDIVRCFG                                                */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0000     0U    /* 0000 : Divide-by-1                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0001     1U    /* 0001 : Divide-by-2                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0010     2U    /* 0010 : Divide-by-3                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0011     3U    /* 0011 : Divide-by-4                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0100     4U    /* 0100 : Divide-by-5                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0101     5U    /* 0101 : Divide-by-6                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0110     6U    /* 0110 : Divide-by-7                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_0111     7U    /* 0111 : Divide-by-8                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1000     8U    /* 1000 : Divide-by-9                                                        */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1001     9U    /* 1001 : Divide-by-10                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1010     10U   /* 1010 : Divide-by-11                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1011     11U   /* 1011 : Divide-by-12                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1100     12U   /* 1100 : Divide-by-13                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1101     13U   /* 1101 : Divide-by-14                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1110     14U   /* 1110 : Divide-by-15                                                       */
#define SCG_RUNCLKCTRL_BCLKDIVRCFG_1111     15U   /* 1111 : Divide-by-16                                                       */


/* ==========================================  SCG RUNCLKCTRL CCLKDIVRCFG [16..19]  ========================================== */
                                  /* SCG_RUNCLKCTRL_CCLKDIVRCFG                                                */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0000     0U    /* 0000 : Divide-by-1                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0001     1U    /* 0001 : Divide-by-2                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0010     2U    /* 0010 : Divide-by-3                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0011     3U    /* 0011 : Divide-by-4                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0100     4U    /* 0100 : Divide-by-5                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0101     5U    /* 0101 : Divide-by-6                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0110     6U    /* 0110 : Divide-by-7                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_0111     7U    /* 0111 : Divide-by-8                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1000     8U    /* 1000 : Divide-by-9                                                        */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1001     9U    /* 1001 : Divide-by-10                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1010     10U   /* 1010 : Divide-by-11                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1011     11U   /* 1011 : Divide-by-12                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1100     12U   /* 1100 : Divide-by-13                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1101     13U   /* 1101 : Divide-by-14                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1110     14U   /* 1110 : Divide-by-15                                                       */
#define SCG_RUNCLKCTRL_CCLKDIVRCFG_1111     15U   /* 1111 : Divide-by-16                                                       */


/* ==========================================  SCG RUNCLKCTRL SYSCLKSSEL [24..27]  =========================================== */
                                  /* SCG_RUNCLKCTRL_SYSCLKSSEL                                                 */
#define SCG_RUNCLKCTRL_SYSCLKSSEL_0001      1U    /* 0001 : System OSC (SYSOSC_CLK)                                              */
#define SCG_RUNCLKCTRL_SYSCLKSSEL_0010      2U    /* 0010 : Low speed internal oscillator (LSI_CLK)                                                */
#define SCG_RUNCLKCTRL_SYSCLKSSEL_0011      3U    /* 0011 : High speed internal oscillator (HSI_CLK)                                                */
#define SCG_RUNCLKCTRL_SYSCLKSSEL_0110      6U    /* 0110 : System PLL (SYSPLL_CLK)                                              */


/* ======================================================  VLPRCLKCTRL  ====================================================== */
/* ==========================================  SCG VLPRCLKCTRL SCLKDIVRCFG [0..3]  =========================================== */
                                  /* SCG_VLPRCLKCTRL_SCLKDIVRCFG                                               */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0000    0U    /* 0000 : Divide-by-1                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0001    1U    /* 0001 : Divide-by-2                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0010    2U    /* 0010 : Divide-by-3                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0011    3U    /* 0011 : Divide-by-4                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0100    4U    /* 0100 : Divide-by-5                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0101    5U    /* 0101 : Divide-by-6                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0110    6U    /* 0110 : Divide-by-7                                                        */
#define SCG_VLPRCLKCTRL_SCLKDIVRCFG_0111    7U    /* 0111 : Divide-by-8                                                        */


/* ==========================================  SCG VLPRCLKCTRL BCLKDIVRCFG [4..7]  =========================================== */
                                  /* SCG_VLPRCLKCTRL_BCLKDIVRCFG                                               */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0000    0U    /* 0000 : Divide-by-1                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0001    1U    /* 0001 : Divide-by-2                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0010    2U    /* 0010 : Divide-by-3                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0011    3U    /* 0011 : Divide-by-4                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0100    4U    /* 0100 : Divide-by-5                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0101    5U    /* 0101 : Divide-by-6                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0110    6U    /* 0110 : Divide-by-7                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_0111    7U    /* 0111 : Divide-by-8                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1000    8U    /* 1000 : Divide-by-9                                                        */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1001    9U    /* 1001 : Divide-by-10                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1010    10U   /* 1010 : Divide-by-11                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1011    11U   /* 1011 : Divide-by-12                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1100    12U   /* 1100 : Divide-by-13                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1101    13U   /* 1101 : Divide-by-14                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1110    14U   /* 1110 : Divide-by-15                                                       */
#define SCG_VLPRCLKCTRL_BCLKDIVRCFG_1111    15U   /* 1111 : Divide-by-16                                                       */


/* =========================================  SCG VLPRCLKCTRL CCLKDIVRCFG [16..19]  ========================================== */
                                  /* SCG_VLPRCLKCTRL_CCLKDIVRCFG                                               */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0000    0U    /* 0000 : Divide-by-1                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0001    1U    /* 0001 : Divide-by-2                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0010    2U    /* 0010 : Divide-by-3                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0011    3U    /* 0011 : Divide-by-4                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0100    4U    /* 0100 : Divide-by-5                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0101    5U    /* 0101 : Divide-by-6                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0110    6U    /* 0110 : Divide-by-7                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_0111    7U    /* 0111 : Divide-by-8                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1000    8U    /* 1000 : Divide-by-9                                                        */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1001    9U    /* 1001 : Divide-by-10                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1010    10U   /* 1010 : Divide-by-11                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1011    11U   /* 1011 : Divide-by-12                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1100    12U   /* 1100 : Divide-by-13                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1101    13U   /* 1101 : Divide-by-14                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1110    14U   /* 1110 : Divide-by-15                                                       */
#define SCG_VLPRCLKCTRL_CCLKDIVRCFG_1111    15U   /* 1111 : Divide-by-16                                                       */


/* ==========================================  SCG VLPRCLKCTRL SYSCLKSSEL [24..27]  ========================================== */
                                  /* SCG_VLPRCLKCTRL_SYSCLKSSEL                                                */
#define SCG_VLPRCLKCTRL_SYSCLKSSEL_0010     2U    /* 0010 : Low speed internal oscillator (LSI_CLK)                                                */


/* =====================================================  HSRUNCLKCTRL  ====================================================== */
/* ==========================================  SCG HSRUNCLKCTRL SCLKDIVRCFG [0..3]  ========================================== */
                                  /* SCG_HSRUNCLKCTRL_SCLKDIVRCFG                                              */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0000   0U    /* 0000 : Divide-by-1                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0001   1U    /* 0001 : Divide-by-2                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0010   2U    /* 0010 : Divide-by-3                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0011   3U    /* 0011 : Divide-by-4                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0100   4U    /* 0100 : Divide-by-5                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0101   5U    /* 0101 : Divide-by-6                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0110   6U    /* 0110 : Divide-by-7                                                        */
#define SCG_HSRUNCLKCTRL_SCLKDIVRCFG_0111   7U    /* 0111 : Divide-by-8                                                        */


/* ==========================================  SCG HSRUNCLKCTRL BCLKDIVRCFG [4..7]  ========================================== */
                                  /* SCG_HSRUNCLKCTRL_BCLKDIVRCFG                                              */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0000   0U    /* 0000 : Divide-by-1                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0001   1U    /* 0001 : Divide-by-2                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0010   2U    /* 0010 : Divide-by-3                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0011   3U    /* 0011 : Divide-by-4                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0100   4U    /* 0100 : Divide-by-5                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0101   5U    /* 0101 : Divide-by-6                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0110   6U    /* 0110 : Divide-by-7                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_0111   7U    /* 0111 : Divide-by-8                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1000   8U    /* 1000 : Divide-by-9                                                        */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1001   9U    /* 1001 : Divide-by-10                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1010   10U   /* 1010 : Divide-by-11                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1011   11U   /* 1011 : Divide-by-12                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1100   12U   /* 1100 : Divide-by-13                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1101   13U   /* 1101 : Divide-by-14                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1110   14U   /* 1110 : Divide-by-15                                                       */
#define SCG_HSRUNCLKCTRL_BCLKDIVRCFG_1111   15U   /* 1111 : Divide-by-16                                                       */


/* =========================================  SCG HSRUNCLKCTRL CCLKDIVRCFG [16..19]  ========================================= */
                                  /* SCG_HSRUNCLKCTRL_CCLKDIVRCFG                                              */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0000   0U    /* 0000 : Divide-by-1                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0001   1U    /* 0001 : Divide-by-2                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0010   2U    /* 0010 : Divide-by-3                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0011   3U    /* 0011 : Divide-by-4                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0100   4U    /* 0100 : Divide-by-5                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0101   5U    /* 0101 : Divide-by-6                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0110   6U    /* 0110 : Divide-by-7                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_0111   7U    /* 0111 : Divide-by-8                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1000   8U    /* 1000 : Divide-by-9                                                        */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1001   9U    /* 1001 : Divide-by-10                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1010   10U   /* 1010 : Divide-by-11                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1011   11U   /* 1011 : Divide-by-12                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1100   12U   /* 1100 : Divide-by-13                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1101   13U   /* 1101 : Divide-by-14                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1110   14U   /* 1110 : Divide-by-15                                                       */
#define SCG_HSRUNCLKCTRL_CCLKDIVRCFG_1111   15U   /* 1111 : Divide-by-16                                                       */


/* =========================================  SCG HSRUNCLKCTRL SYSCLKSSEL [24..27]  ========================================== */
                                  /* SCG_HSRUNCLKCTRL_SYSCLKSSEL                                               */
#define SCG_HSRUNCLKCTRL_SYSCLKSSEL_0011    3U    /* 0011 : High speed internal oscillator (HSI_CLK)                                                */
#define SCG_HSRUNCLKCTRL_SYSCLKSSEL_0110    6U    /* 0110 : System PLL (SYSPLL_CLK)                                              */


/* ======================================================  SYSCLKOSEL  ======================================================= */
/* ==========================================  SCG SYSCLKOSEL SYSCLKOSEL [24..27]  =========================================== */
                                  /* SCG_SYSCLKOSEL_SYSCLKOSEL                                                 */
#define SCG_SYSCLKOSEL_SYSCLKOSEL_0000      0U    /* 0000 : SCG SLOW Clock                                                     */
#define SCG_SYSCLKOSEL_SYSCLKOSEL_0001      1U    /* 0001 : System OSC (SYSOSC_CLK)                                              */
#define SCG_SYSCLKOSEL_SYSCLKOSEL_0010      2U    /* 0010 : Low speed internal oscillator (LSI_CLK)                                                */
#define SCG_SYSCLKOSEL_SYSCLKOSEL_0011      3U    /* 0011 : High speed internal oscillator (HSI_CLK)                                                */
#define SCG_SYSCLKOSEL_SYSCLKOSEL_0110      6U    /* 0110 : System PLL (SYSPLL_CLK)                                              */


/* ======================================================  SYSOSCCSTS  ======================================================= */
/* ============================================  SCG SYSOSCCSTS SYSOSCEN [0..0]  ============================================= */
                                  /* SCG_SYSOSCCSTS_SYSOSCEN                                                   */
#define SCG_SYSOSCCSTS_SYSOSCEN_0           0U    /* 0 : System OSC is disabled                                                */
#define SCG_SYSOSCCSTS_SYSOSCEN_1           1U    /* 1 : System OSC is enabled                                                 */


/* ===========================================  SCG SYSOSCCSTS SYSOSCMEN [16..16]  =========================================== */
                                  /* SCG_SYSOSCCSTS_SYSOSCMEN                                                  */
#define SCG_SYSOSCCSTS_SYSOSCMEN_0          0U    /* 0 : System OSC Clock Monitor is disabled                                  */
#define SCG_SYSOSCCSTS_SYSOSCMEN_1          1U    /* 1 : System OSC Clock Monitor is enabled                                   */


/* =========================================  SCG SYSOSCCSTS SYSOSCMRSTEN [17..17]  ========================================== */
                                  /* SCG_SYSOSCCSTS_SYSOSCMRSTEN                                               */
#define SCG_SYSOSCCSTS_SYSOSCMRSTEN_0       0U    /* 0 : Clock Monitor generates interrupt when error detected                 */
#define SCG_SYSOSCCSTS_SYSOSCMRSTEN_1       1U    /* 1 : Clock Monitor generates reset when error detected                     */


/* =============================================  SCG SYSOSCCSTS LOCK [23..23]  ============================================== */
                                  /* SCG_SYSOSCCSTS_LOCK                                                       */
#define SCG_SYSOSCCSTS_LOCK_0               0U    /* 0 : This Control Status Register can be written.                          */
#define SCG_SYSOSCCSTS_LOCK_1               1U    /* 1 : This Control Status Register cannot be written.                       */


/* =========================================  SCG SYSOSCCSTS SYSOSCVLDFLG [24..24]  ========================================== */
                                  /* SCG_SYSOSCCSTS_SYSOSCVLDFLG                                               */
#define SCG_SYSOSCCSTS_SYSOSCVLDFLG_0       0U    /* 0 : System OSC is not enabled or clock is not valid                       */
#define SCG_SYSOSCCSTS_SYSOSCVLDFLG_1       1U    /* 1 : System OSC is enabled and output clock is valid                       */


/* ===========================================  SCG SYSOSCCSTS SYSOSCSEL [25..25]  =========================================== */
                                  /* SCG_SYSOSCCSTS_SYSOSCSEL                                                  */
#define SCG_SYSOSCCSTS_SYSOSCSEL_0          0U    /* 0 : System OSC is not the system clock source                             */
#define SCG_SYSOSCCSTS_SYSOSCSEL_1          1U    /* 1 : System OSC is the system clock source                                 */


/* =========================================  SCG SYSOSCCSTS SYSOSCCLKEFLG [26..26]  ========================================= */
                                  /* SCG_SYSOSCCSTS_SYSOSCCLKEFLG                                              */
#define SCG_SYSOSCCSTS_SYSOSCCLKEFLG_0      0U    /* 0 : System OSC Clock Monitor is disabled or has not detected
                                                     an error                                                                  */
#define SCG_SYSOSCCSTS_SYSOSCCLKEFLG_1      1U    /* 1 : System OSC Clock Monitor is enabled and detected an error             */


/* =====================================================  SYSOSCDIVCFG  ====================================================== */
/* ==========================================  SCG SYSOSCDIVCFG SYSOSCDCFG1 [0..2]  ========================================== */
                                  /* SCG_SYSOSCDIVCFG_SYSOSCDCFG1                                              */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_000    0U    /* 000 : Output disabled                                                     */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_001    1U    /* 001 : Divide by 1                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_010    2U    /* 010 : Divide by 2                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_011    3U    /* 011 : Divide by 4                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_100    4U    /* 100 : Divide by 8                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_101    5U    /* 101 : Divide by 16                                                        */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_110    6U    /* 110 : Divide by 32                                                        */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG1_111    7U    /* 111 : Divide by 64                                                        */


/* =========================================  SCG SYSOSCDIVCFG SYSOSCDCFG2 [8..10]  ========================================== */
                                  /* SCG_SYSOSCDIVCFG_SYSOSCDCFG2                                              */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_000    0U    /* 000 : Output disabled                                                     */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_001    1U    /* 001 : Divide by 1                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_010    2U    /* 010 : Divide by 2                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_011    3U    /* 011 : Divide by 4                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_100    4U    /* 100 : Divide by 8                                                         */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_101    5U    /* 101 : Divide by 16                                                        */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_110    6U    /* 110 : Divide by 32                                                        */
#define SCG_SYSOSCDIVCFG_SYSOSCDCFG2_111    7U    /* 111 : Divide by 64                                                        */


/* =======================================================  SYSOSCCFG  ======================================================= */
/* =============================================  SCG SYSOSCCFG ERCLKSEL [2..2]  ============================================= */
                                  /* SCG_SYSOSCCFG_ERCLKSEL                                                    */
#define SCG_SYSOSCCFG_ERCLKSEL_0            0U    /* 0 : External reference clock selected                                     */
#define SCG_SYSOSCCFG_ERCLKSEL_1            1U    /* 1 : Internal crystal oscillator of OSC selected.                          */


/* =============================================  SCG SYSOSCCFG GOSCSEL [3..3]  ============================================== */
                                  /* SCG_SYSOSCCFG_GOSCSEL                                                     */
#define SCG_SYSOSCCFG_GOSCSEL_0             0U    /* 0 : Configure crystal oscillator for low-gain operation                   */
#define SCG_SYSOSCCFG_GOSCSEL_1             1U    /* 1 : Configure crystal oscillator for high-gain operation                  */


/* ============================================  SCG SYSOSCCFG SYSOSCFSEL [4..5]  ============================================ */
                                  /* SCG_SYSOSCCFG_SYSOSCFSEL                                                  */
#define SCG_SYSOSCCFG_SYSOSCFSEL_01         1U    /* 01 : Low frequency range selected for the crystal oscillator              */
#define SCG_SYSOSCCFG_SYSOSCFSEL_10         2U    /* 10 : Medium frequency range selected for the crytstal oscillator          */
#define SCG_SYSOSCCFG_SYSOSCFSEL_11         3U    /* 11 : High frequency range selected for the crystal oscillator             */


/* ========================================================  LSICSTS  ======================================================== */
/* ===============================================  SCG LSICSTS LSIEN [0..0]  ================================================ */
                                  /* SCG_LSICSTS_LSIEN                                                         */
#define SCG_LSICSTS_LSIEN_0                 0U    /* 0 : Low speed internal oscillator is disabled                                                  */
#define SCG_LSICSTS_LSIEN_1                 1U    /* 1 : Low speed internal oscillator is enabled                                                   */


/* =============================================  SCG LSICSTS LSIEN_STOP [1..1]  ============================================= */
                                  /* SCG_LSICSTS_LSIEN_STOP                                                    */
#define SCG_LSICSTS_LSIEN_STOP_0            0U    /* 0 : Low speed internal oscillator is disabled in supported Stop modes                          */
#define SCG_LSICSTS_LSIEN_STOP_1            1U    /* 1 : Low speed internal oscillator is enabled in supported Stop modes                           */


/* ==============================================  SCG LSICSTS LSIEN_LP [2..2]  ============================================== */
                                  /* SCG_LSICSTS_LSIEN_LP                                                      */
#define SCG_LSICSTS_LSIEN_LP_0              0U    /* 0 : Low speed internal oscillator is disabled in VLP modes                                     */
#define SCG_LSICSTS_LSIEN_LP_1              1U    /* 1 : Low speed internal oscillator is enabled in VLP modes                                      */


/* ===============================================  SCG LSICSTS LOCK [23..23]  =============================================== */
                                  /* SCG_LSICSTS_LOCK                                                          */
#define SCG_LSICSTS_LOCK_0                  0U    /* 0 : Control Status Register can be written.                               */
#define SCG_LSICSTS_LOCK_1                  1U    /* 1 : Control Status Register cannot be written.                            */


/* ============================================  SCG LSICSTS LSIVLDFLG [24..24]  ============================================= */
                                  /* SCG_LSICSTS_LSIVLDFLG                                                     */
#define SCG_LSICSTS_LSIVLDFLG_0             0U    /* 0 : Low speed internal oscillator is not enabled or clock is not valid                         */
#define SCG_LSICSTS_LSIVLDFLG_1             1U    /* 1 : Low speed internal oscillator is enabled and output clock is valid                         */


/* ==============================================  SCG LSICSTS LSISEL [25..25]  ============================================== */
                                  /* SCG_LSICSTS_LSISEL                                                        */
#define SCG_LSICSTS_LSISEL_0                0U    /* 0 : Low speed internal oscillator is not the system clock source                               */
#define SCG_LSICSTS_LSISEL_1                1U    /* 1 : Low speed internal oscillator is the system clock source                                   */


/* =======================================================  LSIDIV  ======================================================= */
/* ===========================================  SCG LSIDIV LSIDIVCFG1 [0..2]  ============================================ */
                                  /* SCG_LSIDIV_LSIDIVCFG1                                                 */
#define  SCG_LSIDIV_LSIDIVCFG1_000       0U    /* 000 : Output disabled                                                     */
#define  SCG_LSIDIV_LSIDIVCFG1_001       1U    /* 001 : Divide by 1                                                         */
#define  SCG_LSIDIV_LSIDIVCFG1_010       2U    /* 010 : Divide by 2                                                         */
#define  SCG_LSIDIV_LSIDIVCFG1_011       3U    /* 011 : Divide by 4                                                         */
#define  SCG_LSIDIV_LSIDIVCFG1_100       4U    /* 100 : Divide by 8                                                         */
#define  SCG_LSIDIV_LSIDIVCFG1_101       5U    /* 101 : Divide by 16                                                        */
#define  SCG_LSIDIV_LSIDIVCFG1_110       6U    /* 110 : Divide by 32                                                        */
#define  SCG_LSIDIV_LSIDIVCFG1_111       7U    /* 111 : Divide by 64                                                        */


/* ===========================================  SCG LSIDIV LSIDIVCFG2 [8..10]  =========================================== */
                                  /* SCG_LSIDIV_LSIDIVCFG2                                                 */
#define  SCG_LSIDIV_LSIDIVCFG2_000       0U    /* 000 : Output disabled                                                     */
#define  SCG_LSIDIV_LSIDIVCFG2_001       1U    /* 001 : Divide by 1                                                         */
#define  SCG_LSIDIV_LSIDIVCFG2_010       2U    /* 010 : Divide by 2                                                         */
#define  SCG_LSIDIV_LSIDIVCFG2_011       3U    /* 011 : Divide by 4                                                         */
#define  SCG_LSIDIV_LSIDIVCFG2_100       4U    /* 100 : Divide by 8                                                         */
#define  SCG_LSIDIV_LSIDIVCFG2_101       5U    /* 101 : Divide by 16                                                        */
#define  SCG_LSIDIV_LSIDIVCFG2_110       6U    /* 110 : Divide by 32                                                        */
#define  SCG_LSIDIV_LSIDIVCFG2_111       7U    /* 111 : Divide by 64                                                        */


/* ========================================================  LSIFSEL  ======================================================== */
/* ==============================================  SCG LSIFSEL LSIFSEL [0..0]  ============================================== */
                                  /* SCG_LSIFSEL_LSIFSEL                                                      */
#define  SCG_LSIFSEL_LSIFSEL_0              0U    /* 0 : Low Speed Internal oscillator low range clock (2 MHz)                                      */
#define  SCG_LSIFSEL_LSIFSEL_1              1U    /* 1 : Low Speed Internal oscillator high range clock (8 MHz )                                    */


/* ========================================================  HSICSTS  ======================================================== */
/* ===============================================  SCG HSICSTS HSIEN [0..0]  ================================================ */
                                  /* SCG_HSICSTS_HSIEN                                                         */
#define SCG_HSICSTS_HSIEN_0                 0U    /* 0 : High speed internal oscillator is disabled                                                  */
#define SCG_HSICSTS_HSIEN_1                 1U    /* 1 : High speed internal oscillator is enabled                                                   */


/* ===============================================  SCG HSICSTS HSIREN [3..3]  =============================================== */
                                  /* SCG_HSICSTS_HSIREN                                                        */
#define SCG_HSICSTS_HSIREN_0                0U    /* 0 : High speed internal oscillator Regulator is enabled.                                        */
#define SCG_HSICSTS_HSIREN_1                1U    /* 1 : High speed internal oscillator Regulator is disabled.                                       */


/* ===============================================  SCG HSICSTS LOCK [23..23]  =============================================== */
                                  /* SCG_HSICSTS_LOCK                                                          */
#define SCG_HSICSTS_LOCK_0                  0U    /* 0 : Control Status Register can be written.                               */
#define SCG_HSICSTS_LOCK_1                  1U    /* 1 : Control Status Register cannot be written.                            */


/* ============================================  SCG HSICSTS HSIVLDFLG [24..24]  ============================================= */
                                  /* SCG_HSICSTS_HSIVLDFLG                                                     */
#define SCG_HSICSTS_HSIVLDFLG_0             0U    /* 0 : High speed internal oscillator is not enabled or clock is not valid.                        */
#define SCG_HSICSTS_HSIVLDFLG_1             1U    /* 1 : High speed internal oscillator is enabled and output clock is valid. The clock
                                                     is valid once there is an output clock from the HSI analog.              */


/* ==============================================  SCG HSICSTS HSISEL [25..25]  ============================================== */
                                  /* SCG_HSICSTS_HSISEL                                                        */
#define SCG_HSICSTS_HSISEL_0                0U    /* 0 : High speed internal oscillator is not the system clock source                               */
#define SCG_HSICSTS_HSISEL_1                1U    /* 1 : High speed internal oscillator is the system clock source                                   */


/* =============================================  SCG HSICSTS HSIEFLG [26..26]  ============================================== */
                                  /* SCG_HSICSTS_HSIEFLG                                                       */
#define SCG_HSICSTS_HSIEFLG_0               0U    /* 0 : Error not detected with the High speed internal oscillator trimming.                        */
#define SCG_HSICSTS_HSIEFLG_1               1U    /* 1 : Error detected with the High speed internal oscillator trimming.                            */


/* ========================================================  HSIDIV  ========================================================= */
/* =============================================  SCG HSIDIV HSIDIVCFG1 [0..2]  ============================================== */
                                  /* SCG_HSIDIV_HSIDIVCFG1                                                     */
#define SCG_HSIDIV_HSIDIVCFG1_000           0U    /* 000 : Output disabled                                                     */
#define SCG_HSIDIV_HSIDIVCFG1_001           1U    /* 001 : Divide by 1                                                         */
#define SCG_HSIDIV_HSIDIVCFG1_010           2U    /* 010 : Divide by 2                                                         */
#define SCG_HSIDIV_HSIDIVCFG1_011           3U    /* 011 : Divide by 4                                                         */
#define SCG_HSIDIV_HSIDIVCFG1_100           4U    /* 100 : Divide by 8                                                         */
#define SCG_HSIDIV_HSIDIVCFG1_101           5U    /* 101 : Divide by 16                                                        */
#define SCG_HSIDIV_HSIDIVCFG1_110           6U    /* 110 : Divide by 32                                                        */
#define SCG_HSIDIV_HSIDIVCFG1_111           7U    /* 111 : Divide by 64                                                        */


/* =============================================  SCG HSIDIV HSIDIVCFG2 [8..10]  ============================================= */
                                  /* SCG_HSIDIV_HSIDIVCFG2                                                     */
#define SCG_HSIDIV_HSIDIVCFG2_000           0U    /* 000 : Output disabled                                                     */
#define SCG_HSIDIV_HSIDIVCFG2_001           1U    /* 001 : Divide by 1                                                         */
#define SCG_HSIDIV_HSIDIVCFG2_010           2U    /* 010 : Divide by 2                                                         */
#define SCG_HSIDIV_HSIDIVCFG2_011           3U    /* 011 : Divide by 4                                                         */
#define SCG_HSIDIV_HSIDIVCFG2_100           4U    /* 100 : Divide by 8                                                         */
#define SCG_HSIDIV_HSIDIVCFG2_101           5U    /* 101 : Divide by 16                                                        */
#define SCG_HSIDIV_HSIDIVCFG2_110           6U    /* 110 : Divide by 32                                                        */
#define SCG_HSIDIV_HSIDIVCFG2_111           7U    /* 111 : Divide by 64                                                        */


/* ========================================================  HSIFSEL  ======================================================== */
/* ==============================================  SCG HSIFSEL HSIFSEL [0..1]  =============================================== */
                                  /* SCG_HSIFSEL_HSIFSEL                                                       */
#define SCG_HSIFSEL_HSIFSEL_00              0U    /* 00 : High speed internal oscillator is trimmed to 48 MHz                                        */


/* ======================================================  SYSPLLCSTS  ======================================================= */
/* ============================================  SCG SYSPLLCSTS SYSPLLEN [0..0]  ============================================= */
                                  /* SCG_SYSPLLCSTS_SYSPLLEN                                                   */
#define SCG_SYSPLLCSTS_SYSPLLEN_0           0U    /* 0 : System PLL is disabled                                                */
#define SCG_SYSPLLCSTS_SYSPLLEN_1           1U    /* 1 : System PLL is enabled                                                 */


/* ===========================================  SCG SYSPLLCSTS SYSPLLMEN [16..16]  =========================================== */
                                  /* SCG_SYSPLLCSTS_SYSPLLMEN                                                  */
#define SCG_SYSPLLCSTS_SYSPLLMEN_0          0U    /* 0 : System PLL Clock Monitor is disabled                                  */
#define SCG_SYSPLLCSTS_SYSPLLMEN_1          1U    /* 1 : System PLL Clock Monitor is enabled                                   */


/* =========================================  SCG SYSPLLCSTS SYSPLLMRSTEN [17..17]  ========================================== */
                                  /* SCG_SYSPLLCSTS_SYSPLLMRSTEN                                               */
#define SCG_SYSPLLCSTS_SYSPLLMRSTEN_0       0U    /* 0 : Clock Monitor generates interrupt when error detected                 */
#define SCG_SYSPLLCSTS_SYSPLLMRSTEN_1       1U    /* 1 : Clock Monitor generates reset when error detected                     */


/* =============================================  SCG SYSPLLCSTS LOCK [23..23]  ============================================== */
                                  /* SCG_SYSPLLCSTS_LOCK                                                       */
#define SCG_SYSPLLCSTS_LOCK_0               0U    /* 0 : Control Status Register can be written.                               */
#define SCG_SYSPLLCSTS_LOCK_1               1U    /* 1 : Control Status Register cannot be written.                            */


/* =========================================  SCG SYSPLLCSTS SYSPLLVLDFLG [24..24]  ========================================== */
                                  /* SCG_SYSPLLCSTS_SYSPLLVLDFLG                                               */
#define SCG_SYSPLLCSTS_SYSPLLVLDFLG_0       0U    /* 0 : System PLL is not enabled or clock is not valid                       */
#define SCG_SYSPLLCSTS_SYSPLLVLDFLG_1       1U    /* 1 : System PLL is enabled and output clock is valid                       */


/* ===========================================  SCG SYSPLLCSTS SYSPLLSEL [25..25]  =========================================== */
                                  /* SCG_SYSPLLCSTS_SYSPLLSEL                                                  */
#define SCG_SYSPLLCSTS_SYSPLLSEL_0          0U    /* 0 : System PLL is not the system clock source                             */
#define SCG_SYSPLLCSTS_SYSPLLSEL_1          1U    /* 1 : System PLL is the system clock source                                 */


/* =========================================  SCG SYSPLLCSTS SYSPLLCLKEFLG [26..26]  ========================================= */
                                  /* SCG_SYSPLLCSTS_SYSPLLCLKEFLG                                              */
#define SCG_SYSPLLCSTS_SYSPLLCLKEFLG_0      0U    /* 0 : System PLL Clock Monitor is disabled or has not detected
                                                     an error                                                                  */
#define SCG_SYSPLLCSTS_SYSPLLCLKEFLG_1      1U    /* 1 : System PLL Clock Monitor is enabled and detected an error.
                                                     System PLL Clock Error flag will not set when System OSC
                                                     is selected as its source and SYSOSCERR has set.                            */


/* =======================================================  SYSPLLDIV  ======================================================= */
/* ==========================================  SCG SYSPLLDIV SYSPLLDIVCFG1 [0..2]  =========================================== */
                                  /* SCG_SYSPLLDIV_SYSPLLDIVCFG1                                               */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_000     0U    /* 000 : Clock disabled                                                      */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_001     1U    /* 001 : Divide by 1                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_010     2U    /* 010 : Divide by 2                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_011     3U    /* 011 : Divide by 4                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_100     4U    /* 100 : Divide by 8                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_101     5U    /* 101 : Divide by 16                                                        */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_110     6U    /* 110 : Divide by 32                                                        */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG1_111     7U    /* 111 : Divide by 64                                                        */


/* ==========================================  SCG SYSPLLDIV SYSPLLDIVCFG2 [8..10]  ========================================== */
                                  /* SCG_SYSPLLDIV_SYSPLLDIVCFG2                                               */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_000     0U    /* 000 : Clock disabled                                                      */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_001     1U    /* 001 : Divide by 1                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_010     2U    /* 010 : Divide by 2                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_011     3U    /* 011 : Divide by 4                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_100     4U    /* 100 : Divide by 8                                                         */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_101     5U    /* 101 : Divide by 16                                                        */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_110     6U    /* 110 : Divide by 32                                                        */
#define SCG_SYSPLLDIV_SYSPLLDIVCFG2_111     7U    /* 111 : Divide by 64                                                        */


/* =======================================================  SYSPLLCFG  ======================================================= */
/* ===========================================  SCG SYSPLLCFG PLLRDIVCFG [8..10]  ============================================ */
                                  /* SCG_SYSPLLCFG_PLLRDIVCFG                                                  */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_000          0U    /* 000 : Divide Factor is 1                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_001          1U    /* 001 : Divide Factor is 2                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_010          2U    /* 010 : Divide Factor is 3                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_011          3U    /* 011 : Divide Factor is 4                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_100          4U    /* 100 : Divide Factor is 5                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_101          5U    /* 101 : Divide Factor is 6                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_110          6U    /* 110 : Divide Factor is 7                                                    */
#define  SCG_SYSPLLCFG_PLLRDIVCFG_111          7U    /* 111 : Divide Factor is 8                                                    */





/* =========================================================================================================================== */
/* ================                                            PCM                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  FLASHCLK  ========================================================= */
/* ==============================================  PCM FLASHCLK FLASHEN [30..30]  =============================================== */
                                  /* PCM_FLASHCLK_FLASHEN                                                  */
#define PCM_FLASHCLK_FLASHEN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_FLASHCLK_FLASHEN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM FLASHCLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_FLASHCLK_PSTFLG                                                   */
#define PCM_FLASHCLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_FLASHCLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  DMACHMCLK  ========================================================= */
/* =============================================  PCM DMACHMCLK DMACHMEN [30..30]  ============================================== */
                                  /* PCM_DMACHMCLK_DMACHMEN                                                */
#define PCM_DMACHMCLK_DMACHMEN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_DMACHMCLK_DMACHMEN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM DMACHMCLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_DMACHMCLK_PSTFLG                                                  */
#define PCM_DMACHMCLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_DMACHMCLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* =======================================================  CAN0CLK  ======================================================== */
/* =============================================  PCM CAN0CLK CAN0EN [30..30]  ============================================== */
                                 /* PCM_CAN0CLK_CAN0EN                                                */
#define PCM_CAN0CLK_CAN0EN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_CAN0CLK_CAN0EN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* =============================================  PCM CAN0CLK PSTFLG [31..31]  ============================================== */
                                   /* PCM_CAN0CLK_PSTFLG                                                */
#define PCM_CAN0CLK_PSTFLG_0                  0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CAN0CLK_PSTFLG_1                  1U      /* 1 : Peripheral is present.                                         */

/* =======================================================  CAN1CLK  ======================================================== */
/* =============================================  PCM CAN1CLK CAN1EN [30..30]  ============================================== */
                                  /* PCM_CAN1CLK_CAN1EN                                                */
#define PCM_CAN1CLK_CAN1EN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_CAN1CLK_CAN1EN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* =============================================  PCM CAN1CLK PSTFLG [31..31]  ============================================== */
                                  /* PCM_CAN1CLK_PSTFLG                                                */
#define PCM_CAN1CLK_PSTFLG_0                  0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CAN1CLK_PSTFLG_1                  1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  CFGTMR3CLK  ========================================================= */
/* ============================================  PCM CFGTMR3CLK CFGTMR3CSSEL [24..26]  ============================================= */
                                   /* PCM_CFGTMR3CLK_CFGTMR3CSSEL                                              */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_000              0U      /* 000 : Clock is off. An external clock can be enabled for this
                                                     peripheral.                                                        */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_001              1U      /* 001 : Clock option 1                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_010              2U      /* 010 : Clock option 2                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_011              3U      /* 011 : Clock option 3                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_100              4U      /* 100 : Clock option 4                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_101              5U      /* 101 : Clock option 5                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_110              6U      /* 110 : Clock option 6                                               */
#define PCM_CFGTMR3CLK_CFGTMR3CSSEL_111              7U      /* 111 : Clock option 7                                               */

/* ==============================================  PCM CFGTMR3CLK CFGTMR3EN [30..30]  =============================================== */
                                   /* PCM_CFGTMR3CLK_CFGTMR3EN                                                  */
#define PCM_CFGTMR3CLK_CFGTMR3EN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_CFGTMR3CLK_CFGTMR3EN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM CFGTMR3CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_CFGTMR3CLK_PSTFLG                                                   */
#define PCM_CFGTMR3CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR3CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  ADC1CLK  ========================================================== */
/* ==============================================  PCM ADC1CLK ADC1CSSEL [24..26]  ============================================== */
                                   /* PCM_ADC1CLK_ADC1CSSEL                                                 */
#define PCM_ADC1CLK_ADC1CSSEL_000                 0U      /* 000 : Clock is off.                                                */
#define PCM_ADC1CLK_ADC1CSSEL_001                 1U      /* 001 : Clock option 1                                               */
#define PCM_ADC1CLK_ADC1CSSEL_010                 2U      /* 010 : Clock option 2                                               */
#define PCM_ADC1CLK_ADC1CSSEL_011                 3U      /* 011 : Clock option 3                                               */
#define PCM_ADC1CLK_ADC1CSSEL_100                 4U      /* 100 : Clock option 4                                               */
#define PCM_ADC1CLK_ADC1CSSEL_101                 5U      /* 101 : Clock option 5                                               */
#define PCM_ADC1CLK_ADC1CSSEL_110                 6U      /* 110 : Clock option 6                                               */
#define PCM_ADC1CLK_ADC1CSSEL_111                 7U      /* 111 : Clock option 7                                               */

/* ===============================================  PCM ADC1CLK ADC1EN [30..30]  ================================================ */
                                  /* PCM_ADC1CLK_ADC1EN                                                    */
#define PCM_ADC1CLK_ADC1EN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_ADC1CLK_ADC1EN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM ADC1CLK PSTFLG [31..31]  ================================================ */
                                 /* PCM_ADC1CLK_PSTFLG                                                    */
#define PCM_ADC1CLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_ADC1CLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  CAN2CLK  ========================================================== */
/* ===============================================  PCM CAN2CLK CAN2EN [30..30]  ================================================ */
                                   /* PCM_CAN2CLK_CAN2EN                                                    */
#define PCM_CAN2CLK_CAN2EN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_CAN2CLK_CAN2EN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM CAN2CLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_CAN2CLK_PSTFLG                                                    */
#define PCM_CAN2CLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CAN2CLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPSPI0CLK  ========================================================= */
/* =============================================  PCM LPSPI0CLK SPI0CSSEL [24..26]  ============================================= */
                                   /* PCM_LPSPI0CLK_SPI0CSSEL                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_000               0U      /* 000 : Clock is off.                                                */
#define PCM_LPSPI0CLK_SPI0CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_LPSPI0CLK_SPI0CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPSPI0CLK LPSPI0EN [30..30]  ============================================== */
                                   /* PCM_LPSPI0CLK_LPSPI0EN                                                */
#define PCM_LPSPI0CLK_LPSPI0EN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPSPI0CLK_LPSPI0EN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPSPI0CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_LPSPI0CLK_PSTFLG                                                  */
#define PCM_LPSPI0CLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPSPI0CLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPSPI1CLK  ========================================================= */
/* =============================================  PCM LPSPI1CLK SPI1CSSEL [24..26]  ============================================= */
                                   /* PCM_LPSPI1CLK_SPI1CSSEL                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_000               0U      /* 000 : Clock is off.                                                */
#define PCM_LPSPI1CLK_SPI1CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_LPSPI1CLK_SPI1CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPSPI1CLK LPSPI1EN [30..30]  ============================================== */
                                  /* PCM_LPSPI1CLK_LPSPI1EN                                                */
#define PCM_LPSPI1CLK_LPSPI1EN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPSPI1CLK_LPSPI1EN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPSPI1CLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_LPSPI1CLK_PSTFLG                                                  */
#define PCM_LPSPI1CLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPSPI1CLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPSPI2CLK  ========================================================= */
/* =============================================  PCM LPSPI2CLK SPI2CSSEL [24..26]  ============================================= */
                                  /* PCM_LPSPI2CLK_SPI2CSSEL                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_000               0U      /* 000 : Clock is off.                                                */
#define PCM_LPSPI2CLK_SPI2CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_LPSPI2CLK_SPI2CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPSPI2CLK LPSPI2EN [30..30]  ============================================== */
                                  /* PCM_LPSPI2CLK_LPSPI2EN                                                */
#define PCM_LPSPI2CLK_LPSPI2EN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPSPI2CLK_LPSPI2EN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPSPI2CLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_LPSPI2CLK_PSTFLG                                                  */
#define PCM_LPSPI2CLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPSPI2CLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  PDU1CLK  ========================================================== */
/* ===============================================  PCM PDU1CLK PDU1EN [30..30]  ================================================ */
                                   /* PCM_PDU1CLK_PDU1EN                                                    */
#define PCM_PDU1CLK_PDU1EN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_PDU1CLK_PDU1EN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM PDU1CLK PSTFLG [31..31]  ================================================ */
                                  /* PCM_PDU1CLK_PSTFLG                                                    */
#define PCM_PDU1CLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PDU1CLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  CRCCLK  ========================================================== */
/* ================================================  PCM CRCCLK CRCEN [30..30]  ================================================= */
                                   /* PCM_CRCCLK_CRCEN                                                      */
#define PCM_CRCCLK_CRCEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_CRCCLK_CRCEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM CRCCLK PSTFLG [31..31]  ================================================ */
                                  /* PCM_CRCCLK_PSTFLG                                                     */
#define PCM_CRCCLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CRCCLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  PDU0CLK  ========================================================== */
/* ===============================================  PCM PDU0CLK PDU0EN [30..30]  ================================================ */
                                   /* PCM_PDU0CLK_PDU0EN                                                    */
#define PCM_PDU0CLK_PDU0EN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_PDU0CLK_PDU0EN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM PDU0CLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_PDU0CLK_PSTFLG                                                    */
#define PCM_PDU0CLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PDU0CLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPITMRCLK  ========================================================= */
                                   /* PCM_LPITMRCLK_LPITMRCSSEL                                             */
#define PCM_LPITMRCLK_LPITMRCSSEL_000             0U      /* 000 : Clock is off.                                                */
#define PCM_LPITMRCLK_LPITMRCSSEL_001             1U      /* 001 : Clock option 1                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_010             2U      /* 010 : Clock option 2                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_011             3U      /* 011 : Clock option 3                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_100             4U      /* 100 : Clock option 4                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_101             5U      /* 101 : Clock option 5                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_110             6U      /* 110 : Clock option 6                                               */
#define PCM_LPITMRCLK_LPITMRCSSEL_111             7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPITMRCLK LPITMREN [30..30]  ============================================== */
                                   /* PCM_LPITMRCLK_LPITMREN                                                */
#define PCM_LPITMRCLK_LPITMREN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPITMRCLK_LPITMREN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPITMRCLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_LPITMRCLK_PSTFLG                                                  */
#define PCM_LPITMRCLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPITMRCLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  CFGTMR0CLK  ========================================================= */
/* =============================================  PCM CFGTMR0CLK CFGTMR0CSSEL [24..26]  ============================================= */
                                /* PCM_CFGTMR0CLK_CFGTMR0CSSEL                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_000               0U      /* 000 : Clock is off. An external clock can be enabled for this
                                                     peripheral.                                                        */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_CFGTMR0CLK_CFGTMR0CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* ==============================================  PCM CFGTMR0CLK CFGTMR0EN [30..30]  =============================================== */
                                 /* PCM_CFGTMR0CLK_CFGTMR0EN                                                  */
#define PCM_CFGTMR0CLK_CFGTMR0EN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_CFGTMR0CLK_CFGTMR0EN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM CFGTMR0CLK PSTFLG [31..31]  =============================================== */
                                 /* PCM_CFGTMR0CLK_PSTFLG                                                   */
#define PCM_CFGTMR0CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR0CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  CFGTMR1CLK  ========================================================= */
/* =============================================  PCM CFGTMR1CLK CFGTMR1CSSEL [24..26]  ============================================= */
                                 /* PCM_CFGTMR1CLK_CFGTMR1CSSEL                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_000               0U      /* 000 : Clock is off. An external clock can be enabled for this
                                                     peripheral.                                                        */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_CFGTMR1CLK_CFGTMR1CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* ==============================================  PCM CFGTMR1CLK CFGTMR1EN [30..30]  =============================================== */
                                  /* PCM_CFGTMR1CLK_CFGTMR1EN                                                  */
#define PCM_CFGTMR1CLK_CFGTMR1EN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_CFGTMR1CLK_CFGTMR1EN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM CFGTMR1CLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_CFGTMR1CLK_PSTFLG                                                   */
#define PCM_CFGTMR1CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR1CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  CFGTMR2CLK  ========================================================= */
/* =============================================  PCM CFGTMR2CLK CFGTMR2CSSEL [24..26]  ============================================= */
                                  /* PCM_CFGTMR2CLK_CFGTMR2CSSEL                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_000               0U      /* 000 : Clock is off. An external clock can be enabled for this
                                                     peripheral.                                                        */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_001               1U      /* 001 : Clock option 1                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_010               2U      /* 010 : Clock option 2                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_011               3U      /* 011 : Clock option 3                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_100               4U      /* 100 : Clock option 4                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_101               5U      /* 101 : Clock option 5                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_110               6U      /* 110 : Clock option 6                                               */
#define PCM_CFGTMR2CLK_CFGTMR2CSSEL_111               7U      /* 111 : Clock option 7                                               */

/* ==============================================  PCM CFGTMR2CLK CFGTMR2EN [30..30]  =============================================== */
                                 /* PCM_CFGTMR2CLK_CFGTMR2EN                                                  */
#define PCM_CFGTMR2CLK_CFGTMR2EN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_CFGTMR2CLK_CFGTMR2EN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM CFGTMR2CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_CFGTMR2CLK_PSTFLG                                                   */
#define PCM_CFGTMR2CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR2CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  ADC0CLK  ========================================================== */
/* ==============================================  PCM ADC0CLK ADC0CSSEL [24..26]  ============================================== */
                                  /* PCM_ADC0CLK_ADC0CSSEL                                                 */
#define PCM_ADC0CLK_ADC0CSSEL_000                 0U      /* 000 : Clock is off.                                                */
#define PCM_ADC0CLK_ADC0CSSEL_001                 1U      /* 001 : Clock option 1                                               */
#define PCM_ADC0CLK_ADC0CSSEL_010                 2U      /* 010 : Clock option 2                                               */
#define PCM_ADC0CLK_ADC0CSSEL_011                 3U      /* 011 : Clock option 3                                               */
#define PCM_ADC0CLK_ADC0CSSEL_100                 4U      /* 100 : Clock option 4                                               */
#define PCM_ADC0CLK_ADC0CSSEL_101                 5U      /* 101 : Clock option 5                                               */
#define PCM_ADC0CLK_ADC0CSSEL_110                 6U      /* 110 : Clock option 6                                               */
#define PCM_ADC0CLK_ADC0CSSEL_111                 7U      /* 111 : Clock option 7                                               */

/* ===============================================  PCM ADC0CLK ADC0EN [30..30]  ================================================ */
                                   /* PCM_ADC0CLK_ADC0EN                                                    */
#define PCM_ADC0CLK_ADC0EN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_ADC0CLK_ADC0EN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM ADC0CLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_ADC0CLK_PSTFLG                                                    */
#define PCM_ADC0CLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_ADC0CLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  RTCCLK  ========================================================== */
/* ================================================  PCM RTCCLK RTCEN [30..30]  ================================================= */
                                   /* PCM_RTCCLK_RTCEN                                                      */
#define PCM_RTCCLK_RTCEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_RTCCLK_RTCEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM RTCCLK PSTFLG [31..31]  ================================================ */
                                  /* PCM_RTCCLK_PSTFLG                                                     */
#define PCM_RTCCLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_RTCCLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPTMRCLK  ========================================================= */
/* ============================================  PCM LPTMRCLK LPTMRDIVDCFG [0..2]  ============================================ */
                                  /* PCM_LPTMRCLK_LPTMRDIVDCFG                                           */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_000           0U      /* 000 : Divide by 1.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_001           1U      /* 001 : Divide by 2.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_010           2U      /* 010 : Divide by 3.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_011           3U      /* 011 : Divide by 4.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_100           4U      /* 100 : Divide by 5.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_101           5U      /* 101 : Divide by 6.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_110           6U      /* 110 : Divide by 7.                                                 */
#define PCM_LPTMRCLK_LPTMRDIVDCFG_111           7U      /* 111 : Divide by 8.                                                 */

/* ============================================  PCM LPTMRCLK LPTMRDIVNCFG [3..3]  ============================================ */
                                  /* PCM_LPTMRCLK_LPTMRDIVNCFG                                           */
#define PCM_LPTMRCLK_LPTMRDIVNCFG_0             0U      /* 0 : Fractional value is 0.                                         */
#define PCM_LPTMRCLK_LPTMRDIVNCFG_1             1U      /* 1 : Fractional value is 1.                                         */

/* ============================================  PCM LPTMRCLK LPTMRCSSEL [24..26]  ============================================ */
                                   /* PCM_LPTMRCLK_LPTMRCSSEL                                             */
#define PCM_LPTMRCLK_LPTMRCSSEL_000             0U      /* 000 : Clock is off.                                                */
#define PCM_LPTMRCLK_LPTMRCSSEL_001             1U      /* 001 : Clock option 1                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_010             2U      /* 010 : Clock option 2                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_011             3U      /* 011 : Clock option 3                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_100             4U      /* 100 : Clock option 4                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_101             5U      /* 101 : Clock option 5                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_110             6U      /* 110 : Clock option 6                                               */
#define PCM_LPTMRCLK_LPTMRCSSEL_111             7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPTMRCLK LPTMREN [30..30]  ============================================== */
                                  /* PCM_LPTMRCLK_LPTMREN                                                */
#define PCM_LPTMRCLK_LPTMREN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPTMRCLK_LPTMREN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPTMRCLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_LPTMRCLK_PSTFLG                                                  */
#define PCM_LPTMRCLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPTMRCLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  PMACLK  ========================================================== */
/* ================================================  PCM PMACLK PMAEN [30..30]  ================================================= */
                                  /* PCM_PMACLK_PMAEN                                                      */
#define PCM_PMACLK_PMAEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_PMACLK_PMAEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM PMACLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_PMACLK_PSTFLG                                                     */
#define PCM_PMACLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PMACLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  PMBCLK  ========================================================== */
/* ================================================  PCM PMBCLK PMBEN [30..30]  ================================================= */
                                 /* PCM_PMBCLK_PMBEN                                                      */
#define PCM_PMBCLK_PMBEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_PMBCLK_PMBEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM PMBCLK PSTFLG [31..31]  ================================================ */
                                  /* PCM_PMBCLK_PSTFLG                                                     */
#define PCM_PMBCLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PMBCLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  PMCCLK  ========================================================== */
/* ================================================  PCM PMCCLK PMCEN [30..30]  ================================================= */
                                   /* PCM_PMCCLK_PMCEN                                                      */
#define PCM_PMCCLK_PMCEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_PMCCLK_PMCEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM PMCCLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_PMCCLK_PSTFLG                                                     */
#define PCM_PMCCLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PMCCLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  PMDCLK  ========================================================== */
/* ================================================  PCM PMDCLK PMDEN [30..30]  ================================================= */
                                    /* PCM_PMDCLK_PMDEN                                                      */
#define PCM_PMDCLK_PMDEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_PMDCLK_PMDEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM PMDCLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_PMDCLK_PSTFLG                                                     */
#define PCM_PMDCLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PMDCLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  PMECLK  ========================================================== */
/* ================================================  PCM PMECLK PMEEN [30..30]  ================================================= */
                                   /* PCM_PMECLK_PMEEN                                                      */
#define PCM_PMECLK_PMEEN_0                        0U      /* 0 : Clock disabled                                                 */
#define PCM_PMECLK_PMEEN_1                        1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM PMECLK PSTFLG [31..31]  ================================================ */
                                   /* PCM_PMECLK_PSTFLG                                                     */
#define PCM_PMECLK_PSTFLG_0                       0U      /* 0 : Peripheral is not present.                                     */
#define PCM_PMECLK_PSTFLG_1                       1U      /* 1 : Peripheral is present.                                         */

/* ==========================================================  CFGIOCLK  =========================================================== */
/* ================================================  PCM CFGIOCLK CFGIOCSSEL [24..26]  ================================================ */
                                   /* PCM_CFGIOCLK_CFGIOCSSEL                                                     */
#define PCM_CFGIOCLK_CFGIOCSSEL_000                     0U      /* 000 : Clock is off.                                                */
#define PCM_CFGIOCLK_CFGIOCSSEL_001                     1U      /* 001 : Clock option 1                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_010                     2U      /* 010 : Clock option 2                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_011                     3U      /* 011 : Clock option 3                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_100                     4U      /* 100 : Clock option 4                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_101                     5U      /* 101 : Clock option 5                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_110                     6U      /* 110 : Clock option 6                                               */
#define PCM_CFGIOCLK_CFGIOCSSEL_111                     7U      /* 111 : Clock option 7                                               */

/* =================================================  PCM CFGIOCLK CFGIOEN [30..30]  ================================================== */
                                   /* PCM_CFGIOCLK_CFGIOEN                                                        */
#define PCM_CFGIOCLK_CFGIOEN_0                          0U      /* 0 : Clock disabled                                                 */
#define PCM_CFGIOCLK_CFGIOEN_1                          1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ================================================  PCM CFGIOCLK PSTFLG [31..31]  ================================================= */
                                   /* PCM_CFGIOCLK_PSTFLG                                                      */
#define PCM_CFGIOCLK_PSTFLG_0                        0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGIOCLK_PSTFLG_1                        1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  EWDTCLK  ========================================================== */
/* ===============================================  PCM EWDTCLK EWDTEN [30..30]  ================================================ */
                                   /* PCM_EWDTCLK_EWDTEN                                                    */
#define PCM_EWDTCLK_EWDTEN_0                      0U      /* 0 : Clock disabled                                                 */
#define PCM_EWDTCLK_EWDTEN_1                      1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM EWDTCLK PSTFLG [31..31]  ================================================ */
                                  /* PCM_EWDTCLK_PSTFLG                                                    */
#define PCM_EWDTCLK_PSTFLG_0                      0U      /* 0 : Peripheral is not present.                                     */
#define PCM_EWDTCLK_PSTFLG_1                      1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPI2CCLK  ========================================================= */
/* ============================================  PCM LPI2CCLK LPI2CCSSEL [24..26]  ============================================ */
                                  /* PCM_LPI2CCLK_LPI2CCSSEL                                             */
#define PCM_LPI2CCLK_LPI2CCSSEL_000             0U      /* 000 : Clock is off.                                                */
#define PCM_LPI2CCLK_LPI2CCSSEL_001             1U      /* 001 : Clock option 1                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_010             2U      /* 010 : Clock option 2                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_011             3U      /* 011 : Clock option 3                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_100             4U      /* 100 : Clock option 4                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_101             5U      /* 101 : Clock option 5                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_110             6U      /* 110 : Clock option 6                                               */
#define PCM_LPI2CCLK_LPI2CCSSEL_111             7U      /* 111 : Clock option 7                                               */

/* =============================================  PCM LPI2CCLK LPI2CEN [30..30]  ============================================== */
                                  /* PCM_LPI2CCLK_LPI2CEN                                                */
#define PCM_LPI2CCLK_LPI2CEN_0                  0U      /* 0 : Clock disabled                                                 */
#define PCM_LPI2CCLK_LPI2CEN_1                  1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPI2CCLK PSTFLG [31..31]  =============================================== */
                                  /* PCM_LPI2CCLK_PSTFLG                                                  */
#define PCM_LPI2CCLK_PSTFLG_0                    0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPI2CCLK_PSTFLG_1                    1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPUART0CLK  ======================================================== */
/* ===========================================  PCM LPUART0CLK LPUART0CSSEL [24..26]  =========================================== */
                                  /* PCM_LPUART0CLK_LPUART0CSSEL                                           */
#define PCM_LPUART0CLK_LPUART0CSSEL_000           0U      /* 000 : Clock is off.                                                */
#define PCM_LPUART0CLK_LPUART0CSSEL_001           1U      /* 001 : Clock option 1                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_010           2U      /* 010 : Clock option 2                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_011           3U      /* 011 : Clock option 3                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_100           4U      /* 100 : Clock option 4                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_101           5U      /* 101 : Clock option 5                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_110           6U      /* 110 : Clock option 6                                               */
#define PCM_LPUART0CLK_LPUART0CSSEL_111           7U      /* 111 : Clock option 7                                               */

/* ============================================  PCM LPUART0CLK LPUART0EN [30..30]  ============================================= */
                                 /* PCM_LPUART0CLK_LPUART0EN                                              */
#define PCM_LPUART0CLK_LPUART0EN_0                0U      /* 0 : Clock disabled                                                 */
#define PCM_LPUART0CLK_LPUART0EN_1                1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPUART0CLK PSTFLG [31..31]  ============================================== */
                                   /* PCM_LPUART0CLK_PSTFLG                                                 */
#define PCM_LPUART0CLK_PSTFLG_0                   0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPUART0CLK_PSTFLG_1                   1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPUART1CLK  ======================================================== */
/* ===========================================  PCM LPUART1CLK LPUART1CSSEL [24..26]  =========================================== */
                                   /* PCM_LPUART1CLK_LPUART1CSSEL                                           */
#define PCM_LPUART1CLK_LPUART1CSSEL_000           0U      /* 000 : Clock is off.                                                */
#define PCM_LPUART1CLK_LPUART1CSSEL_001           1U      /* 001 : Clock option 1                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_010           2U      /* 010 : Clock option 2                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_011           3U      /* 011 : Clock option 3                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_100           4U      /* 100 : Clock option 4                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_101           5U      /* 101 : Clock option 5                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_110           6U      /* 110 : Clock option 6                                               */
#define PCM_LPUART1CLK_LPUART1CSSEL_111           7U      /* 111 : Clock option 7                                               */

/* ============================================  PCM LPUART1CLK LPUART1EN [30..30]  ============================================= */
                                   /* PCM_LPUART1CLK_LPUART1EN                                              */
#define PCM_LPUART1CLK_LPUART1EN_0                0U      /* 0 : Clock disabled                                                 */
#define PCM_LPUART1CLK_LPUART1EN_1                1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPUART1CLK PSTFLG [31..31]  ============================================== */
                                  /* PCM_LPUART1CLK_PSTFLG                                                 */
#define PCM_LPUART1CLK_PSTFLG_0                   0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPUART1CLK_PSTFLG_1                   1U      /* 1 : Peripheral is present.                                         */

/* ========================================================  LPUART2CLK  ======================================================== */
/* ===========================================  PCM LPUART2CLK LPUART2CSSEL [24..26]  =========================================== */
                                   /* PCM_LPUART2CLK_LPUART2CSSEL                                           */
#define PCM_LPUART2CLK_LPUART2CSSEL_000           0U      /* 000 : Clock is off.                                                */
#define PCM_LPUART2CLK_LPUART2CSSEL_001           1U      /* 001 : Clock option 1                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_010           2U      /* 010 : Clock option 2                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_011           3U      /* 011 : Clock option 3                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_100           4U      /* 100 : Clock option 4                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_101           5U      /* 101 : Clock option 5                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_110           6U      /* 110 : Clock option 6                                               */
#define PCM_LPUART2CLK_LPUART2CSSEL_111           7U      /* 111 : Clock option 7                                               */

/* ============================================  PCM LPUART2CLK LPUART2EN [30..30]  ============================================= */
                                  /* PCM_LPUART2CLK_LPUART2EN                                              */
#define PCM_LPUART2CLK_LPUART2EN_0                0U      /* 0 : Clock disabled                                                 */
#define PCM_LPUART2CLK_LPUART2EN_1                1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ==============================================  PCM LPUART2CLK PSTFLG [31..31]  ============================================== */
                                   /* PCM_LPUART2CLK_PSTFLG                                                 */
#define PCM_LPUART2CLK_PSTFLG_0                   0U      /* 0 : Peripheral is not present.                                     */
#define PCM_LPUART2CLK_PSTFLG_1                   1U      /* 1 : Peripheral is present.                                         */

/* =========================================================  COMP0CLK  ========================================================= */
/* ==============================================  PCM COMP0CLK COMP0EN [30..30]  =============================================== */
                                  /* PCM_COMP0CLK_COMP0EN                                                  */
#define PCM_COMP0CLK_COMP0EN_0                    0U      /* 0 : Clock disabled                                                 */
#define PCM_COMP0CLK_COMP0EN_1                    1U      /* 1 : Clock enabled. The current clock selection and divider options
                                                     are locked.                                                        */

/* ===============================================  PCM COMP0CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_COMP0CLK_PSTFLG                                                   */
#define PCM_COMP0CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_COMP0CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* ===============================================  PCM CFGTMR4CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_CFGTMR4CLK_PSTFLG                                                   */
#define PCM_CFGTMR4CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR4CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */

/* ===============================================  PCM CFGTMR5CLK PSTFLG [31..31]  =============================================== */
                                   /* PCM_CFGTMR5CLK_PSTFLG                                                   */
#define PCM_CFGTMR5CLK_PSTFLG_0                     0U      /* 0 : Peripheral is not present.                                     */
#define PCM_CFGTMR5CLK_PSTFLG_1                     1U      /* 1 : Peripheral is present.                                         */


/* =========================================================================================================================== */
/* ================                                           LPI2C                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  VERID  ======================================================== */
/* =============================================  LPI2C VERID FEATURE [0..15]  ============================================= */
                                  /* LPI2C_VERSION_FEATURE                                              */
#define LPI2C_VERID_FEATURE_0000000000000010   2U    /* 0000000000000010 : Master only with standard feature set.          */
#define LPI2C_VERID_FEATURE_0000000000000011   3U    /* 0000000000000011 : Master and slave with standard feature set.     */

/* ==========================================================  PARA  ========================================================== */
/* =========================================================  MCTRL  ========================================================= */
/* ================================================  LPI2C MCTRL MMEN [0..0]  ================================================ */
                                  /* LPI2C_MCTRL_MMEN                                                   */
#define LPI2C_MCTRL_MMEN_0                     0U      /* 0 : Master logic is disabled.                                      */
#define LPI2C_MCTRL_MMEN_1                     1U      /* 1 : Master logic is enabled.                                       */

/* ================================================  LPI2C MCTRL MRST [1..1]  ================================================ */
                                  /* LPI2C_MCTRL_MRST                                                   */
#define LPI2C_MCTRL_MRST_0                     0U      /* 0 : Master logic is not reset.                                     */
#define LPI2C_MCTRL_MRST_1                     1U      /* 1 : Master logic is reset.                                         */

/* ================================================  LPI2C MCTRL DOZEDIS [2..2]  ================================================ */
                                  /* LPI2C_MCTRL_DOZEDIS                                                   */
#define LPI2C_MCTRL_DOZEDIS_0                     0U      /* 0 : Master is enabled in Doze mode.                                */
#define LPI2C_MCTRL_DOZEDIS_1                     1U      /* 1 : Master is disabled in Doze mode.                               */

/* ================================================  LPI2C MCTRL DBGEN [3..3]  ================================================ */
                                   /* LPI2C_MCTRL_DBGEN                                                   */
#define LPI2C_MCTRL_DBGEN_0                     0U      /* 0 : Master is disabled in debug mode.                              */
#define LPI2C_MCTRL_DBGEN_1                     1U      /* 1 : Master is enabled in debug mode.                               */

/* ===============================================  LPI2C MCTRL TXFRST [8..8]  =============================================== */
                                  /* LPI2C_MCTRL_TXFRST                                                 */
#define LPI2C_MCTRL_TXFRST_0                   0U      /* 0 : No effect.                                                     */
#define LPI2C_MCTRL_TXFRST_1                   1U      /* 1 : Transmit FIFO is reset.                                        */

/* ===============================================  LPI2C MCTRL RXFRST [9..9]  =============================================== */
                                  /* LPI2C_MCTRL_RXFRST                                                 */
#define LPI2C_MCTRL_RXFRST_0                   0U      /* 0 : No effect.                                                     */
#define LPI2C_MCTRL_RXFRST_1                   1U      /* 1 : Receive FIFO is reset.                                         */

/* =========================================================  MSTS  ========================================================== */
/* ================================================  LPI2C MSTS TXFLG [0..0]  ================================================ */
                                  /* LPI2C_MSTS_TXFLG                                                   */
#define LPI2C_MSTS_TXFLG_0                     0U      /* 0 : Transmit data not requested.                                   */
#define LPI2C_MSTS_TXFLG_1                     1U      /* 1 : Transmit data is requested.                                    */

/* ================================================  LPI2C MSTS RXFLG [1..1]  ================================================ */
                                  /* LPI2C_MSTS_RXFLG                                                   */
#define LPI2C_MSTS_RXFLG_0                     0U      /* 0 : Receive Data is not ready.                                     */
#define LPI2C_MSTS_RXFLG_1                     1U      /* 1 : Receive data is ready.                                         */

/* ===============================================  LPI2C MSTS ENDFLG [8..8]  ================================================ */
                                   /* LPI2C_MSTS_ENDFLG                                                  */
#define LPI2C_MSTS_ENDFLG_0                    0U      /* 0 : Master has not generated a STOP or Repeated START condition.   */
#define LPI2C_MSTS_ENDFLG_1                    1U      /* 1 : Master has generated a STOP or Repeated START condition.       */

/* ===============================================  LPI2C MSTS STOPFLG [9..9]  =============================================== */
                                   /* LPI2C_MSTS_STOPFLG                                                 */
#define LPI2C_MSTS_STOPFLG_0                   0U      /* 0 : Master has not generated a STOP condition.                     */
#define LPI2C_MSTS_STOPFLG_1                   1U      /* 1 : Master has generated a STOP condition.                         */

/* ==============================================  LPI2C MSTS NACKFLG [10..10]  ============================================== */
                                   /* LPI2C_MSTS_NACKFLG                                                 */
#define LPI2C_MSTS_NACKFLG_0                   0U      /* 0 : Unexpected NACK not detected.                                  */
#define LPI2C_MSTS_NACKFLG_1                   1U      /* 1 : Unexpected NACK was detected.                                  */

/* ==============================================  LPI2C MSTS MALFLG [11..11]  =============================================== */
                                   /* LPI2C_MSTS_MALFLG                                                  */
#define LPI2C_MSTS_MALFLG_0                    0U      /* 0 : Master has not lost arbitration.                               */
#define LPI2C_MSTS_MALFLG_1                    1U      /* 1 : Master has lost arbitration.                                   */

/* ===============================================  LPI2C MSTS FEFLG [12..12]  =============================================== */
                                  /* LPI2C_MSTS_FEFLG                                                   */
#define LPI2C_MSTS_FEFLG_0                     0U      /* 0 : No error.                                                      */
#define LPI2C_MSTS_FEFLG_1                     1U      /* 1 : Master sending or receiving data without START condition.      */

/* ==============================================  LPI2C MSTS PLTFLG [13..13]  =============================================== */
                                   /* LPI2C_MSTS_PLTFLG                                                  */
#define LPI2C_MSTS_PLTFLG_0                    0U      /* 0 : Pin low timeout has not occurred or is disabled.               */
#define LPI2C_MSTS_PLTFLG_1                    1U      /* 1 : Pin low timeout has occurred.                                  */

/* ==============================================  LPI2C MSTS RXMFLG [14..14]  =============================================== */
                                  /* LPI2C_MSTS_RXMFLG                                                  */
#define LPI2C_MSTS_RXMFLG_0                    0U      /* 0 : Have not received matching data.                               */
#define LPI2C_MSTS_RXMFLG_1                    1U      /* 1 : Have received matching data.                                   */

/* ==============================================  LPI2C MSTS MBSYFLG [24..24]  ============================================== */
                                   /* LPI2C_MSTS_MBSYFLG                                                 */
#define LPI2C_MSTS_MBSYFLG_0                   0U      /* 0 : I2C Master is idle.                                            */
#define LPI2C_MSTS_MBSYFLG_1                   1U      /* 1 : I2C Master is busy.                                            */

/* ==============================================  LPI2C MSTS BBSYFLG [25..25]  ============================================== */
                                  /* LPI2C_MSTS_BBSYFLG                                                 */
#define LPI2C_MSTS_BBSYFLG_0                   0U      /* 0 : I2C Bus is idle.                                               */
#define LPI2C_MSTS_BBSYFLG_1                   1U      /* 1 : I2C Bus is busy.                                               */

/* ========================================================  MINTEN  ========================================================= */
                                   /* LPI2C_MINTEN_TXDIEN                                                */
#define LPI2C_MINTEN_TXDIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_TXDIEN_1                  1U      /* 1 : Interrupt enabled                                              */

/* ==============================================  LPI2C MINTEN RXDIEN [1..1]  =============================================== */
                                   /* LPI2C_MINTEN_RXDIEN                                                */
#define LPI2C_MINTEN_RXDIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_RXDIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C MINTEN ENDIEN [8..8]  =============================================== */
                                 /* LPI2C_MINTEN_ENDIEN                                                */
#define LPI2C_MINTEN_ENDIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_ENDIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C MINTEN STOPIEN [9..9]  ============================================== */
                                   /* LPI2C_MINTEN_STOPIEN                                               */
#define LPI2C_MINTEN_STOPIEN_0                 0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_STOPIEN_1                 1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C MINTEN NACKIEN [10..10]  ============================================= */
                                  /* LPI2C_MINTEN_NACKIEN                                               */
#define LPI2C_MINTEN_NACKIEN_0                 0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_NACKIEN_1                 1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C MINTEN MALIEN [11..11]  ============================================== */
                                  /* LPI2C_MINTEN_MALIEN                                                */
#define LPI2C_MINTEN_MALIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_MALIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C MINTEN FEIEN [12..12]  ============================================== */
                                   /* LPI2C_MINTEN_FEIEN                                                 */
#define LPI2C_MINTEN_FEIEN_0                   0U      /* 0 : Interrupt enabled.                                             */
#define LPI2C_MINTEN_FEIEN_1                   1U      /* 1 : Interrupt disabled.                                            */

/* =============================================  LPI2C MINTEN PLTIEN [13..13]  ============================================== */
                                  /* LPI2C_MINTEN_PLTIEN                                                */
#define LPI2C_MINTEN_PLTIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_PLTIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C MINTEN RXMIEN [14..14]  ============================================== */
                                  /* LPI2C_MINTEN_RXMIEN                                                */
#define LPI2C_MINTEN_RXMIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_MINTEN_RXMIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ========================================================  MDMAEN  ========================================================= */
/* ==============================================  LPI2C MDMAEN TXDMAEN [0..0]  ============================================== */
                                 /* LPI2C_MDMAEN_TXDMAEN                                               */
#define LPI2C_MDMAEN_TXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPI2C_MDMAEN_TXDMAEN_1                 1U      /* 1 : DMA request enabled                                            */

/* ==============================================  LPI2C MDMAEN RXDMAEN [1..1]  ============================================== */
                                  /* LPI2C_MDMAEN_RXDMAEN                                               */
#define LPI2C_MDMAEN_RXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPI2C_MDMAEN_RXDMAEN_1                 1U      /* 1 : DMA request enabled.                                           */

/* =========================================================  MCFG0  ========================================================= */
/* ===============================================  LPI2C MCFG0 HRIEN [0..0]  ================================================ */
                                   /* LPI2C_MCFG0_HRIEN                                                  */
#define LPI2C_MCFG0_HRIEN_0                    0U      /* 0 : Host request input is disabled.                                */
#define LPI2C_MCFG0_HRIEN_1                    1U      /* 1 : Host request input is enabled.                                 */

/* ===============================================  LPI2C MCFG0 HRPCFG [1..1]  =============================================== */
                                  /* LPI2C_MCFG0_HRPCFG                                                 */
#define LPI2C_MCFG0_HRPCFG_0                   0U      /* 0 : Active low.                                                    */
#define LPI2C_MCFG0_HRPCFG_1                   1U      /* 1 : Active high.                                                   */

/* ===============================================  LPI2C MCFG0 HRISRC [2..2]  =============================================== */
                                  /* LPI2C_MCFG0_HRISRC                                                 */
#define LPI2C_MCFG0_HRISRC_0                   0U      /* 0 : Host request input is pin HREQ.                                */
#define LPI2C_MCFG0_HRISRC_1                   1U      /* 1 : Host request input is input trigger.                           */

/* ================================================  LPI2C MCFG0 CFEN [8..8]  ================================================ */
                                  /* LPI2C_MCFG0_CFEN                                                   */
#define LPI2C_MCFG0_CFEN_0                     0U      /* 0 : Circular FIFO is disabled.                                     */
#define LPI2C_MCFG0_CFEN_1                     1U      /* 1 : Circular FIFO is enabled.                                      */

/* ===============================================  LPI2C MCFG0 RXMEN [9..9]  ================================================ */
                                  /* LPI2C_MCFG0_RXMEN                                                  */
#define LPI2C_MCFG0_RXMEN_0                    0U      /* 0 : Received data is stored in the receive FIFO as normal.         */
#define LPI2C_MCFG0_RXMEN_1                    1U      /* 1 : Received data is discarded unless the RMF is set.              */

/* =========================================================  MCFG1  ========================================================= */
/* ===============================================  LPI2C MCFG1 CLKPS [0..2]  ================================================ */
                                   /* LPI2C_MCFG1_CLKPS                                                  */
#define LPI2C_MCFG1_CLKPS_000                  0U      /* 000 : Divide by 1.                                                 */
#define LPI2C_MCFG1_CLKPS_001                  1U      /* 001 : Divide by 2.                                                 */
#define LPI2C_MCFG1_CLKPS_010                  2U      /* 010 : Divide by 4.                                                 */
#define LPI2C_MCFG1_CLKPS_011                  3U      /* 011 : Divide by 8.                                                 */
#define LPI2C_MCFG1_CLKPS_100                  4U      /* 100 : Divide by 16.                                                */
#define LPI2C_MCFG1_CLKPS_101                  5U      /* 101 : Divide by 32.                                                */
#define LPI2C_MCFG1_CLKPS_110                  6U      /* 110 : Divide by 64.                                                */
#define LPI2C_MCFG1_CLKPS_111                  7U      /* 111 : Divide by 128.                                               */

/* ===============================================  LPI2C MCFG1 ASGEN [8..8]  ================================================ */
                                  /* LPI2C_MCFG1_ASGEN                                                  */
#define LPI2C_MCFG1_ASGEN_0                    0U      /* 0 : No effect.                                                     */
#define LPI2C_MCFG1_ASGEN_1                    1U      /* 1 : STOP condition is automatically generated whenever the transmit
                                                     FIFO is empty and LPI2C master is busy.                            */

/* ===============================================  LPI2C MCFG1 INACK [9..9]  ================================================ */
                                  /* LPI2C_MCFG1_INACK                                                  */
#define LPI2C_MCFG1_INACK_0                    0U      /* 0 : LPI2C Master will receive ACK and NACK normally.               */
#define LPI2C_MCFG1_INACK_1                    1U      /* 1 : LPI2C Master will treat a received NACK as if it was an
                                                     ACK.                                                               */

/* ==============================================  LPI2C MCFG1 PINLTOCFG [10..10]  =============================================== */
                                   /* LPI2C_MCFG1_PINLTOCFG                                                  */
#define LPI2C_MCFG1_PINLTOCFG_0                    0U      /* 0 : Pin Low Timeout Flag will set if SCL is low for longer than
                                                     the configured timeout.                                            */
#define LPI2C_MCFG1_PINLTOCFG_1                    1U      /* 1 : Pin Low Timeout Flag will set if either SCL or SDA is low
                                                     for longer than the configured timeout.                            */

/* ==============================================  LPI2C MCFG1 MCCFG [16..18]  =============================================== */
                                   /* LPI2C_MCFG1_MCCFG                                                  */
#define LPI2C_MCFG1_MCCFG_000                  0U      /* 000 : Match disabled.                                              */
#define LPI2C_MCFG1_MCCFG_010                  2U      /* 010 : Match enabled (1st data word equals MATCH0 OR MATCH1).       */
#define LPI2C_MCFG1_MCCFG_011                  3U      /* 011 : Match enabled (any data word equals MATCH0 OR MATCH1).       */
#define LPI2C_MCFG1_MCCFG_100                  4U      /* 100 : Match enabled (1st data word equals MATCH0 AND 2nd data
                                                     word equals MATCH1).                                               */
#define LPI2C_MCFG1_MCCFG_101                  5U      /* 101 : Match enabled (any data word equals MATCH0 AND next data
                                                     word equals MATCH1).                                               */
#define LPI2C_MCFG1_MCCFG_110                  6U      /* 110 : Match enabled (1st data word AND MATCH1 equals MATCH0
                                                     AND MATCH1).                                                       */
#define LPI2C_MCFG1_MCCFG_111                  7U      /* 111 : Match enabled (any data word AND MATCH1 equals MATCH0
                                                     AND MATCH1).                                                       */

/* =============================================  LPI2C MCFG1 PINMCFG [24..26]  ============================================== */
                                   /* LPI2C_MCFG1_PINMCFG                                                */
#define LPI2C_MCFG1_PINMCFG_000                0U      /* 000 : LPI2C configured for 2-pin open drain mode.                  */
#define LPI2C_MCFG1_PINMCFG_001                1U      /* 001 : LPI2C configured for 2-pin output only mode (ultra-fast
                                                     mode).                                                             */
#define LPI2C_MCFG1_PINMCFG_010                2U      /* 010 : LPI2C configured for 2-pin push-pull mode.                   */
#define LPI2C_MCFG1_PINMCFG_011                3U      /* 011 : LPI2C configured for 4-pin push-pull mode.                   */
#define LPI2C_MCFG1_PINMCFG_100                4U      /* 100 : LPI2C configured for 2-pin open drain mode with separate
                                                     LPI2C slave.                                                       */
#define LPI2C_MCFG1_PINMCFG_101                5U      /* 101 : LPI2C configured for 2-pin output only mode (ultra-fast
                                                     mode) with separate LPI2C slave.                                   */
#define LPI2C_MCFG1_PINMCFG_110                6U      /* 110 : LPI2C configured for 2-pin push-pull mode with separate
                                                     LPI2C slave.                                                       */
#define LPI2C_MCFG1_PINMCFG_111                7U      /* 111 : LPI2C configured for 4-pin push-pull mode (inverted outputs).*/

/* =========================================================  MCFG2  ========================================================= */
/* =========================================================  MCFG3  ========================================================= */
/* ========================================================  MDATAM  ========================================================= */
/* =======================================================  MCLKCFG0  ======================================================= */
/* =======================================================  MCLKCFG1  ======================================================= */
/* ========================================================  MFCTRL  ========================================================= */
/* =========================================================  MFSTS  ========================================================= */
/* ========================================================  MTXDATA  ======================================================== */
/* ===============================================  LPI2C MTXDATA CMD [8..10]  =============================================== */
                                 /* LPI2C_MTXDATA_CMD                                                  */
#define LPI2C_MTXDATA_CMD_000                  0U      /* 000 : Transmit DATA[7:0].                                          */
#define LPI2C_MTXDATA_CMD_001                  1U      /* 001 : Receive (DATA[7:0] + 1) bytes.                               */
#define LPI2C_MTXDATA_CMD_010                  2U      /* 010 : Generate STOP condition.                                     */
#define LPI2C_MTXDATA_CMD_011                  3U      /* 011 : Receive and discard (DATA[7:0] + 1) bytes.                   */
#define LPI2C_MTXDATA_CMD_100                  4U      /* 100 : Generate (repeated) START and transmit address in DATA[7:0]. */
#define LPI2C_MTXDATA_CMD_101                  5U      /* 101 : Generate (repeated) START and transmit address in DATA[7:0].
                                                     This transfer expects a NACK to be returned.                       */
#define LPI2C_MTXDATA_CMD_110                  6U      /* 110 : Generate (repeated) START and transmit address in DATA[7:0]
                                                     using high speed mode.                                             */
#define LPI2C_MTXDATA_CMD_111                  7U      /* 111 : Generate (repeated) START and transmit address in DATA[7:0]
                                                     using high speed mode. This transfer expects a NACK to
                                                     be returned.                                                       */

/* ========================================================  MRXDATA  ======================================================== */
/* ==============================================  LPI2C MRXDATA RXFE [14..14]  ============================================== */
                                   /* LPI2C_MRXDATA_RXFE                                                 */
#define LPI2C_MRXDATA_RXFE_0                   0U      /* 0 : Receive FIFO is not empty.                                     */
#define LPI2C_MRXDATA_RXFE_1                   1U      /* 1 : Receive FIFO is empty.                                         */

/* =========================================================  SCTRL  ========================================================= */
/* ================================================  LPI2C SCTRL SMEN [0..0]  ================================================ */
                                   /* LPI2C_SCTRL_SMEN                                                   */
#define LPI2C_SCTRL_SMEN_0                     0U      /* 0 : Slave mode is disabled.                                        */
#define LPI2C_SCTRL_SMEN_1                     1U      /* 1 : Slave mode is enabled.                                         */

/* ================================================  LPI2C SCTRL SRST [1..1]  ================================================ */
                                   /* LPI2C_SCTRL_SRST                                                   */
#define LPI2C_SCTRL_SRST_0                     0U      /* 0 : Slave logic is not reset.                                      */
#define LPI2C_SCTRL_SRST_1                     1U      /* 1 : Slave logic is reset.                                          */

/* ===============================================  LPI2C SCTRL SMFEN [4..4]  ================================================ */
                                  /* LPI2C_SCTRL_SMFEN                                                  */
#define LPI2C_SCTRL_SMFEN_0                    0U      /* 0 : Disable digital filter and output delay counter for slave
                                                     mode.                                                              */
#define LPI2C_SCTRL_SMFEN_1                    1U      /* 1 : Enable digital filter and output delay counter for slave
                                                     mode.                                                              */

/* ================================================  LPI2C SCTRL FDDM [5..5]  ================================================ */
                                  /* LPI2C_SCTRL_FDDM                                                   */
#define LPI2C_SCTRL_FDDM_0                     0U      /* 0 : Filter remains enabled in Doze mode.                           */
#define LPI2C_SCTRL_FDDM_1                     1U      /* 1 : Filter is disabled in Doze mode.                               */

/* ===============================================  LPI2C SCTRL TXFRST [8..8]  =============================================== */
                                 /* LPI2C_SCTRL_TXFRST                                                 */
#define LPI2C_SCTRL_TXFRST_0                   0U      /* 0 : No effect                                                      */
#define LPI2C_SCTRL_TXFRST_1                   1U      /* 1 : Transmit Data Register is now empty                            */

/* ===============================================  LPI2C SCTRL RXFRST [9..9]  =============================================== */
                                  /* LPI2C_SCTRL_RXFRST                                                 */
#define LPI2C_SCTRL_RXFRST_0                   0U      /* 0 : No effect                                                      */
#define LPI2C_SCTRL_RXFRST_1                   1U      /* 1 : Receive Data Register is now empty                             */

/* =========================================================  SSTS  ========================================================== */
/* ===============================================  LPI2C SSTS TXFLG [0..0]  ================================================ */
                                 /* LPI2C_SSTS_TXFLG                                                  */
#define LPI2C_SSTS_TXFLG_0                    0U      /* 0 : Transmit data not requested.                                   */
#define LPI2C_SSTS_TXFLG_1                    1U      /* 1 : Transmit data is requested.                                    */

/* ===============================================  LPI2C SSTS RXFLG [1..1]  ================================================ */
                                  /* LPI2C_SSTS_RXFLG                                                  */
#define LPI2C_SSTS_RXFLG_0                    0U      /* 0 : Receive Data is not ready.                                     */
#define LPI2C_SSTS_RXFLG_1                    1U      /* 1 : Receive data is ready.                                         */

/* ================================================  LPI2C SSTS AVFLG [2..2]  ================================================ */
                                 /* LPI2C_SSTS_AVFLG                                                   */
#define LPI2C_SSTS_AVFLG_0                     0U      /* 0 : Address Status Register is not valid.                          */
#define LPI2C_SSTS_AVFLG_1                     1U      /* 1 : Address Status Register is valid.                              */

/* ================================================  LPI2C SSTS TAFLG [3..3]  ================================================ */
                                  /* LPI2C_SSTS_TAFLG                                                   */
#define LPI2C_SSTS_TAFLG_0                     0U      /* 0 : Transmit ACK/NACK is not required.                             */
#define LPI2C_SSTS_TAFLG_1                     1U      /* 1 : Transmit ACK/NACK is required.                                 */

/* ================================================  LPI2C SSTS RSFLG [8..8]  ================================================ */
                                   /* LPI2C_SSTS_RSFLG                                                   */
#define LPI2C_SSTS_RSFLG_0                     0U      /* 0 : Slave has not detected a Repeated START condition.             */
#define LPI2C_SSTS_RSFLG_1                     1U      /* 1 : Slave has detected a Repeated START condition.                 */

/* ===============================================  LPI2C SSTS STOPFLG [9..9]  =============================================== */
                                  /* LPI2C_SSTS_STOPFLG                                                 */
#define LPI2C_SSTS_STOPFLG_0                   0U      /* 0 : Slave has not detected a STOP condition.                       */
#define LPI2C_SSTS_STOPFLG_1                   1U      /* 1 : Slave has detected a STOP condition.                           */

/* ===============================================  LPI2C SSTS BEFLG [10..10]  =============================================== */
                                 /* LPI2C_SSTS_BEFLG                                                   */
#define LPI2C_SSTS_BEFLG_0                     0U      /* 0 : Slave has not detected a bit error.                            */
#define LPI2C_SSTS_BEFLG_1                     1U      /* 1 : Slave has detected a bit error.                                */

/* ===============================================  LPI2C SSTS FEFLG [11..11]  =============================================== */
                                  /* LPI2C_SSTS_FEFLG                                                   */
#define LPI2C_SSTS_FEFLG_0                     0U      /* 0 : FIFO underflow or overflow not detected.                       */
#define LPI2C_SSTS_FEFLG_1                     1U      /* 1 : FIFO underflow or overflow detected.                           */

/* ==============================================  LPI2C SSTS A0MFLG [12..12]  =============================================== */
                                  /* LPI2C_SSTS_A0MFLG                                                  */
#define LPI2C_SSTS_A0MFLG_0                    0U      /* 0 : Have not received ADDR0 matching address.                      */
#define LPI2C_SSTS_A0MFLG_1                    1U      /* 1 : Have received ADDR0 matching address.                          */

/* ==============================================  LPI2C SSTS A1MFLG [13..13]  =============================================== */
                                 /* LPI2C_SSTS_A1MFLG                                                  */
#define LPI2C_SSTS_A1MFLG_0                    0U      /* 0 : Have not received ADDR1 or ADDR0/ADDR1 range matching address. */
#define LPI2C_SSTS_A1MFLG_1                    1U      /* 1 : Have received ADDR1 or ADDR0/ADDR1 range matching address.     */

/* ==============================================  LPI2C SSTS GCAFLG [14..14]  =============================================== */
                                  /* LPI2C_SSTS_GCAFLG                                                  */
#define LPI2C_SSTS_GCAFLG_0                    0U      /* 0 : Slave has not detected the General Call Address or General
                                                     Call Address disabled.                                             */
#define LPI2C_SSTS_GCAFLG_1                    1U      /* 1 : Slave has detected the General Call Address.                   */

/* ==============================================  LPI2C SSTS SARFLG [15..15]  =============================================== */
                                  /* LPI2C_SSTS_SARFLG                                                  */
#define LPI2C_SSTS_SARFLG_0                    0U      /* 0 : SMBus Alert Response disabled or not detected.                 */
#define LPI2C_SSTS_SARFLG_1                    1U      /* 1 : SMBus Alert Response enabled and detected.                     */

/* ==============================================  LPI2C SSTS SBSYFLG [24..24]  ============================================== */
                                  /* LPI2C_SSTS_SBSYFLG                                                 */
#define LPI2C_SSTS_SBSYFLG_0                   0U      /* 0 : I2C Slave is idle.                                             */
#define LPI2C_SSTS_SBSYFLG_1                   1U      /* 1 : I2C Slave is busy.                                             */

/* ==============================================  LPI2C SSTS BBSYFLG [25..25]  ============================================== */
                                  /* LPI2C_SSTS_BBSYFLG                                                 */
#define LPI2C_SSTS_BBSYFLG_0                   0U      /* 0 : I2C Bus is idle.                                               */
#define LPI2C_SSTS_BBSYFLG_1                   1U      /* 1 : I2C Bus is busy.                                               */

/* ========================================================  SINTEN  ========================================================= */
/* ==============================================  LPI2C SINTEN TXIEN [0..0]  =============================================== */
                                  /* LPI2C_SINTEN_TXIEN                                                */
#define LPI2C_SINTEN_TXIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_TXIEN_1                  1U      /* 1 : Interrupt enabled                                              */

/* ==============================================  LPI2C SINTEN RXIEN [1..1]  =============================================== */
                                 /* LPI2C_SINTEN_RXIEN                                                */
#define LPI2C_SINTEN_RXIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_RXIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ===============================================  LPI2C SINTEN AVIEN [2..2]  =============================================== */
                                  /* LPI2C_SINTEN_AVIEN                                                 */
#define LPI2C_SINTEN_AVIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_AVIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* ===============================================  LPI2C SINTEN TAIEN [3..3]  =============================================== */
                                  /* LPI2C_SINTEN_TAIEN                                                 */
#define LPI2C_SINTEN_TAIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_TAIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* ===============================================  LPI2C SINTEN RSIEN [8..8]  =============================================== */
                                 /* LPI2C_SINTEN_RSIEN                                                 */
#define LPI2C_SINTEN_RSIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_RSIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C SINTEN STOPIEN [9..9]  ============================================== */
                                  /* LPI2C_SINTEN_STOPIEN                                               */
#define LPI2C_SINTEN_STOPIEN_0                 0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_STOPIEN_1                 1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C SINTEN BEIEN [10..10]  ============================================== */
                                  /* LPI2C_SINTEN_BEIEN                                                 */
#define LPI2C_SINTEN_BEIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_BEIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* ==============================================  LPI2C SINTEN FEIEN [11..11]  ============================================== */
                                 /* LPI2C_SINTEN_FEIEN                                                 */
#define LPI2C_SINTEN_FEIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_FEIEN_1                   1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C SINTEN A0MIEN [12..12]  ============================================== */
                                  /* LPI2C_SINTEN_A0MIEN                                                */
#define LPI2C_SINTEN_A0MIEN_0                  0U      /* 0 : Interrupt enabled.                                             */
#define LPI2C_SINTEN_A0MIEN_1                  1U      /* 1 : Interrupt disabled.                                            */

/* =============================================  LPI2C SINTEN A1MIEN [13..13]  ============================================== */
                                  /* LPI2C_SINTEN_A1MIEN                                                */
#define LPI2C_SINTEN_A1MIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_A1MIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C SINTEN GCAIEN [14..14]  ============================================== */
                                   /* LPI2C_SINTEN_GCAIEN                                                */
#define LPI2C_SINTEN_GCAIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_GCAIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* =============================================  LPI2C SINTEN SARIEN [15..15]  ============================================== */
                                 /* LPI2C_SINTEN_SARIEN                                                */
#define LPI2C_SINTEN_SARIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define LPI2C_SINTEN_SARIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ========================================================  SDMAEN  ========================================================= */
/* ==============================================  LPI2C SDMAEN TXDMAEN [0..0]  ============================================== */
                                  /* LPI2C_SDMAEN_TXDMAEN                                               */
#define LPI2C_SDMAEN_TXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPI2C_SDMAEN_TXDMAEN_1                 1U      /* 1 : DMA request enabled                                            */

/* ==============================================  LPI2C SDMAEN RXDMAEN [1..1]  ============================================== */
                                 /* LPI2C_SDMAEN_RXDMAEN                                               */
#define LPI2C_SDMAEN_RXDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPI2C_SDMAEN_RXDMAEN_1                 1U      /* 1 : DMA request enabled.                                           */

/* ==============================================  LPI2C SDMAEN AVDMAEN [2..2]  ============================================== */
                                   /* LPI2C_SDMAEN_AVDMAEN                                               */
#define LPI2C_SDMAEN_AVDMAEN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPI2C_SDMAEN_AVDMAEN_1                 1U      /* 1 : DMA request enabled.                                           */


/* =========================================================  SCFG1  ========================================================= */
/* ==============================================  LPI2C SCFG1 ADDRSEN [0..0]  =============================================== */
                                  /* LPI2C_SCFG1_ADDRSEN                                                */
#define LPI2C_SCFG1_ADDRSEN_0                  0U      /* 0 : Clock stretching disabled.                                     */
#define LPI2C_SCFG1_ADDRSEN_1                  1U      /* 1 : Clock stretching enabled.                                      */

/* ===============================================  LPI2C SCFG1 RXDSEN [1..1]  =============================================== */
                                   /* LPI2C_SCFG1_RXDSEN                                                 */
#define LPI2C_SCFG1_RXDSEN_0                   0U      /* 0 : Clock stretching disabled.                                     */
#define LPI2C_SCFG1_RXDSEN_1                   1U      /* 1 : Clock stretching enabled.                                      */


/* ===============================================  LPI2C SCFG1 TXDSEN [2..2]  =============================================== */
                                  /* LPI2C_SCFG1_TXDSEN                                                 */
#define LPI2C_SCFG1_TXDSEN_0                   0U      /* 0 : Clock stretching disabled.                                     */
#define LPI2C_SCFG1_TXDSEN_1                   1U      /* 1 : Clock stretching enabled.                                      */

/* ===============================================  LPI2C SCFG1 ACKSEN [3..3]  =============================================== */
                                  /* LPI2C_SCFG1_ACKSEN                                                 */
#define LPI2C_SCFG1_ACKSEN_0                   0U      /* 0 : Clock stretching disabled.                                     */
#define LPI2C_SCFG1_ACKSEN_1                   1U      /* 1 : Clock stretching enabled.                                      */

/* ===============================================  LPI2C SCFG1 GCAEN [8..8]  ================================================ */
                                  /* LPI2C_SCFG1_GCAEN                                                  */
#define LPI2C_SCFG1_GCAEN_0                    0U      /* 0 : General Call address is disabled.                              */
#define LPI2C_SCFG1_GCAEN_1                    1U      /* 1 : General call address is enabled.                               */

/* ===============================================  LPI2C SCFG1 SAMEN [9..9]  ================================================ */
                                  /* LPI2C_SCFG1_SAMEN                                                  */
#define LPI2C_SCFG1_SAMEN_0                    0U      /* 0 : Disables match on SMBus Alert.                                 */
#define LPI2C_SCFG1_SAMEN_1                    1U      /* 1 : Enables match on SMBus Alert.                                  */

/* =============================================  LPI2C SCFG1 TXFCFG [10..10]  ============================================== */
                                   /* LPI2C_SCFG1_TXFCFG                                                */
#define LPI2C_SCFG1_TXFCFG_0                  0U      /* 0 : Transmit Data Flag will only assert during a slave-transmit
                                                     transfer when the transmit data register is empty.                 */
#define LPI2C_SCFG1_TXFCFG_1                  1U      /* 1 : Transmit Data Flag will assert whenever the transmit data
                                                     register is empty.                                                 */

/* =============================================  LPI2C SCFG1 RXFCFG [11..11]  ============================================== */
                                   /* LPI2C_SCFG1_RXFCFG                                                */
#define LPI2C_SCFG1_RXFCFG_0                  0U      /* 0 : Reading the receive data register will return receive data
                                                     and clear the receive data flag.                                   */
#define LPI2C_SCFG1_RXFCFG_1                  1U      /* 1 : Reading the Receive Data register when the Address Valid
                                                     flag (SSR[AVF])is set  will return the Address Status register
                                                     and clear the Address Valid flag. Reading the Receive Data
                                                     register when the Address Valid flag is clear  will return
                                                     received data and clear the Receive Data flag (MSR[RDF]).          */

/* ==============================================  LPI2C SCFG1 INACK [12..12]  =============================================== */
                                  /* LPI2C_SCFG1_INACK                                                  */
#define LPI2C_SCFG1_INACK_0                    0U      /* 0 : Slave will end transfer when NACK detected.                    */
#define LPI2C_SCFG1_INACK_1                    1U      /* 1 : Slave will not end transfer when NACK detected.                */

/* ==============================================  LPI2C SCFG1 HSMDEN [13..13]  ============================================== */
                                  /* LPI2C_SCFG1_HSMDEN                                                 */
#define LPI2C_SCFG1_HSMDEN_0                   0U      /* 0 : Disables detection of Hs-mode master code.                     */
#define LPI2C_SCFG1_HSMDEN_1                   1U      /* 1 : Enables detection of Hs-mode master code.                      */

/* ==============================================  LPI2C SCFG1 ADDRMCFG [16..18]  =============================================== */
                                   /* LPI2C_SCFG1_ADDRMCFG                                                  */
#define LPI2C_SCFG1_ADDRMCFG_000                  0U      /* 000 : Address match 0 (7-bit).                                     */
#define LPI2C_SCFG1_ADDRMCFG_001                  1U      /* 001 : Address match 0 (10-bit).                                    */
#define LPI2C_SCFG1_ADDRMCFG_010                  2U      /* 010 : Address match 0 (7-bit) or Address match 1 (7-bit).          */
#define LPI2C_SCFG1_ADDRMCFG_011                  3U      /* 011 : Address match 0 (10-bit) or Address match 1 (10-bit).        */
#define LPI2C_SCFG1_ADDRMCFG_100                  4U      /* 100 : Address match 0 (7-bit) or Address match 1 (10-bit).         */
#define LPI2C_SCFG1_ADDRMCFG_101                  5U      /* 101 : Address match 0 (10-bit) or Address match 1 (7-bit).         */
#define LPI2C_SCFG1_ADDRMCFG_110                  6U      /* 110 : From Address match 0 (7-bit) to Address match 1 (7-bit).     */
#define LPI2C_SCFG1_ADDRMCFG_111                  7U      /* 111 : From Address match 0 (10-bit) to Address match 1 (10-bit).   */


/* =========================================================  SCFG2  ========================================================= */
/* ========================================================  SADDRM  ========================================================= */
/* =======================================================  SADDRSTS  ======================================================== */
/* ===========================================  LPI2C SADDRSTS RXADDRNV [14..14]  ============================================ */
                                  /* LPI2C_SADDRSTS_RXADDRNV                                            */
#define LPI2C_SADDRSTS_RXADDRNV_0              0U      /* 0 : RADDR is valid.                                                */
#define LPI2C_SADDRSTS_RXADDRNV_1              1U      /* 1 : RADDR is not valid.                                            */

/* ========================================================  STXACK  ========================================================= */
/* ==============================================  LPI2C STXACK TXNACK [0..0]  =============================================== */
                                  /* LPI2C_STXACK_TXNACK                                                */
#define LPI2C_STXACK_TXNACK_0                  0U      /* 0 : Transmit ACK for received word.                                */
#define LPI2C_STXACK_TXNACK_1                  1U      /* 1 : Transmit NACK for received word.                               */

/* ========================================================  STXDATA  ======================================================== */
/* ========================================================  SRXDATA  ======================================================== */
/* ==============================================  LPI2C SRXDATA RXDE [14..14]  ============================================== */
                                  /* LPI2C_SRXDATA_RXDE                                                 */
#define LPI2C_SRXDATA_RXDE_0                   0U      /* 0 : The Receive Data Register is not empty.                        */
#define LPI2C_SRXDATA_RXDE_1                   1U      /* 1 : The Receive Data Register is empty.                            */

/* ==============================================  LPI2C SRXDATA FDW [15..15]  =============================================== */
                                  /* LPI2C_SRXDATA_FDW                                                  */
#define LPI2C_SRXDATA_FDW_0                    0U      /* 0 : Indicates this is not the first data word since a (repeated)
                                                     START or STOP condition.                                           */
#define LPI2C_SRXDATA_FDW_1                    1U      /* 1 : Indicates this is the first data word since a (repeated)
                                                     START or STOP condition.                                           */



/* =========================================================================================================================== */
/* ================                                          LPUART                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* =============================================  LPUART VERID FEATURE [0..15]  ============================================= */
                                 /* LPUART_VERID_FEATURE                                              */
#define LPUART_VERID_FEATURE_0000000000000001   1U    /* 0000000000000001 : Standard feature set.                           */
#define LPUART_VERID_FEATURE_0000000000000011   3U    /* 0000000000000011 : Standard feature set with MODEM/IrDA support.   */

/* =========================================================  PARA  ========================================================= */
/* ==========================================================  SWRST  ========================================================== */
/* ==============================================  LPUART SWRST SWRSTEN [1..1]  =============================================== */
                                 /* LPUART_SWRST_SWRSTEN                                                */
#define LPUART_SWRST_SWRSTEN_0                  0U      /* 0 : Module is not reset.                                           */
#define LPUART_SWRST_SWRSTEN_1                  1U      /* 1 : Module is reset.                                               */


/* =========================================================  PCFG  ========================================================== */
/* ==============================================  LPUART PCFG ITRGCFG [0..1]  ============================================== */
                                  /* LPUART_PCFG_ITRGCFG                                               */
#define LPUART_PCFG_ITRGCFG_00                0U      /* 00 : Input trigger is disabled.                                    */
#define LPUART_PCFG_ITRGCFG_01                1U      /* 01 : Input trigger is used instead of RXD pin input.               */
#define LPUART_PCFG_ITRGCFG_10                2U      /* 10 : Input trigger is used instead of CTS_B pin input.             */
#define LPUART_PCFG_ITRGCFG_11                3U      /* 11 : Input trigger is used to modulate the TXD pin output. The
                                                     TXD pin output (after TXINV configuration) is ANDed with
                                                     the input trigger.                                                 */


/* ==========================================================  BR  =========================================================== */
/* =============================================  LPUART BR STOPBSEL [13..13]  ============================================== */
                                  /* LPUART_BR_STOPBSEL                                                */
#define LPUART_BR_STOPBSEL_0                  0U      /* 0 : One stop bit.                                                  */
#define LPUART_BR_STOPBSEL_1                  1U      /* 1 : Two stop bits.                                                 */


/* =============================================  LPUART BR RXIAEIEN [14..14]  ============================================== */
                                  /* LPUART_BR_RXIAEIEN                                                */
#define LPUART_BR_RXIAEIEN_0                  0U      /* 0 : Hardware interrupts from LPUART_STAT[RXEDGIF] disabled.        */
#define LPUART_BR_RXIAEIEN_1                  1U      /* 1 : Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag
                                                     is 1.                                                              */


/* ==============================================  LPUART BR LBDFIEN [15..15]  ============================================== */
                                  /* LPUART_BR_LBDFIEN                                                 */
#define LPUART_BR_LBDFIEN_0                   0U      /* 0 : Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use
                                                     polling).                                                          */
#define LPUART_BR_LBDFIEN_1                   1U      /* 1 : Hardware interrupt requested when LPUART_STAT[LBKDIF] flag
                                                     is 1.                                                              */


/* =============================================  LPUART BR RXDWRDIS [16..16]  ============================================== */
                                  /* LPUART_BR_RXDWRDIS                                                */
#define LPUART_BR_RXDWRDIS_0                  0U      /* 0 : Resynchronization during received data word is supported       */
#define LPUART_BR_RXDWRDIS_1                  1U      /* 1 : Resynchronization during received data word is disabled        */


/* =============================================  LPUART BR BEDSMPSEL [17..17]  ============================================= */
                                  /* LPUART_BR_BEDSMPSEL                                               */
#define LPUART_BR_BEDSMPSEL_0                 0U      /* 0 : Receiver samples input data using the rising edge of the
                                                     baud rate clock.                                                   */
#define LPUART_BR_BEDSMPSEL_1                 1U      /* 1 : Receiver samples input data using the rising and falling
                                                     edge of the baud rate clock.                                       */


/* =============================================  LPUART BR MADDRMCFG [18..19]  ============================================= */
                                  /* LPUART_BR_MADDRMCFG                                               */
#define LPUART_BR_MADDRMCFG_00                0U      /* 00 : Address Match Wakeup                                          */
#define LPUART_BR_MADDRMCFG_01                1U      /* 01 : Idle Match Wakeup                                             */
#define LPUART_BR_MADDRMCFG_10                2U      /* 10 : Match On and Match Off                                        */

/* =============================================  LPUART BR RXIDMAREN [20..20]  ============================================= */
                                   /* LPUART_BR_RXIDMAREN                                               */
#define LPUART_BR_RXIDMAREN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPUART_BR_RXIDMAREN_1                 1U      /* 1 : DMA request enabled.                                           */

/* =============================================  LPUART BR RXFDMAREN [21..21]  ============================================= */
                                  /* LPUART_BR_RXFDMAREN                                               */
#define LPUART_BR_RXFDMAREN_0                 0U      /* 0 : DMA request disabled.                                          */
#define LPUART_BR_RXFDMAREN_1                 1U      /* 1 : DMA request enabled.                                           */


/* =============================================  LPUART BR TXDMAREN [23..23]  ============================================== */
                                  /* LPUART_BR_TXDMAREN                                                */
#define LPUART_BR_TXDMAREN_0                  0U      /* 0 : DMA request disabled.                                          */
#define LPUART_BR_TXDMAREN_1                  1U      /* 1 : DMA request enabled.                                           */


/* ==============================================  LPUART BR OSRCFG [24..28]  =============================================== */
                                  /* LPUART_BR_OSRCFG                                                  */
#define LPUART_BR_OSRCFG_00000                0U      /* 00000 : Writing 0 to this field will result in an oversampling
                                                     ratio of 16                                                        */
#define LPUART_BR_OSRCFG_00011                3U      /* 00011 : Oversampling ratio of 4  requires BOTHEDGE to be set.      */
#define LPUART_BR_OSRCFG_00100                4U      /* 00100 : Oversampling ratio of 5  requires BOTHEDGE to be set.      */
#define LPUART_BR_OSRCFG_00101                5U      /* 00101 : Oversampling ratio of 6  requires BOTHEDGE to be set.      */
#define LPUART_BR_OSRCFG_00110                6U      /* 00110 : Oversampling ratio of 7  requires BOTHEDGE to be set.      */
#define LPUART_BR_OSRCFG_00111                7U      /* 00111 : Oversampling ratio of 8.                                   */
#define LPUART_BR_OSRCFG_01000                8U      /* 01000 : Oversampling ratio of 9.                                   */
#define LPUART_BR_OSRCFG_01001                9U      /* 01001 : Oversampling ratio of 10.                                  */
#define LPUART_BR_OSRCFG_01010                10U     /* 01010 : Oversampling ratio of 11.                                  */
#define LPUART_BR_OSRCFG_01011                11U     /* 01011 : Oversampling ratio of 12.                                  */
#define LPUART_BR_OSRCFG_01100                12U     /* 01100 : Oversampling ratio of 13.                                  */
#define LPUART_BR_OSRCFG_01101                13U     /* 01101 : Oversampling ratio of 14.                                  */
#define LPUART_BR_OSRCFG_01110                14U     /* 01110 : Oversampling ratio of 15.                                  */
#define LPUART_BR_OSRCFG_01111                15U     /* 01111 : Oversampling ratio of 16.                                  */
#define LPUART_BR_OSRCFG_10000                16U     /* 10000 : Oversampling ratio of 17.                                  */
#define LPUART_BR_OSRCFG_10001                17U     /* 10001 : Oversampling ratio of 18.                                  */
#define LPUART_BR_OSRCFG_10010                18U     /* 10010 : Oversampling ratio of 19.                                  */
#define LPUART_BR_OSRCFG_10011                19U     /* 10011 : Oversampling ratio of 20.                                  */
#define LPUART_BR_OSRCFG_10100                20U     /* 10100 : Oversampling ratio of 21.                                  */
#define LPUART_BR_OSRCFG_10101                21U     /* 10101 : Oversampling ratio of 22.                                  */
#define LPUART_BR_OSRCFG_10110                22U     /* 10110 : Oversampling ratio of 23.                                  */
#define LPUART_BR_OSRCFG_10111                23U     /* 10111 : Oversampling ratio of 24.                                  */
#define LPUART_BR_OSRCFG_11000                24U     /* 11000 : Oversampling ratio of 25.                                  */
#define LPUART_BR_OSRCFG_11001                25U     /* 11001 : Oversampling ratio of 26.                                  */
#define LPUART_BR_OSRCFG_11010                26U     /* 11010 : Oversampling ratio of 27.                                  */
#define LPUART_BR_OSRCFG_11011                27U     /* 11011 : Oversampling ratio of 28.                                  */
#define LPUART_BR_OSRCFG_11100                28U     /* 11100 : Oversampling ratio of 29.                                  */
#define LPUART_BR_OSRCFG_11101                29U     /* 11101 : Oversampling ratio of 30.                                  */
#define LPUART_BR_OSRCFG_11110                30U     /* 11110 : Oversampling ratio of 31.                                  */
#define LPUART_BR_OSRCFG_11111                31U     /* 11111 : Oversampling ratio of 32.                                  */


/* ==============================================  LPUART BR SELM10 [29..29]  =============================================== */
                                   /* LPUART_BR_SELM10                                                  */
#define LPUART_BR_SELM10_0                    0U      /* 0 : Receiver and transmitter use 7-bit to 9-bit data characters.   */
#define LPUART_BR_SELM10_1                    1U      /* 1 : Receiver and transmitter use 10-bit data characters.           */

/* =============================================  LPUART BR MADDREN2 [30..30]  ============================================== */
                                   /* LPUART_BR_MADDREN2                                                */
#define LPUART_BR_MADDREN2_0                  0U      /* 0 : Normal operation.                                              */
#define LPUART_BR_MADDREN2_1                  1U      /* 1 : Enables automatic address matching or data matching mode
                                                     for MATCH[MA2].                                                    */

/* =============================================  LPUART BR MADDREN1 [31..31]  ============================================== */
                                  /* LPUART_BR_MADDREN1                                                */
#define LPUART_BR_MADDREN1_0                  0U      /* 0 : Normal operation.                                              */
#define LPUART_BR_MADDREN1_1                  1U      /* 1 : Enables automatic address matching or data matching mode
                                                     for MATCH[MA1].                                                    */

/* ==========================================================  STS  ========================================================== */
/* =============================================  LPUART STS RXDMFLG2 [14..14]  ============================================= */
                                  /* LPUART_STS_RXDMFLG2                                               */
#define LPUART_STS_RXDMFLG2_0                 0U      /* 0 : Received data is not equal to MA2                              */
#define LPUART_STS_RXDMFLG2_1                 1U      /* 1 : Received data is equal to MA2                                  */

/* =============================================  LPUART STS RXDMFLG1 [15..15]  ============================================= */
                                  /* LPUART_STS_RXDMFLG1                                               */
#define LPUART_STS_RXDMFLG1_0                 0U      /* 0 : Received data is not equal to MA1                              */
#define LPUART_STS_RXDMFLG1_1                 1U      /* 1 : Received data is equal to MA1                                  */

/* ==============================================  LPUART STS PEFLG [16..16]  =============================================== */
                                  /* LPUART_STS_PEFLG                                                  */
#define LPUART_STS_PEFLG_0                    0U      /* 0 : No parity error.                                               */
#define LPUART_STS_PEFLG_1                    1U      /* 1 : Parity error.                                                  */

/* ==============================================  LPUART STS FEFLG [17..17]  =============================================== */
                                  /* LPUART_STS_FEFLG                                                  */
#define LPUART_STS_FEFLG_0                    0U      /* 0 : No framing error detected. This does not guarantee the framing
                                                     is correct.                                                        */
#define LPUART_STS_FEFLG_1                    1U      /* 1 : Framing error.                                                 */

/* ==============================================  LPUART STS NEFLG [18..18]  =============================================== */
                                  /* LPUART_STS_NEFLG                                                  */
#define LPUART_STS_NEFLG_0                    0U      /* 0 : No noise detected.                                             */
#define LPUART_STS_NEFLG_1                    1U      /* 1 : Noise detected in the received character in LPUART_DATA.       */

/* =============================================  LPUART STS OVREFLG [19..19]  ============================================== */
                                   /* LPUART_STS_OVREFLG                                                */
#define LPUART_STS_OVREFLG_0                  0U      /* 0 : No overrun.                                                    */
#define LPUART_STS_OVREFLG_1                  1U      /* 1 : Receive overrun (new LPUART data lost).                        */


/* =============================================  LPUART STS IDLEFLG [20..20]  ============================================== */
                                  /* LPUART_STS_IDLEFLG                                                */
#define LPUART_STS_IDLEFLG_0                  0U      /* 0 : No idle line detected.                                         */
#define LPUART_STS_IDLEFLG_1                  1U      /* 1 : Idle line was detected.                                        */

/* =============================================  LPUART STS RXBFFLG [21..21]  ============================================== */
                                  /* LPUART_STS_RXBFFLG                                                */
#define LPUART_STS_RXBFFLG_0                  0U      /* 0 : Receive data buffer empty.                                     */
#define LPUART_STS_RXBFFLG_1                  1U      /* 1 : Receive data buffer full.                                      */

/* ==============================================  LPUART STS TXCFLG [22..22]  ============================================== */
                                  /* LPUART_STS_TXCFLG                                                 */
#define LPUART_STS_TXCFLG_0                   0U      /* 0 : Transmitter active (sending data  a preamble  or a break).     */
#define LPUART_STS_TXCFLG_1                   1U      /* 1 : Transmitter idle (transmission activity complete).             */

/* =============================================  LPUART STS TXBEFLG [23..23]  ============================================== */
                                  /* LPUART_STS_TXBEFLG                                                */
#define LPUART_STS_TXBEFLG_0                  0U      /* 0 : Transmit data buffer full.                                     */
#define LPUART_STS_TXBEFLG_1                  1U      /* 1 : Transmit data buffer empty.                                    */

/* ============================================  LPUART STS RXDINIFLG [24..24]  ============================================= */
                                 /* LPUART_STS_RXDINIFLG                                              */
#define LPUART_STS_RXDINIFLG_0                0U      /* 0 : LPUART receiver idle waiting for a start bit.                  */
#define LPUART_STS_RXDINIFLG_1                1U      /* 1 : LPUART receiver active (RXD input not idle).                   */

/* ==============================================  LPUART STS LBDEN [25..25]  =============================================== */
                                  /* LPUART_STS_LBDEN                                                  */
#define LPUART_STS_LBDEN_0                    0U      /* 0 : LIN break detect is disabled  normal break character can
                                                     be detected.                                                       */
#define LPUART_STS_LBDEN_1                    1U      /* 1 : LIN break detect is enabled. LIN break character is detected
                                                     at length of 11 bit times (if M = 0) or 12 (if M = 1) or
                                                     13 (M10 = 1).                                                      */


/* =============================================  LPUART STS BCTXLEN [26..26]  ============================================== */
                                  /* LPUART_STS_BCTXLEN                                                */
#define LPUART_STS_BCTXLEN_0                  0U      /* 0 : Break character is transmitted with length of 9 to 13 bit
                                                     times.                                                             */
#define LPUART_STS_BCTXLEN_1                  1U      /* 1 : Break character is transmitted with length of 12 to 15 bit
                                                     times.                                                             */


/* =============================================  LPUART STS RXWUPID [27..27]  ============================================== */
                                 /* LPUART_STS_RXWUPID                                                */
#define LPUART_STS_RXWUPID_0                  0U      /* 0 : During receive standby state (RWU = 1)  the IDLE bit does
                                                     not get set upon detection of an idle character. During
                                                     address match wakeup  the IDLE bit does not set when an
                                                     address does not match.                                            */
#define LPUART_STS_RXWUPID_1                  1U      /* 1 : During receive standby state (RWU = 1)  the IDLE bit gets
                                                     set upon detection of an idle character. During address
                                                     match wakeup  the IDLE bit does set when an address does
                                                     not match.                                                         */


/* =============================================  LPUART STS RXDIPINV [28..28]  ============================================= */
                                  /* LPUART_STS_RXDIPINV                                               */
#define LPUART_STS_RXDIPINV_0                 0U      /* 0 : Receive data not inverted.                                     */
#define LPUART_STS_RXDIPINV_1                 1U      /* 1 : Receive data inverted.                                         */


/* =============================================  LPUART STS MSBFSET [29..29]  ============================================== */
                                 /* LPUART_STS_MSBFSET                                                */
#define LPUART_STS_MSBFSET_0                  0U      /* 0 : LSB (bit0) is the first bit that is transmitted following
                                                     the start bit. Further  the first bit received after the
                                                     start bit is identified as bit0.                                   */
#define LPUART_STS_MSBFSET_1                  1U      /* 1 : MSB (bit9  bit8  bit7 or bit6) is the first bit that is
                                                     transmitted following the start bit depending on the setting
                                                     of CTRL[M]  CTRL[PE] and BAUD[M10]. Further  the first
                                                     bit received after the start bit is identified as bit9
                                                     bit8  bit7 or bit6 depending on the setting of CTRL[M]
                                                     and CTRL[PE].                                                      */


/* =============================================  LPUART STS AERXPFLG [30..30]  ============================================= */
                                 /* LPUART_STS_AERXPFLG                                               */
#define LPUART_STS_AERXPFLG_0                 0U      /* 0 : No active edge on the receive pin has occurred.                */
#define LPUART_STS_AERXPFLG_1                 1U      /* 1 : An active edge on the receive pin has occurred.                */


/* ==============================================  LPUART STS LBDFLG [31..31]  ============================================== */
                                 /* LPUART_STS_LBDFLG                                                 */
#define LPUART_STS_LBDFLG_0                   0U      /* 0 : No LIN break character has been detected.                      */
#define LPUART_STS_LBDFLG_1                   1U      /* 1 : LIN break character has been detected.                         */


/* =========================================================  CTRL  ========================================================== */
/* ===============================================  LPUART CTRL PTCFG [0..0]  =============================================== */
                                   /* LPUART_CTRL_PTCFG                                                 */
#define LPUART_CTRL_PTCFG_0                   0U      /* 0 : Even parity.                                                   */
#define LPUART_CTRL_PTCFG_1                   1U      /* 1 : Odd parity.                                                    */


/* ===============================================  LPUART CTRL PENCFG [1..1]  =============================================== */
                                 /* LPUART_CTRL_PECFG                                                 */
#define LPUART_CTRL_PENCFG_0                   0U      /* 0 : No hardware parity generation or checking.                     */
#define LPUART_CTRL_PENCFG_1                   1U      /* 1 : Parity enabled.                                                */


/* ===============================================  LPUART CTRL ITSEL [2..2]  =============================================== */
                                 /* LPUART_CTRL_ITSEL                                                 */
#define LPUART_CTRL_ITSEL_0                   0U      /* 0 : Idle character bit count starts after start bit.               */
#define LPUART_CTRL_ITSEL_1                   1U      /* 1 : Idle character bit count starts after stop bit.                */


/* =============================================  LPUART CTRL RXWAKESEL [3..3]  ============================================= */
                                 /* LPUART_CTRL_RXWAKESEL                                             */
#define LPUART_CTRL_RXWAKESEL_0               0U      /* 0 : Configures RWU for idle-line wakeup.                           */
#define LPUART_CTRL_RXWAKESEL_1               1U      /* 1 : Configures RWU with address-mark wakeup.                       */


/* =============================================  LPUART CTRL RXTXCSEL [4..4]  ============================================== */
                                  /* LPUART_CTRL_RXTXCSEL                                              */
#define LPUART_CTRL_RXTXCSEL_0                0U      /* 0 : Receiver and transmitter use 8-bit data characters.            */
#define LPUART_CTRL_RXTXCSEL_1                1U      /* 1 : Receiver and transmitter use 9-bit data characters.            */


/* =============================================  LPUART CTRL RXISRCSEL [5..5]  ============================================= */
                                  /* LPUART_CTRL_RXISRCSEL                                             */
#define LPUART_CTRL_RXISRCSEL_0               0U      /* 0 : Provided LOOPS is set  RSRC is cleared  selects internal
                                                     loop back mode and the LPUART does not use the RXD pin.            */
#define LPUART_CTRL_RXISRCSEL_1               1U      /* 1 : Single-wire LPUART mode where the TXD pin is connected to
                                                     the transmitter output and receiver input.                         */


/* ============================================  LPUART CTRL DOZEMODEEN [6..6]  ============================================= */
                                  /* LPUART_CTRL_DOZEMODEEN                                            */
#define LPUART_CTRL_DOZEMODEEN_0              0U      /* 0 : LPUART is enabled in Doze mode.                                */
#define LPUART_CTRL_DOZEMODEEN_1              1U      /* 1 : LPUART is disabled in Doze mode.                               */


/* ==============================================  LPUART CTRL LSWSEL [7..7]  =============================================== */
                                   /* LPUART_CTRL_LSWSEL                                                */
#define LPUART_CTRL_LSWSEL_0                  0U      /* 0 : Normal operation - RXD and TXD use separate pins.              */
#define LPUART_CTRL_LSWSEL_1                  1U      /* 1 : Loop mode or single-wire mode where transmitter outputs
                                                     are internally connected to receiver input (see RSRC bit).         */


/* =============================================  LPUART CTRL IDLECCFG [8..10]  ============================================= */
                                   /* LPUART_CTRL_IDLECCFG                                              */
#define LPUART_CTRL_IDLECCFG_000              0U      /* 000 : 1 idle character                                             */
#define LPUART_CTRL_IDLECCFG_001              1U      /* 001 : 2 idle characters                                            */
#define LPUART_CTRL_IDLECCFG_010              2U      /* 010 : 4 idle characters                                            */
#define LPUART_CTRL_IDLECCFG_011              3U      /* 011 : 8 idle characters                                            */
#define LPUART_CTRL_IDLECCFG_100              4U      /* 100 : 16 idle characters                                           */
#define LPUART_CTRL_IDLECCFG_101              5U      /* 101 : 32 idle characters                                           */
#define LPUART_CTRL_IDLECCFG_110              6U      /* 110 : 64 idle characters                                           */
#define LPUART_CTRL_IDLECCFG_111              7U      /* 111 : 128 idle characters                                          */


/* ============================================  LPUART CTRL RXTXSELM7 [11..11]  ============================================ */
                                  /* LPUART_CTRL_RXTXSELM7                                             */
#define LPUART_CTRL_RXTXSELM7_0               0U      /* 0 : Receiver and transmitter use 8-bit to 10-bit data characters.  */
#define LPUART_CTRL_RXTXSELM7_1               1U      /* 1 : Receiver and transmitter use 7-bit data characters.            */


/* =============================================  LPUART CTRL FIENM2 [14..14]  ============================================== */
                                  /* LPUART_CTRL_FIENM2                                                */
#define LPUART_CTRL_FIENM2_0                  0U      /* 0 : MA2F interrupt disabled                                        */
#define LPUART_CTRL_FIENM2_1                  1U      /* 1 : MA2F interrupt enabled                                         */


/* =============================================  LPUART CTRL FIENM1 [15..15]  ============================================== */
                                   /* LPUART_CTRL_FIENM1                                                */
#define LPUART_CTRL_FIENM1_0                  0U      /* 0 : MA1F interrupt disabled                                        */
#define LPUART_CTRL_FIENM1_1                  1U      /* 1 : MA1F interrupt enabled                                         */


/* ==============================================  LPUART CTRL TXBK [16..16]  =============================================== */
                                  /* LPUART_CTRL_TXBK                                                  */
#define LPUART_CTRL_TXBK_0                    0U      /* 0 : Normal transmitter operation.                                  */
#define LPUART_CTRL_TXBK_1                    1U      /* 1 : Queue break character(s) to be sent.                           */


/* ============================================  LPUART CTRL RXWUPCTRL [17..17]  ============================================ */
                                /* LPUART_CTRL_RXWUPCTRL                                             */
#define LPUART_CTRL_RXWUPCTRL_0               0U      /* 0 : Normal receiver operation.                                     */
#define LPUART_CTRL_RXWUPCTRL_1               1U      /* 1 : LPUART receiver in standby waiting for wakeup condition.       */


/* ==============================================  LPUART CTRL RXEN [18..18]  =============================================== */
                                 /* LPUART_CTRL_RXEN                                                  */
#define LPUART_CTRL_RXEN_0                    0U      /* 0 : Receiver disabled.                                             */
#define LPUART_CTRL_RXEN_1                    1U      /* 1 : Receiver enabled.                                              */


/* ==============================================  LPUART CTRL TXEN [19..19]  =============================================== */
                                /* LPUART_CTRL_TXEN                                                  */
#define LPUART_CTRL_TXEN_0                    0U      /* 0 : Transmitter disabled.                                          */
#define LPUART_CTRL_TXEN_1                    1U      /* 1 : Transmitter enabled.                                           */


/* =============================================  LPUART CTRL IDLEIEN [20..20]  ============================================= */
                                   /* LPUART_CTRL_IDLEIEN                                               */
#define LPUART_CTRL_IDLEIEN_0                 0U      /* 0 : Hardware interrupts from IDLE disabled; use polling.           */
#define LPUART_CTRL_IDLEIEN_1                 1U      /* 1 : Hardware interrupt requested when IDLE flag is 1.              */


/* ==============================================  LPUART CTRL RXIEN [21..21]  ============================================== */
                                  /* LPUART_CTRL_RXIEN                                                 */
#define LPUART_CTRL_RXIEN_0                   0U      /* 0 : Hardware interrupts from RDRF disabled; use polling.           */
#define LPUART_CTRL_RXIEN_1                   1U      /* 1 : Hardware interrupt requested when RDRF flag is 1.              */


/* =============================================  LPUART CTRL TXCIEN [22..22]  ============================================== */
                                  /* LPUART_CTRL_TXCIEN                                                */
#define LPUART_CTRL_TXCIEN_0                  0U      /* 0 : Hardware interrupts from TC disabled; use polling.             */
#define LPUART_CTRL_TXCIEN_1                  1U      /* 1 : Hardware interrupt requested when TC flag is 1.                */

/* ==============================================  LPUART CTRL TXIEN [23..23]  ============================================== */
                                  /* LPUART_CTRL_TXIEN                                                 */
#define LPUART_CTRL_TXIEN_0                   0U      /* 0 : Hardware interrupts from TDRE disabled; use polling.           */
#define LPUART_CTRL_TXIEN_1                   1U      /* 1 : Hardware interrupt requested when TDRE flag is 1.              */


/* ==============================================  LPUART CTRL PEIEN [24..24]  ============================================== */
                                 /* LPUART_CTRL_PEIEN                                                 */
#define LPUART_CTRL_PEIEN_0                   0U      /* 0 : PF interrupts disabled; use polling).                          */
#define LPUART_CTRL_PEIEN_1                   1U      /* 1 : Hardware interrupt requested when PF is set.                   */


/* ==============================================  LPUART CTRL FEIEN [25..25]  ============================================== */
                                   /* LPUART_CTRL_FEIEN                                                 */
#define LPUART_CTRL_FEIEN_0                   0U      /* 0 : FE interrupts disabled; use polling.                           */
#define LPUART_CTRL_FEIEN_1                   1U      /* 1 : Hardware interrupt requested when FE is set.                   */


/* ==============================================  LPUART CTRL NEIEN [26..26]  ============================================== */
                                 /* LPUART_CTRL_NEIEN                                                 */
#define LPUART_CTRL_NEIEN_0                   0U      /* 0 : NF interrupts disabled; use polling.                           */
#define LPUART_CTRL_NEIEN_1                   1U      /* 1 : Hardware interrupt requested when NF is set.                   */


/* =============================================  LPUART CTRL OVRIEN [27..27]  ============================================== */
                                  /* LPUART_CTRL_OVRIEN                                                */
#define LPUART_CTRL_OVRIEN_0                  0U      /* 0 : OR interrupts disabled; use polling.                           */
#define LPUART_CTRL_OVRIEN_1                  1U      /* 1 : Hardware interrupt requested when OR is set.                   */


/* ============================================  LPUART CTRL TXDOPINV [28..28]  ============================================= */
                                  /* LPUART_CTRL_TXDOPINV                                              */
#define LPUART_CTRL_TXDOPINV_0                0U      /* 0 : Transmit data not inverted.                                    */
#define LPUART_CTRL_TXDOPINV_1                1U      /* 1 : Transmit data inverted.                                        */


/* ===========================================  LPUART CTRL TXDPDIRSEL [29..29]  ============================================ */
                                  /* LPUART_CTRL_TXDPDIRSEL                                            */
#define LPUART_CTRL_TXDPDIRSEL_0              0U      /* 0 : TXD pin is an input in single-wire mode.                       */
#define LPUART_CTRL_TXDPDIRSEL_1              1U      /* 1 : TXD pin is an output in single-wire mode.                      */


/* =========================================================  DATA  ========================================================== */
/* =============================================  LPUART DATA RXIDLE [11..11]  ============================================== */
                                  /* LPUART_DATA_RXIDLE                                                */
#define LPUART_DATA_RXIDLE_0                  0U      /* 0 : Receiver was not idle before receiving this character.         */
#define LPUART_DATA_RXIDLE_1                  1U      /* 1 : Receiver was idle before receiving this character.             */


/* ==============================================  LPUART DATA RXBE [12..12]  =============================================== */
                                  /* LPUART_DATA_RXBE                                                  */
#define LPUART_DATA_RXBE_0                    0U      /* 0 : Receive buffer contains valid data.                            */
#define LPUART_DATA_RXBE_1                    1U      /* 1 : Receive buffer is empty  data returned on read is not valid.   */


/* =============================================  LPUART DATA FETXSC [13..13]  ============================================== */
                                  /* LPUART_DATA_FETXSC                                                */
#define LPUART_DATA_FETXSC_0                  0U      /* 0 : The dataword was received without a frame error on read
                                                     or transmit a normal character on write.                           */
#define LPUART_DATA_FETXSC_1                  1U      /* 1 : The dataword was received with a frame error  or transmit
                                                     an idle or break character on transmit.                            */


/* ===============================================  LPUART DATA PE [14..14]  ================================================ */
                                  /* LPUART_DATA_PE                                                    */
#define LPUART_DATA_PE_0                      0U      /* 0 : The dataword was received without a parity error.              */
#define LPUART_DATA_PE_1                      1U      /* 1 : The dataword was received with a parity error.                 */


/* ===============================================  LPUART DATA NE [15..15]  ================================================ */
                                  /* LPUART_DATA_NE                                                    */
#define LPUART_DATA_NE_0                      0U      /* 0 : The dataword was received without noise.                       */
#define LPUART_DATA_NE_1                      1U      /* 1 : The data was received with noise.                              */


/* =========================================================  MADDR  ========================================================= */
/* ==========================================================  MIR  ========================================================== */
/* ===============================================  LPUART MIR TXCSEN [0..0]  =============================================== */
                                  /* LPUART_MIR_TXCSEN                                                 */
#define LPUART_MIR_TXCSEN_0                   0U      /* 0 : CTS has no effect on the transmitter.                          */
#define LPUART_MIR_TXCSEN_1                   1U      /* 1 : Enables clear-to-send operation. The transmitter checks
                                                     the state of CTS each time it is ready to send a character.
                                                     If CTS is asserted  the character is sent. If CTS is deasserted
                                                     the signal TXD remains in the mark state and transmission
                                                     is delayed until CTS is asserted. Changes in CTS as a character
                                                     is being sent do not affect its transmission.                      */


/* ===============================================  LPUART MIR TXRSEN [1..1]  =============================================== */
                                  /* LPUART_MIR_TXRSEN                                                 */
#define LPUART_MIR_TXRSEN_0                   0U      /* 0 : The transmitter has no effect on RTS.                          */
#define LPUART_MIR_TXRSEN_1                   1U      /* 1 : When a character is placed into an empty transmitter data
                                                     buffer   RTS asserts one bit time before the start bit
                                                     is transmitted. RTS deasserts one bit time after all characters
                                                     in the transmitter data buffer and shift register are completely
                                                     sent  including the last stop bit.                                 */


/* ==============================================  LPUART MIR TXRSPCFG [2..2]  ============================================== */
                                  /* LPUART_MIR_TXRSPCFG                                               */
#define LPUART_MIR_TXRSPCFG_0                 0U      /* 0 : Transmitter RTS is active low.                                 */
#define LPUART_MIR_TXRSPCFG_1                 1U      /* 1 : Transmitter RTS is active high.                                */


/* ===============================================  LPUART MIR RXRSEN [3..3]  =============================================== */
                                  /* LPUART_MIR_RXRSEN                                                 */
#define LPUART_MIR_RXRSEN_0                   0U      /* 0 : The receiver has no effect on RTS.                             */


/* ==============================================  LPUART MIR TXCSCFG [4..4]  =============================================== */
                                   /* LPUART_MIR_TXCSCFG                                                */
#define LPUART_MIR_TXCSCFG_0                  0U      /* 0 : CTS input is sampled at the start of each character.           */
#define LPUART_MIR_TXCSCFG_1                  1U      /* 1 : CTS input is sampled when the transmitter is idle.             */


/* =============================================  LPUART MIR TXCSRCSEL [5..5]  ============================================== */
                                  /* LPUART_MIR_TXCSRCSEL                                              */
#define LPUART_MIR_TXCSRCSEL_0                0U      /* 0 : CTS input is the CTS_B pin.                                    */
#define LPUART_MIR_TXCSRCSEL_1                1U      /* 1 : CTS input is the inverted Receiver Match result.               */


/* =============================================  LPUART MIR TXNPCFG [16..17]  ============================================== */
                                  /* LPUART_MIR_TXNPCFG                                                */
#define LPUART_MIR_TXNPCFG_00                 0U      /* 00 : 1/OSR.                                                        */
#define LPUART_MIR_TXNPCFG_01                 1U      /* 01 : 2/OSR.                                                        */
#define LPUART_MIR_TXNPCFG_10                 2U      /* 10 : 3/OSR.                                                        */
#define LPUART_MIR_TXNPCFG_11                 3U      /* 11 : 4/OSR.                                                        */


/* =============================================  LPUART MIR IRMODEEN [18..18]  ============================================= */
                                   /* LPUART_MIR_IRMODEEN                                               */
#define LPUART_MIR_IRMODEEN_0                 0U      /* 0 : IR disabled.                                                   */
#define LPUART_MIR_IRMODEEN_1                 1U      /* 1 : IR enabled.                                                    */


/* =========================================================  FIFO  ========================================================== */
/* =============================================  LPUART FIFO RXFBDCFG [0..2]  ============================================== */
                                  /* LPUART_FIFO_RXFBDCFG                                              */
#define LPUART_FIFO_RXFBDCFG_000              0U      /* 000 : Receive FIFO/Buffer depth = 1 dataword.                      */
#define LPUART_FIFO_RXFBDCFG_001              1U      /* 001 : Receive FIFO/Buffer depth = 4 datawords.                     */
#define LPUART_FIFO_RXFBDCFG_010              2U      /* 010 : Receive FIFO/Buffer depth = 8 datawords.                     */
#define LPUART_FIFO_RXFBDCFG_011              3U      /* 011 : Receive FIFO/Buffer depth = 16 datawords.                    */
#define LPUART_FIFO_RXFBDCFG_100              4U      /* 100 : Receive FIFO/Buffer depth = 32 datawords.                    */
#define LPUART_FIFO_RXFBDCFG_101              5U      /* 101 : Receive FIFO/Buffer depth = 64 datawords.                    */
#define LPUART_FIFO_RXFBDCFG_110              6U      /* 110 : Receive FIFO/Buffer depth = 128 datawords.                   */
#define LPUART_FIFO_RXFBDCFG_111              7U      /* 111 : Receive FIFO/Buffer depth = 256 datawords.                   */


/* ==============================================  LPUART FIFO RXBFEN [3..3]  =============================================== */
                                  /* LPUART_FIFO_RXBFEN                                                */
#define LPUART_FIFO_RXBFEN_0                  0U      /* 0 : Receive FIFO is not enabled. Buffer is depth 1. (Legacy
                                                     support)                                                           */
#define LPUART_FIFO_RXBFEN_1                  1U     /* 1 : Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.*/


/* =============================================  LPUART FIFO TXFBDCFG [4..6]  ============================================== */
                                  /* LPUART_FIFO_TXFBDCFG                                              */
#define LPUART_FIFO_TXFBDCFG_000              0U      /* 000 : Transmit FIFO/Buffer depth = 1 dataword.                     */
#define LPUART_FIFO_TXFBDCFG_001              1U      /* 001 : Transmit FIFO/Buffer depth = 4 datawords.                    */
#define LPUART_FIFO_TXFBDCFG_010              2U      /* 010 : Transmit FIFO/Buffer depth = 8 datawords.                    */
#define LPUART_FIFO_TXFBDCFG_011              3U      /* 011 : Transmit FIFO/Buffer depth = 16 datawords.                   */
#define LPUART_FIFO_TXFBDCFG_100              4U      /* 100 : Transmit FIFO/Buffer depth = 32 datawords.                   */
#define LPUART_FIFO_TXFBDCFG_101              5U      /* 101 : Transmit FIFO/Buffer depth = 64 datawords.                   */
#define LPUART_FIFO_TXFBDCFG_110              6U      /* 110 : Transmit FIFO/Buffer depth = 128 datawords.                  */
#define LPUART_FIFO_TXFBDCFG_111              7U      /* 111 : Transmit FIFO/Buffer depth = 256 datawords                   */


/* ==============================================  LPUART FIFO TXBFEN [7..7]  =============================================== */
                               /* LPUART_FIFO_TXBFEN                                         */
#define LPUART_FIFO_TXBFEN_0                  0U      /* 0 : Transmit FIFO is not enabled. Buffer is depth 1. (Legacy
                                                     support).                                                   */
#define LPUART_FIFO_TXBFEN_1                  1U   /* 1 : Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.*/


/* =============================================  LPUART FIFO RXUFGINT [8..8]  ============================================== */
                                 /* LPUART_FIFO_RXUFGINT                                       */
#define LPUART_FIFO_RXUFGINT_0                0U      /* 0 : RXUF flag does not generate an interrupt to the host.   */
#define LPUART_FIFO_RXUFGINT_1                1U      /* 1 : RXUF flag generates an interrupt to the host.           */


/* =============================================  LPUART FIFO TXOFGINT [9..9]  ============================================== */
                                  /* LPUART_FIFO_TXOFGINT                                       */
#define LPUART_FIFO_TXOFGINT_0                0U      /* 0 : TXOF flag does not generate an interrupt to the host.   */
#define LPUART_FIFO_TXOFGINT_1                1U      /* 1 : TXOF flag generates an interrupt to the host.           */


/* ============================================  LPUART FIFO CFGRXIEEN [10..12]  ============================================ */
                                  /* LPUART_FIFO_CFGRXIEEN                                      */
#define LPUART_FIFO_CFGRXIEEN_000             0U      /* 000 : Disable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle.                                           */
#define LPUART_FIFO_CFGRXIEEN_001             1U      /* 001 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 1 character.                           */
#define LPUART_FIFO_CFGRXIEEN_010             2U      /* 010 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 2 characters.                          */
#define LPUART_FIFO_CFGRXIEEN_011             3U      /* 011 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 4 characters.                          */
#define LPUART_FIFO_CFGRXIEEN_100             4U      /* 100 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 8 characters.                          */
#define LPUART_FIFO_CFGRXIEEN_101             5U      /* 101 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 16 characters.                         */
#define LPUART_FIFO_CFGRXIEEN_110             6U      /* 110 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 32 characters.                         */
#define LPUART_FIFO_CFGRXIEEN_111             7U      /* 111 : Enable RDRF assertion due to partially filled FIFO when
                                                     receiver is idle for 64 characters.                         */


/* ============================================  LPUART FIFO RXFBDFLU [14..14]  ============================================= */
                                   /* LPUART_FIFO_RXFBDFLU                                       */
#define LPUART_FIFO_RXFBDFLU_0                0U      /* 0 : No flush operation occurs.                              */
#define LPUART_FIFO_RXFBDFLU_1                1U      /* 1 : All data in the receive FIFO/buffer is cleared out.     */


/* ============================================  LPUART FIFO TXFBDFLU [15..15]  ============================================= */
                                  /* LPUART_FIFO_TXFBDFLU                                       */
#define LPUART_FIFO_TXFBDFLU_0                0U      /* 0 : No flush operation occurs.                              */
#define LPUART_FIFO_TXFBDFLU_1                1U      /* 1 : All data in the transmit FIFO/Buffer is cleared out.    */


/* =============================================  LPUART FIFO RXBUFLG [16..16]  ============================================= */
                                   /* LPUART_FIFO_RXBUFLG                                               */
#define LPUART_FIFO_RXBUFLG_0                 0U      /* 0 : No receive buffer underflow has occurred since the last
                                                     time the flag was cleared.                                         */
#define LPUART_FIFO_RXBUFLG_1                 1U      /* 1 : At least one receive buffer underflow has occurred since
                                                     the last time the flag was cleared.                                */


/* =============================================  LPUART FIFO TXBOFLG [17..17]  ============================================= */
                                  /* LPUART_FIFO_TXBOFLG                                               */
#define LPUART_FIFO_TXBOFLG_0                 0U      /* 0 : No transmit buffer overflow has occurred since the last
                                                     time the flag was cleared.                                         */
#define LPUART_FIFO_TXBOFLG_1                 1U      /* 1 : At least one transmit buffer overflow has occurred since
                                                     the last time the flag was cleared.                                */

/* ==============================================  LPUART FIFO RXBE [22..22]  =============================================== */
                                 /* LPUART_FIFO_RXBE                                                  */
#define LPUART_FIFO_RXBE_0                    0U      /* 0 : Receive buffer is not empty.                                   */
#define LPUART_FIFO_RXBE_1                    1U      /* 1 : Receive buffer is empty.                                       */


/* ==============================================  LPUART FIFO TXBE [23..23]  =============================================== */
                                  /* LPUART_FIFO_TXBE                                                  */
#define LPUART_FIFO_TXBE_0                    0U      /* 0 : Transmit buffer is not empty.                                  */
#define LPUART_FIFO_TXBE_1                    1U      /* 1 : Transmit buffer is empty.                                      */


/* =========================================================  WMKR  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           COMP                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL0  ========================================================= */
/* ===============================================  COMP CTRL0 HBHLSEL [0..1]  =============================================== */
                                   /* COMP_CTRL0_HBHLSEL                                                 */
#define COMP_CTRL0_HBHLSEL_00                  0U      /* 00 : The hard block output has level 0 hysteresis internally.      */
#define COMP_CTRL0_HBHLSEL_01                  1U      /* 01 : The hard block output has level 1 hysteresis internally.      */
#define COMP_CTRL0_HBHLSEL_10                  2U      /* 10 : The hard block output has level 2 hysteresis internally.      */
#define COMP_CTRL0_HBHLSEL_11                  3U      /* 11 : The hard block output has level 3 hysteresis internally.      */


/* ===============================================  COMP CTRL0 HBOLSEL [2..2]  =============================================== */
                                  /* COMP_CTRL0_HBOLSEL                                                 */
#define COMP_CTRL0_HBOLSEL_0                   0U      /* 0 : The comparator hard block output has level 0 offset internally.*/
#define COMP_CTRL0_HBOLSEL_1                   1U      /* 1 : The comparator hard block output has level 1 offset internally.*/


/* ==============================================  COMP CTRL0 FOSMPCNT [4..6]  =============================================== */
                               /* COMP_CTRL0_FOSMPCNT                                                */
#define COMP_CTRL0_FOSMPCNT_000                0U      /* 000 : Filter is disabled. If SE = 1  then COUT is a logic zero
                                                     (this is not a legal state  and is not recommended). If
                                                     SE = 0  COUT = COUTA.                                              */
#define COMP_CTRL0_FOSMPCNT_001                1U      /* 001 : 1 consecutive sample must agree (comparator output is
                                                     simply sampled).                                                   */
#define COMP_CTRL0_FOSMPCNT_010                2U      /* 010 : 2 consecutive samples must agree.                            */
#define COMP_CTRL0_FOSMPCNT_011                3U      /* 011 : 3 consecutive samples must agree.                            */
#define COMP_CTRL0_FOSMPCNT_100                4U      /* 100 : 4 consecutive samples must agree.                            */
#define COMP_CTRL0_FOSMPCNT_101                5U      /* 101 : 5 consecutive samples must agree.                            */
#define COMP_CTRL0_FOSMPCNT_110                6U      /* 110 : 6 consecutive samples must agree.                            */
#define COMP_CTRL0_FOSMPCNT_111                7U      /* 111 : 7 consecutive samples must agree.                            */


/* ================================================  COMP CTRL0 ACEN [8..8]  ================================================= */
                                  /* COMP_CTRL0_ACEN                                                    */
#define COMP_CTRL0_ACEN_0                      0U      /* 0 : Analog Comparator is disabled.                                 */
#define COMP_CTRL0_ACEN_1                      1U      /* 1 : Analog Comparator is enabled.                                  */


/* ===============================================  COMP CTRL0 COPCFG [9..9]  ================================================ */
                               /* COMP_CTRL0_COPCFG                                                  */
#define COMP_CTRL0_COPCFG_0                    0U      /* 0 : When OPE is 0  the comparator output (after window/filter
                                                     settings dependent on software configuration) is not available
                                                     to a packaged pin.                                                 */
#define COMP_CTRL0_COPCFG_1                    1U      /* 1 : When OPE is 1  and if the software has configured the comparator
                                                     to own a packaged pin  the comparator is available in a
                                                     packaged pin.                                                      */


/* ===============================================  COMP CTRL0 COCFG [10..10]  =============================================== */
                                 /* COMP_CTRL0_COCFG                                                   */
#define COMP_CTRL0_COCFG_0                     0U      /* 0 : Set CMPO to equal COUT (filtered comparator output).           */
#define COMP_CTRL0_COCFG_1                     1U      /* 1 : Set CMPO to equal COUTA (unfiltered comparator output).        */


/* ===============================================  COMP CTRL0 INVEN [11..11]  =============================================== */
                                 /* COMP_CTRL0_INVEN                                                   */
#define COMP_CTRL0_INVEN_0                     0U      /* 0 : Does not invert the comparator output.                         */
#define COMP_CTRL0_INVEN_1                     1U      /* 1 : Inverts the comparator output.                                 */


/* ===============================================  COMP CTRL0 PMSEL [12..12]  =============================================== */
                                 /* COMP_CTRL0_PMSEL                                                   */
#define COMP_CTRL0_PMSEL_0                     0U      /* 0 : Low Speed (LS) comparison mode is selected.                    */
#define COMP_CTRL0_PMSEL_1                     1U      /* 1 : High Speed (HS) comparison mode is selected  in VLPx mode
                                                     or Stop mode switched to Low Speed (LS) mode.                      */


/* ==============================================  COMP CTRL0 WINMEN [14..14]  =============================================== */
                                /* COMP_CTRL0_WINMEN                                                  */
#define COMP_CTRL0_WINMEN_0                    0U      /* 0 : Windowing mode is not selected.                                */
#define COMP_CTRL0_WINMEN_1                    1U      /* 1 : Windowing mode is selected.                                    */


/* ==============================================  COMP CTRL0 SMPMEN [15..15]  =============================================== */
                                  /* COMP_CTRL0_SMPMEN                                                  */
#define COMP_CTRL0_SMPMEN_0                    0U      /* 0 : Sampling mode is not selected.                                 */
#define COMP_CTRL0_SMPMEN_1                    1U      /* 1 : Sampling mode is selected.                                     */


/* ==============================================  COMP CTRL0 ACFFLG [25..25]  =============================================== */
                                 /* COMP_CTRL0_ACFFLG                                                  */
#define COMP_CTRL0_ACFFLG_0                    0U      /* 0 : A falling edge has not been detected on COUT.                  */
#define COMP_CTRL0_ACFFLG_1                    1U      /* 1 : A falling edge on COUT has occurred.                           */


/* ==============================================  COMP CTRL0 ACRFLG [26..26]  =============================================== */
                                  /* COMP_CTRL0_ACRFLG                                                  */
#define COMP_CTRL0_ACRFLG_0                    0U      /* 0 : A rising edge has not been detected on COUT.                   */
#define COMP_CTRL0_ACRFLG_1                    1U      /* 1 : A rising edge on COUT has occurred.                            */


/* ==============================================  COMP CTRL0 ACFIEN [27..27]  =============================================== */
                                   /* COMP_CTRL0_ACFIEN                                                  */
#define COMP_CTRL0_ACFIEN_0                    0U      /* 0 : Interrupt is disabled.                                         */
#define COMP_CTRL0_ACFIEN_1                    1U      /* 1 : Interrupt is enabled.                                          */


/* ==============================================  COMP CTRL0 ACRIEN [28..28]  =============================================== */
                                  /* COMP_CTRL0_ACRIEN                                                  */
#define COMP_CTRL0_ACRIEN_0                    0U      /* 0 : Interrupt is disabled.                                         */
#define COMP_CTRL0_ACRIEN_1                    1U      /* 1 : Interrupt is enabled.                                          */


/* ===============================================  COMP CTRL0 DMAEN [30..30]  =============================================== */
                                /* COMP_CTRL0_DMAEN                                                   */
#define COMP_CTRL0_DMAEN_0                     0U      /* 0 : DMA is disabled.                                               */
#define COMP_CTRL0_DMAEN_1                     1U      /* 1 : DMA is enabled.                                                */


/* =========================================================  CTRL1  ========================================================= */
/* =============================================  COMP CTRL1 MUXMICSEL [8..10]  ============================================== */
                                   /* COMP_CTRL1_MUXMICSEL                                               */
#define COMP_CTRL1_MUXMICSEL_000               0U      /* 000 : IN0                                                          */
#define COMP_CTRL1_MUXMICSEL_001               1U      /* 001 : IN1                                                          */
#define COMP_CTRL1_MUXMICSEL_010               2U      /* 010 : IN2                                                          */
#define COMP_CTRL1_MUXMICSEL_011               3U      /* 011 : IN3                                                          */
#define COMP_CTRL1_MUXMICSEL_100               4U      /* 100 : IN4                                                          */
#define COMP_CTRL1_MUXMICSEL_101               5U      /* 101 : IN5                                                          */
#define COMP_CTRL1_MUXMICSEL_110               6U      /* 110 : IN6                                                          */
#define COMP_CTRL1_MUXMICSEL_111               7U      /* 111 : IN7                                                          */


/* =============================================  COMP CTRL1 MUXPICSEL [11..13]  ============================================= */
                                   /* COMP_CTRL1_MUXPICSEL                                               */
#define COMP_CTRL1_MUXPICSEL_000               0U      /* 000 : IN0                                                          */
#define COMP_CTRL1_MUXPICSEL_001               1U      /* 001 : IN1                                                          */
#define COMP_CTRL1_MUXPICSEL_010               2U      /* 010 : IN2                                                          */
#define COMP_CTRL1_MUXPICSEL_011               3U      /* 011 : IN3                                                          */
#define COMP_CTRL1_MUXPICSEL_100               4U      /* 100 : IN4                                                          */
#define COMP_CTRL1_MUXPICSEL_101               5U      /* 101 : IN5                                                          */
#define COMP_CTRL1_MUXPICSEL_110               6U      /* 110 : IN6                                                          */
#define COMP_CTRL1_MUXPICSEL_111               7U      /* 111 : IN7                                                          */


/* ==============================================  COMP CTRL1 SVRSSEL [14..14]  ============================================== */
                                  /* COMP_CTRL1_SVRSSEL                                                 */
#define COMP_CTRL1_SVRSSEL_0                   0U      /* 0 : Vin1 is selected as resistor ladder network supply reference
                                                     Vin.                                                               */
#define COMP_CTRL1_SVRSSEL_1                   1U      /* 1 : Vin2 is selected as resistor ladder network supply reference
                                                     Vin.                                                               */


/* ===============================================  COMP CTRL1 DACEN [15..15]  =============================================== */
                                  /* COMP_CTRL1_DACEN                                                   */
#define COMP_CTRL1_DACEN_0                     0U      /* 0 : DAC is disabled.                                               */
#define COMP_CTRL1_DACEN_1                     1U      /* 1 : DAC is enabled.                                                */


/* ==============================================  COMP CTRL1 CNISEL [24..25]  =============================================== */
                                  /* COMP_CTRL1_CNISEL                                                  */
#define COMP_CTRL1_CNISEL_00                   0U      /* 00 : IN0  from the 8-bit DAC output                                */
#define COMP_CTRL1_CNISEL_01                   1U      /* 01 : IN1  from the analog 8-1 mux                                  */


/* ==============================================  COMP CTRL1 CPISEL [27..28]  =============================================== */
                                 /* COMP_CTRL1_CPISEL                                                  */
#define COMP_CTRL1_CPISEL_00                   0U      /* 00 : IN0  from the 8-bit DAC output                                */
#define COMP_CTRL1_CPISEL_01                   1U      /* 01 : IN1  from the analog 8-1 mux                                  */


/* =========================================================  CTRL2  ========================================================= */
/* ==============================================  COMP CTRL2 IDCLKCFG [8..13]  ============================================== */
                                /* COMP_CTRL2_IDCLKCFG                                                */
#define COMP_CTRL2_IDCLKCFG_000000             0U      /* 000000 : The modulus is set to 64 (same with 111111).              */

/* ===============================================  COMP CTRL2 NSCFG [14..15]  =============================================== */
                                 /* COMP_CTRL2_NSCFG                                                   */
#define COMP_CTRL2_NSCFG_00                    0U      /* 00 : The comparison result is sampled as soon as the active
                                                     channel is scanned in one round-robin clock.                       */
#define COMP_CTRL2_NSCFG_01                    1U      /* 01 : The sampling takes place 1 round-robin clock cycle after
                                                     the next cycle of the round-robin clock.                           */
#define COMP_CTRL2_NSCFG_10                    2U      /* 10 : The sampling takes place 2 round-robin clock cycles after
                                                     the next cycle of the round-robin clock.                           */
#define COMP_CTRL2_NSCFG_11                    3U      /* 11 : The sampling takes place 3 round-robin clock cycles after
                                                     the next cycle of the round-robin clock.                           */


/* =============================================  COMP CTRL2 MUXFCHSEL [25..27]  ============================================= */
                                 /* COMP_CTRL2_MUXFCHSEL                                               */
#define COMP_CTRL2_MUXFCHSEL_000               0U      /* 000 : Channel 0 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_001               1U      /* 001 : Channel 1 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_010               2U      /* 010 : Channel 2 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_011               3U      /* 011 : Channel 3 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_100               4U      /* 100 : Channel 4 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_101               5U      /* 101 : Channel 5 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_110               6U      /* 110 : Channel 6 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */
#define COMP_CTRL2_MUXFCHSEL_111               7U      /* 111 : Channel 7 is selected as the fixed reference input for
                                                     the fixed mux port.                                                */


/* =============================================  COMP CTRL2 MUXFPSEL [29..29]  ============================================== */
                                 /* COMP_CTRL2_MUXFPSEL                                                */
#define COMP_CTRL2_MUXFPSEL_0                  0U      /* 0 : The Plus port is fixed. Only the inputs to the Minus port
                                                     are swept in each round.                                           */
#define COMP_CTRL2_MUXFPSEL_1                  1U      /* 1 : The Minus port is fixed. Only the inputs to the Plus port
                                                     are swept in each round.                                           */


/* ===============================================  COMP CTRL2 RRIEN [30..30]  =============================================== */
                               /* COMP_CTRL2_RRIEN                                                   */
#define COMP_CTRL2_RRIEN_0                     0U      /* 0 : The round-robin interrupt is disabled.                         */
#define COMP_CTRL2_RRIEN_1                     1U      /* 1 : The round-robin interrupt is enabled when a comparison result
                                                     changes from the last sample.                                      */


/* ===============================================  COMP CTRL2 RRSEL [31..31]  =============================================== */
                                  /* COMP_CTRL2_RRSEL                                                   */
#define COMP_CTRL2_RRSEL_0                     0U      /* 0 : Round-robin operation is disabled.                             */
#define COMP_CTRL2_RRSEL_1                     1U      /* 1 : Round-robin operation is enabled.                              */




/* =========================================================================================================================== */
/* ================                                            PMU                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  LVDCSTS1  ======================================================== */
/* ============================================  PMU LVDCSTS1 LVDEGSYSREN [4..4]  ============================================ */
                                  /* PMU_LVDCSTS1_LVDEGSYSREN                                           */
#define PMU_LVDCSTS1_LVDEGSYSREN_0             0U      /* 0 : Hardware interrupt disabled (use polling)                      */
#define PMU_LVDCSTS1_LVDEGSYSREN_1             1U      /* 1 : Request a hardware interrupt when LVWF=1                       */


/* ==============================================  PMU LVDCSTS1 LVWEFLG [7..7]  ============================================== */
                                  /* PMU_LVDCSTS1_LVWEFLG                                               */
#define PMU_LVDCSTS1_LVWEFLG_0                 0U      /* 0 : Low-voltage warning event not detected                         */
#define PMU_LVDCSTS1_LVWEFLG_1                 1U      /* 1 : Low-voltage warning event detected                             */


/* =======================================================  LVDCSTS2  ======================================================== */
/* ============================================  PMU LVDCSTS2 LVWHWINTREN [5..5]  ============================================ */
                                  /* PMU_LVDCSTS2_LVWHWINTREN                                           */
#define PMU_LVDCSTS2_LVWHWINTREN_0             0U      /* 0 : Hardware interrupt disabled (use polling)                      */
#define PMU_LVDCSTS2_LVWHWINTREN_1             1U      /* 1 : Request a hardware interrupt when LVWF=1                       */


/* ==============================================  PMU LVDCSTS2 LVWEFLG [7..7]  ============================================== */
                                  /* PMU_LVDCSTS2_LVWEFLG                                               */
#define PMU_LVDCSTS2_LVWEFLG_0                 0U      /* 0 : Low-voltage warning event not detected                         */
#define PMU_LVDCSTS2_LVWEFLG_1                 1U      /* 1 : Low-voltage warning event detected                             */


/* ========================================================  REGCSTS  ======================================================== */
/* ================================================  PMU REGCSTS BEN [0..0]  ================================================= */
                                  /* PMU_REGCSTS_BEN                                                    */
#define PMU_REGCSTS_BEN_0                      0U      /* 0 : Biasing disabled  core logic can run in full performance       */
#define PMU_REGCSTS_BEN_1                      1U      /* 1 : Biasing enabled  core logic is slower and there are restrictions
                                                     in allowed system clock speed (see Data Sheet for details)         */


/* ==============================================  PMU REGCSTS CLKBDIS [1..1]  =============================================== */
                                  /* PMU_REGCSTS_CLKBDIS                                                */
#define PMU_REGCSTS_CLKBDIS_0                  0U      /* 0 : No effect                                                      */
#define PMU_REGCSTS_CLKBDIS_1                  1U      /* 1 : In VLPS mode  the bias currents and reference voltages for
                                                     the following clock modules are disabled: LSI  HSI  PLL.
                                                     (if available on device)                                           */


/* ==============================================  PMU REGCSTS RFPMSTS [2..2]  =============================================== */
                                 /* PMU_REGCSTS_RFPMSTS                                                */
#define PMU_REGCSTS_RFPMSTS_0                  0U      /* 0 : Regulator is in low power mode or transition to/from           */
#define PMU_REGCSTS_RFPMSTS_1                  1U      /* 1 : Regulator is in full performance mode                          */


/* =============================================  PMU REGCSTS LPOCLKSTS [6..6]  ============================================== */
                                 /* PMU_REGCSTS_LPOCLKSTS                                              */
#define PMU_REGCSTS_LPOCLKSTS_0                0U      /* 0 : Low power oscillator in low phase                              */
#define PMU_REGCSTS_LPOCLKSTS_1                1U      /* 1 : Low power oscillator in high phase                             */


/* ===============================================  PMU REGCSTS LPODIS [7..7]  =============================================== */
                                 /* PMU_REGCSTS_LPODIS                                                 */
#define PMU_REGCSTS_LPODIS_0                   0U      /* 0 : Low power oscillator enabled                                   */
#define PMU_REGCSTS_LPODIS_1                   1U      /* 1 : Low power oscillator disabled                                  */


/* =======================================================  LPOSCTRIM  ======================================================= */


/* =========================================================================================================================== */
/* ================                                           SYSMC                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* ==============================================  SYSMC VERID FEATURE [0..15]  ============================================== */
                               /* SYSMC_VERID_FEATURE                                                */
#define SYSMC_VERID_FEATURE_0                  0U      /* 0 : Standard features implemented                                  */


/* ========================================================  FEATURE  ======================================================== */
/* =============================================  SYSMC FEATURE HSRUNAVA [0..0]  ============================================= */
                                  /* SYSMC_FEATURE_HSRUNAVA                                             */
#define SYSMC_FEATURE_HSRUNAVA_0               0U      /* 0 : The feature is not available.                                  */
#define SYSMC_FEATURE_HSRUNAVA_1               1U      /* 1 : The feature is available.                                      */


/* ==============================================  SYSMC FEATURE LLSAVA [3..3]  ============================================== */
                                   /* SYSMC_FEATURE_LLSAVA                                               */
#define SYSMC_FEATURE_LLSAVA_0                 0U      /* 0 : The feature is not available.                                  */
#define SYSMC_FEATURE_LLSAVA_1                 1U      /* 1 : The feature is available.                                      */


/* =============================================  SYSMC FEATURE LLS2AVA [5..5]  ============================================== */
                                  /* SYSMC_FEATURE_LLS2AVA                                              */
#define SYSMC_FEATURE_LLS2AVA_0                0U      /* 0 : The feature is not available.                                  */
#define SYSMC_FEATURE_LLS2AVA_1                1U      /* 1 : The feature is available.                                      */


/* =============================================  SYSMC FEATURE VLLS0AVA [6..6]  ============================================= */
                                   /* SYSMC_FEATURE_VLLS0AVA                                             */
#define SYSMC_FEATURE_VLLS0AVA_0               0U      /* 0 : The feature is not available.                                  */
#define SYSMC_FEATURE_VLLS0AVA_1               1U      /* 1 : The feature is available.                                      */


/* =========================================================  PMPRO  ========================================================= */
/* ==============================================  SYSMC PMPRO ALLOWLP [5..5]  ============================================== */
                                  /* SYSMC_PMPROALLOWLP                                               */
#define SYSMC_PMPRO_ALLOWLP_0                 0U      /* 0 : VLPR and VLPS are not allowed.                                 */
#define SYSMC_PMPRO_ALLOWLP_1                 1U      /* 1 : VLPR and VLPS are allowed.                                     */


/* ==============================================  SYSMC PMPRO ALLOWHS [7..7]  =============================================== */
                                /* SYSMC_PMPRO_ALLOWHS                                                */
#define SYSMC_PMPRO_ALLOWHS_0                  0U      /* 0 : HSRUN is not allowed                                           */
#define SYSMC_PMPRO_ALLOWHS_1                  1U      /* 1 : HSRUN is allowed                                               */


/* ========================================================  PMCTRL  ========================================================= */
/* =============================================  SYSMC PMCTRL STOPCTRL [0..2]  ============================================== */
                                  /* SYSMC_PMCTRL_STOPCTRL                                              */
#define SYSMC_PMCTRL_STOPCTRL_000              0U      /* 000 : Normal Stop (STOP)                                           */
#define SYSMC_PMCTRL_STOPCTRL_010              2U      /* 010 : Very-Low-Power Stop (VLPS)                                   */
#define SYSMC_PMCTRL_STOPCTRL_110              6U      /* 110 : Reseved                                                      */


/* =============================================  SYSMC PMCTRL VLPSEA [3..3]  ============================================= */
                                  /* SYSMC_PMCTRL_VLPSEA                                             */
#define SYSMC_PMCTRL_VLPSEA_0               0U      /* 0 : The previous stop mode entry was successful.                   */
#define SYSMC_PMCTRL_VLPSEA_1               1U      /* 1 : The previous stop mode entry was aborted.                      */


/* ==============================================  SYSMC PMCTRL RUNCTRL [5..6]  ============================================== */
                                 /* SYSMC_PMCTRL_RUNCTRL                                               */
#define SYSMC_PMCTRL_RUNCTRL_00                0U      /* 00 : Normal Run mode (RUN)                                         */
#define SYSMC_PMCTRL_RUNCTRL_10                2U      /* 10 : Very-Low-Power Run mode (VLPR)                                */
#define SYSMC_PMCTRL_RUNCTRL_11                3U      /* 11 : High Speed Run mode (HSRUN)                                   */


/* =======================================================  STOPOSEL  ======================================================== */
/* ============================================  SYSMC STOPOSEL STOPOSEL [6..7]  ============================================= */
                                   /* SYSMC_STOPOSEL_STOPOSEL                                            */
#define SYSMC_STOPOSEL_STOPOSEL_01             1U      /* 01 : STOP1 - Stop with both system and bus clocks disabled         */
#define SYSMC_STOPOSEL_STOPOSEL_10             2U      /* 10 : STOP2 - Stop with system clock disabled and bus clock enabled */


/* =========================================================  PMSTS  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            RMU                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  VERID  ========================================================= */
/* ===============================================  RMU VERID FEATURE [0..15]  =============================================== */
                              /* RMU_VERID_FEATURE                                                  */
#define RMU_VERID_FEATURE_11                   3U      /* 11 : Standard feature set.                                         */


/* =========================================================  PARA  ========================================================== */
/* ===============================================  RMU PARA LVDRSTSTS [0..0]  =============================================== */
                                 /* RMU_PARA_LVDRSTSTS                                                 */
#define RMU_PARA_LVDRSTSTS_0                   0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_LVDRSTSTS_1                   1U      /* 1 : The feature is available.                                      */


/* ==============================================  RMU PARA CLKLRSTSTS [1..1]  =============================================== */
                                  /* RMU_PARA_CLKLRSTSTS                                                */
#define RMU_PARA_CLKLRSTSTS_0                  0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_CLKLRSTSTS_1                  1U      /* 1 : The feature is available.                                      */


/* ==============================================  RMU PARA LOCKLRSTSTS [2..2]  ============================================== */
                               /* RMU_PARA_LOCKLRSTSTS                                               */
#define RMU_PARA_LOCKLRSTSTS_0                 0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_LOCKLRSTSTS_1                 1U      /* 1 : The feature is available.                                      */


/* ===============================================  RMU PARA WDTRSTSTS [5..5]  =============================================== */
                                  /* RMU_PARA_WDTRSTSTS                                                 */
#define RMU_PARA_WDTRSTSTS_0                   0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_WDTRSTSTS_1                   1U      /* 1 : The feature is available.                                      */


/* ================================================  RMU PARA ERSTSTS [6..6]  ================================================ */
                                 /* RMU_PARA_ERSTSTS                                                   */
#define RMU_PARA_ERSTSTS_0                     0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_ERSTSTS_1                     1U      /* 1 : The feature is available.                                      */


/* ===============================================  RMU PARA PORRSTSTS [7..7]  =============================================== */
                                 /* RMU_PARA_PORRSTSTS                                                 */
#define RMU_PARA_PORRSTSTS_0                   0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_PORRSTSTS_1                   1U      /* 1 : The feature is available.                                      */


/* ==============================================  RMU PARA JTAGRSTSTS [8..8]  =============================================== */
                                  /* RMU_PARA_JTAGRSTSTS                                                */
#define RMU_PARA_JTAGRSTSTS_0                  0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_JTAGRSTSTS_1                  1U      /* 1 : The feature is available.                                      */


/* ==============================================  RMU PARA CLOCKRSTSTS [9..9]  ============================================== */
                                 /* RMU_PARA_CLOCKRSTSTS                                               */
#define RMU_PARA_CLOCKRSTSTS_0                 0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_CLOCKRSTSTS_1                 1U      /* 1 : The feature is available.                                      */


/* ==============================================  RMU PARA SWRSTSTS [10..10]  =============================================== */
                                  /* RMU_PARA_SWRSTSTS                                                  */
#define RMU_PARA_SWRSTSTS_0                    0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_SWRSTSTS_1                    1U      /* 1 : The feature is available.                                      */


/* ===============================================  RMU PARA SRSTSTS [11..11]  =============================================== */
                                 /* RMU_PARA_SRSTSTS                                                   */
#define RMU_PARA_SRSTSTS_0                     0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_SRSTSTS_1                     1U      /* 1 : The feature is available.                                      */


/* ===========================================  RMU PARA STOPACKERSTSTS [13..13]  ============================================ */
                                /* RMU_PARA_STOPACKERSTSTS                                            */
#define RMU_PARA_STOPACKERSTSTS_0              0U      /* 0 : The feature is not available.                                  */
#define RMU_PARA_STOPACKERSTSTS_1              1U      /* 1 : The feature is available.                                      */


/* ========================================================  RSTFLG  ========================================================= */
/* ===============================================  RMU RSTFLG LVDRSTFLG [1..1]  ================================================ */
                                 /* RMU_RSTFLG_LVDRSTFLG                                                  */
#define RMU_RSTFLG_LVDRSTFLG_0                    0U      /* 0 : Reset not caused by LVD trip  HVD trip or POR                  */
#define RMU_RSTFLG_LVDRSTFLG_1                    1U      /* 1 : Reset caused by LVD trip  HVD trip or POR                      */


/* ===============================================  RMU RSTFLG CLKLRSTFLG [2..2]  =============================================== */
                                 /* RMU_RSTFLG_CLKLRSTFLG                                                 */
#define RMU_RSTFLG_CLKLRSTFLG_0                   0U      /* 0 : Reset not caused by a loss of external clock.                  */
#define RMU_RSTFLG_CLKLRSTFLG_1                   1U      /* 1 : Reset caused by a loss of external clock.                      */


/* ==============================================  RMU RSTFLG LOCKLRSTFLG [3..3]  =============================================== */
                                   /* RMU_RSTFLG_LOCKLRSTFLG                                                */
#define RMU_RSTFLG_LOCKLRSTFLG_0                  0U      /* 0 : Reset not caused by a loss of lock in the PLL/FLL              */
#define RMU_RSTFLG_LOCKLRSTFLG_1                  1U      /* 1 : Reset caused by a loss of lock in the PLL/FLL                  */

/* ===============================================  RMU RSTFLG WDTTOFFLG [5..5]  ================================================ */
                                 /* RMU_RSTFLG_WDTTOFFLG                                                  */
#define RMU_RSTFLG_WDTTOFFLG_0                    0U      /* 0 : Reset not caused by external reset pin                         */
#define RMU_RSTFLG_WDTTOFFLG_1                    1U      /* 1 : Reset caused by external reset pin                             */


/* ================================================  RMU RSTFLG ERSTPFLG [6..6]  ================================================ */
                                   /* RMU_RSTFLG_ERSTPFLG                                                   */
#define RMU_RSTFLG_ERSTPFLG_0                     0U      /* 0 : Reset not caused by POR                                        */
#define RMU_RSTFLG_ERSTPFLG_1                     1U      /* 1 : Reset caused by POR                                            */


/* =================================================  RMU RSTFLG PORFLG [7..7]  ================================================= */
                                   /* RMU_RSTFLG_PORFLG                                                     */
#define RMU_RSTFLG_PORFLG_0                       0U      /* 0 : Reset not caused by JTAG                                       */
#define RMU_RSTFLG_PORFLG_1                       1U      /* 1 : Reset caused by JTAG                                           */


/* ===============================================  RMU RSTFLG JTAGRSTFLG [8..8]  =============================================== */
                                   /* RMU_RSTFLG_JTAGRSTFLG                                                 */
#define RMU_RSTFLG_JTAGRSTFLG_0                   0U      /* 0 : Reset not caused by core LOCKUP event                          */
#define RMU_RSTFLG_JTAGRSTFLG_1                   1U      /* 1 : Reset caused by core LOCKUP event                              */


/* ==============================================  RMU RSTFLG CLOCKEFLG [9..9]  =============================================== */
                                 /* RMU_RSTFLG_CLOCKEFLG                                                 */
#define RMU_RSTFLG_CLOCKEFLG_0                    0U      /* 0 : Reset not caused by software setting of SYSRESETREQ bit        */
#define RMU_RSTFLG_CLOCKEFLG_1                    1U      /* 1 : Reset caused by software setting of SYSRESETREQ bit            */


/* ===============================================  RMU RSTFLG SWSETFLG [10..10]  =============================================== */
                                 /* RMU_RSTFLG_SWSETFLG                                                   */
#define RMU_RSTFLG_SWSETFLG_0                     0U      /* 0 : Reset was not caused by host debugger system setting of
                                                     the System Reset Request bit                                       */
#define RMU_RSTFLG_SWSETFLG_1                     1U      /* 1 : Reset was caused by host debugger system setting of the
                                                     System Reset Request bit                                           */

/* ==============================================  RMU RSTFLG SRSTREQFLG [11..11]  ============================================== */
                                  /* RMU_RSTFLG_SRSTREQFLG                                                        */
 #define RMU_RSTFLG_SRSTREQFLG_0                  0U     /* 0 : Reset was not caused by host debugger system setting of
                                                     the System Reset Request bit                                              */
#define  RMU_RSTFLG_SRSTREQFLG_1                  1U     /* 1 : Reset was caused by host debugger system setting of the
                                                     System Reset Request bit                                                  */

/* ==============================================  RMU RSTFLG SRSTREQFLG [13..13]  ============================================== */
                                 /* RMU_RSTFLG_SRSTREQFLG                                                 */
#define RMU_RSTFLG_SRSTREQFLG_0                   0U      /* 0 : Reset not caused by peripheral failure to acknowledge attempt
                                                     to enter stop mode                                                 */
#define RMU_RSTFLG_SRSTREQFLG_1                   1U      /* 1 : Reset caused by peripheral failure to acknowledge attempt
                                                     to enter stop mode                                                 */


/* =======================================================  RSTPCTRL  ======================================================== */
/* =============================================  RMU RSTPCTRL RSTPFSEL [0..1]  ============================================== */
                                  /* RMU_RSTPCTRL_RSTPFSEL                                              */
#define RMU_RSTPCTRL_RSTPFSEL_00               0U      /* 00 : All filtering disabled                                        */
#define RMU_RSTPCTRL_RSTPFSEL_01               1U      /* 01 : Bus clock filter enabled for normal operation                 */
#define RMU_RSTPCTRL_RSTPFSEL_10               2U      /* 10 : LPO clock filter enabled for normal operation                 */


/* ==============================================  RMU RSTPCTRL RSTPFEN [2..2]  ============================================== */
                                   /* RMU_RSTPCTRL_RSTPFEN                                               */
#define RMU_RSTPCTRL_RSTPFEN_0                 0U      /* 0 : All filtering disabled                                         */
#define RMU_RSTPCTRL_RSTPFEN_1                 1U      /* 1 : LPO clock filter enabled                                       */


/* ========================================================  SRSTFLG  ======================================================== */
/* =============================================  RMU SRSTFLG LVDRSTRCD [1..1]  ============================================== */
                                  /* RMU_SRSTFLG_LVDRSTRCD                                              */
#define RMU_SRSTFLG_LVDRSTRCD_0                0U      /* 0 : Reset not caused by LVD trip or POR                            */
#define RMU_SRSTFLG_LVDRSTRCD_1                1U      /* 1 : Reset caused by LVD trip or POR                                */


/* ============================================  RMU SRSTFLG ECLKLRSTRCD [2..2]  ============================================= */
                                  /* RMU_SRSTFLG_ECLKLRSTRCD                                            */
#define RMU_SRSTFLG_ECLKLRSTRCD_0              0U      /* 0 : Reset not caused by a loss of external clock.                  */
#define RMU_SRSTFLG_ECLKLRSTRCD_1              1U      /* 1 : Reset caused by a loss of external clock.                      */


/* ============================================  RMU SRSTFLG LOCKLRSTRCD [3..3]  ============================================= */
                                  /* RMU_SRSTFLG_LOCKLRSTRCD                                            */
#define RMU_SRSTFLG_LOCKLRSTRCD_0              0U      /* 0 : Reset not caused by a loss of lock in the PLL/FLL              */
#define RMU_SRSTFLG_LOCKLRSTRCD_1              1U      /* 1 : Reset caused by a loss of lock in the PLL/FLL                  */


/* =============================================  RMU SRSTFLG WDTRSTRCD [5..5]  ============================================== */
                                  /* RMU_SRSTFLG_WDTRSTRCD                                              */
#define RMU_SRSTFLG_WDTRSTRCD_0                0U      /* 0 : Reset not caused by watchdog timeout                           */
#define RMU_SRSTFLG_WDTRSTRCD_1                1U      /* 1 : Reset caused by watchdog timeout                               */


/* ==============================================  RMU SRSTFLG EPRSTRCD [6..6]  ============================================== */
                                   /* RMU_SRSTFLG_EPRSTRCD                                               */
#define RMU_SRSTFLG_EPRSTRCD_0                 0U      /* 0 : Reset not caused by external reset pin                         */
#define RMU_SRSTFLG_EPRSTRCD_1                 1U      /* 1 : Reset caused by external reset pin                             */


/* ===============================================  RMU SRSTFLG PORRCD [7..7]  =============================================== */
                                  /* RMU_SRSTFLG_PORRCD                                                 */
#define RMU_SRSTFLG_PORRCD_0                   0U      /* 0 : Reset not caused by POR                                        */
#define RMU_SRSTFLG_PORRCD_1                   1U      /* 1 : Reset caused by POR                                            */


/* =============================================  RMU SRSTFLG JTAGRSTRCD [8..8]  ============================================= */
                                  /* RMU_SRSTFLG_JTAGRSTRCD                                             */
#define RMU_SRSTFLG_JTAGRSTRCD_0               0U      /* 0 : Reset not caused by JTAG                                       */
#define RMU_SRSTFLG_JTAGRSTRCD_1               1U      /* 1 : Reset caused by JTAG                                           */


/* ==============================================  RMU SRSTFLG CLOCKRCD [9..9]  ============================================== */
                                  /* RMU_SRSTFLG_CLOCKRCD                                               */
#define RMU_SRSTFLG_CLOCKRCD_0                 0U      /* 0 : Reset not caused by core LOCKUP event                          */
#define RMU_SRSTFLG_CLOCKRCD_1                 1U      /* 1 : Reset caused by core LOCKUP event                              */


/* =============================================  RMU SRSTFLG SWRSTRCD [10..10]  ============================================= */
                                   /* RMU_SRSTFLG_SWRSTRCD                                               */
#define RMU_SRSTFLG_SWRSTRCD_0                 0U      /* 0 : Reset not caused by software setting of SYSRESETREQ bit        */
#define RMU_SRSTFLG_SWRSTRCD_1                 1U      /* 1 : Reset caused by software setting of SYSRESETREQ bit            */


/* ============================================  RMU SRSTFLG SRSTREGRCD [11..11]  ============================================ */
                                  /* RMU_SRSTFLG_SRSTREGRCD                                             */
#define RMU_SRSTFLG_SRSTREGRCD_0               0U      /* 0 : Reset was not caused by host debugger system setting of
                                                     the System Reset Request bit                                       */
#define RMU_SRSTFLG_SRSTREGRCD_1               1U      /* 1 : Reset was caused by host debugger system setting of the
                                                     System Reset Request bit                                           */


/* ==========================================  RMU SRSTFLG STOPACKERSTRCD [13..13]  ========================================== */
                                 /* RMU_SRSTFLG_STOPACKERSTRCD                                         */
#define RMU_SRSTFLG_STOPACKERSTRCD_0           0U      /* 0 : Reset not caused by peripheral failure to acknowledge attempt
                                                     to enter stop mode                                                 */
#define RMU_SRSTFLG_STOPACKERSTRCD_1           1U      /* 1 : Reset caused by peripheral failure to acknowledge attempt
                                                     to enter stop mode                                                 */


/* ========================================================  RSTIEN  ========================================================= */
/* =============================================  RMU RSTIEN RSTDTIMCFG [0..1]  ============================================== */
                                  /* RMU_RSTIEN_RSTDTIMCFG                                              */
#define RMU_RSTIEN_RSTDTIMCFG_00               0U      /* 00 : 10 LPO cycles                                                 */
#define RMU_RSTIEN_RSTDTIMCFG_01               1U      /* 01 : 34 LPO cycles                                                 */
#define RMU_RSTIEN_RSTDTIMCFG_10               2U      /* 10 : 130 LPO cycles                                                */
#define RMU_RSTIEN_RSTDTIMCFG_11               3U      /* 11 : 514 LPO cycles                                                */

/* ===============================================  RMU RSTIEN CLKLIEN [2..2]  =============================================== */
                                  /* RMU_RSTIEN_CLKLIEN                                                 */
#define RMU_RSTIEN_CLKLIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_CLKLIEN_1                   1U      /* 1 : Interrupt enabled.                                             */


/* ==============================================  RMU RSTIEN LOCKLIEN [3..3]  =============================================== */
                                 /* RMU_RSTIEN_LOCKLIEN                                                */
#define RMU_RSTIEN_LOCKLIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_LOCKLIEN_1                  1U      /* 1 : Interrupt enabled.                                             */

/* ================================================  RMU RSTIEN WDTIEN [5..5]  ================================================ */
                                  /* RMU_RSTIEN_WDTIEN                                                   */
#define RMU_RSTIEN_WDTIEN_0                     0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_WDTIEN_1                     1U      /* 1 : Interrupt enabled.                                             */


/* ===============================================  RMU RSTIEN EXTPIEN [6..6]  =============================================== */
                                   /* RMU_RSTIEN_EXTPIEN                                                 */
#define RMU_RSTIEN_EXTPIEN_0                   0U      /* 0 : Reset not caused by external reset pin                         */
#define RMU_RSTIEN_EXTPIEN_1                   1U      /* 1 : Reset caused by external reset pin                             */


/* ================================================  RMU RSTIEN GIEN [7..7]  ================================================= */
                                  /* RMU_RSTIEN_GIEN                                                    */
#define RMU_RSTIEN_GIEN_0                      0U      /* 0 : All interrupt sources disabled.                                */
#define RMU_RSTIEN_GIEN_1                      1U      /* 1 : All interrupt sources enabled. Note that the individual
                                                     interrupt-enable bits still need to be set to generate
                                                     interrupts.                                                        */


/* ===============================================  RMU RSTIEN JTAGIEN [8..8]  =============================================== */
                                  /* RMU_RSTIEN_JTAGIEN                                                 */
#define RMU_RSTIEN_JTAGIEN_0                   0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_JTAGIEN_1                   1U      /* 1 : Interrupt enabled.                                             */


/* ==============================================  RMU RSTIEN CLOCKIEN [9..9]  =============================================== */
                                  /* RMU_RSTIEN_CLOCKIEN                                                */
#define RMU_RSTIEN_CLOCKIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_CLOCKIEN_1                  1U      /* 1 : Interrupt enabled.                                             */


/* ===============================================  RMU RSTIEN SWIEN [10..10]  =============================================== */
                                  /* RMU_RSTIEN_SWIEN                                                   */
#define RMU_RSTIEN_SWIEN_0                     0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_SWIEN_1                     1U      /* 1 : Interrupt enabled.                                             */


/* =============================================  RMU RSTIEN SRSTREQEN [11..11]  ============================================= */
                                  /* RMU_RSTIEN_SRSTREQEN                                               */
#define RMU_RSTIEN_SRSTREQEN_0                 0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_SRSTREQEN_1                 1U      /* 1 : Interrupt enabled.                                             */


/* =============================================  RMU RSTIEN SACKEIEN [13..13]  ============================================== */
                                  /* RMU_RSTIEN_SACKEIEN                                                */
#define RMU_RSTIEN_SACKEIEN_0                  0U      /* 0 : Interrupt disabled.                                            */
#define RMU_RSTIEN_SACKEIEN_1                  1U      /* 1 : Interrupt enabled.                                             */




/* =========================================================================================================================== */
/* ================                                           GPIO                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  PLLO  ========================================================== */
/* =========================================================  PLLOS  ========================================================= */
/* =========================================================  PLLOC  ========================================================= */
/* =========================================================  PLLOT  ========================================================= */
/* =========================================================  PLLI  ========================================================== */
/* ========================================================  PLLTDS  ========================================================= */
/* =========================================================  PLLID  ========================================================= */



/* =========================================================================================================================== */
/* ================                                          APM32_SCB                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  ACTLR  ========================================================= */
/* =========================================================  CPUID  ========================================================= */
/* =========================================================  ICSR  ========================================================== */
/* ============================================  APM32_SCB ICSR RETTOBASE [11..11]  ============================================ */
                                  /* APM32_SCB_ICSR_RETTOBASE                                             */
#define APM32_SCB_ICSR_RETTOBASE_0               0U      /* 0 : there are preempted active exceptions to execute               */
#define APM32_SCB_ICSR_RETTOBASE_1               1U      /* 1 : there are no active exceptions  or the currently-executing
                                                     exception is the only active exception                             */


/* ===========================================  APM32_SCB ICSR ISRPENDING [22..22]  ============================================ */
                                   /* APM32_SCB_ICSR_ISRPENDING                                            */
#define APM32_SCB_ICSR_ISRPENDING_0              0U      /* 0 : interrupt not pending                                          */
#define APM32_SCB_ICSR_ISRPENDING_1              1U      /* 1 : interrupt pending                                              */


/* ===========================================  APM32_SCB ICSR ISRPREEMPT [23..23]  ============================================ */
                                  /* APM32_SCB_ICSR_ISRPREEMPT                                            */
#define APM32_SCB_ICSR_ISRPREEMPT_0              0U      /* 0 : Will not service                                               */
#define APM32_SCB_ICSR_ISRPREEMPT_1              1U      /* 1 : Will service a pending exception                               */


/* ============================================  APM32_SCB ICSR PENDSTCLR [25..25]  ============================================ */
                                   /* APM32_SCB_ICSR_PENDSTCLR                                             */
#define APM32_SCB_ICSR_PENDSTCLR_0               0U      /* 0 : no effect                                                      */
#define APM32_SCB_ICSR_PENDSTCLR_1               1U      /* 1 : removes the pending state from the SysTick exception           */


/* ============================================  APM32_SCB ICSR PENDSTSET [26..26]  ============================================ */
                                  /* APM32_SCB_ICSR_PENDSTSET                                             */
#define APM32_SCB_ICSR_PENDSTSET_0               0U      /* 0 : write: no effect; read: SysTick exception is not pending       */
#define APM32_SCB_ICSR_PENDSTSET_1               1U      /* 1 : write: changes SysTick exception state to pending; read:
                                                     SysTick exception is pending                                       */


/* ============================================  APM32_SCB ICSR PENDSVCLR [27..27]  ============================================ */
                                   /* APM32_SCB_ICSR_PENDSVCLR                                             */
#define APM32_SCB_ICSR_PENDSVCLR_0               0U      /* 0 : no effect                                                      */
#define APM32_SCB_ICSR_PENDSVCLR_1               1U      /* 1 : removes the pending state from the PendSV exception            */


/* ============================================  APM32_SCB ICSR PENDSVSET [28..28]  ============================================ */
                                   /* APM32_SCB_ICSR_PENDSVSET                                             */
#define APM32_SCB_ICSR_PENDSVSET_0               0U      /* 0 : write: no effect; read: PendSV exception is not pending        */
#define APM32_SCB_ICSR_PENDSVSET_1               1U      /* 1 : write: changes PendSV exception state to pending; read:
                                                     PendSV exception is pending                                        */


/* ===========================================  APM32_SCB ICSR NMIPENDSET [31..31]  ============================================ */
                                  /* APM32_SCB_ICSR_NMIPENDSET                                            */
#define APM32_SCB_ICSR_NMIPENDSET_0              0U      /* 0 : write: no effect; read: NMI exception is not pending           */
#define APM32_SCB_ICSR_NMIPENDSET_1              1U      /* 1 : write: changes NMI exception state to pending; read: NMI
                                                     exception is pending                                               */


/* =========================================================  VTOR  ========================================================== */
/* =========================================================  AIRCR  ========================================================= */
/* ===========================================  APM32_SCB AIRCR SYSRESETREQ [2..2]  ============================================ */
                                  /* APM32_SCB_AIRCR_SYSRESETREQ                                          */
#define APM32_SCB_AIRCR_SYSRESETREQ_0            0U      /* 0 : no system reset request                                        */
#define APM32_SCB_AIRCR_SYSRESETREQ_1            1U      /* 1 : asserts a signal to the outer system that requests a reset     */


/* ===========================================  APM32_SCB AIRCR ENDIANNESS [15..15]  =========================================== */
                                   /* APM32_SCB_AIRCR_ENDIANNESS                                           */
#define APM32_SCB_AIRCR_ENDIANNESS_0             0U      /* 0 : Little-endian                                                  */
#define APM32_SCB_AIRCR_ENDIANNESS_1             1U      /* 1 : Big-endian                                                     */


/* ==========================================================  SCR  ========================================================== */
/* ============================================  APM32_SCB SCR SLEEPONEXIT [1..1]  ============================================= */
                                  /* APM32_SCB_SCR_SLEEPONEXIT                                            */
#define APM32_SCB_SCR_SLEEPONEXIT_0              0U      /* 0 : o not sleep when returning to Thread mode                      */
#define APM32_SCB_SCR_SLEEPONEXIT_1              1U      /* 1 : enter sleep  or deep sleep  on return from an ISR              */


/* =============================================  APM32_SCB SCR SLEEPDEEP [2..2]  ============================================== */
                                   /* APM32_SCB_SCR_SLEEPDEEP                                              */
#define APM32_SCB_SCR_SLEEPDEEP_0                0U      /* 0 : sleep                                                          */
#define APM32_SCB_SCR_SLEEPDEEP_1                1U      /* 1 : deep sleep                                                     */


/* =============================================  APM32_SCB SCR SEVONPEND [4..4]  ============================================== */
                                   /* APM32_SCB_SCR_SEVONPEND                                              */
#define APM32_SCB_SCR_SEVONPEND_0                0U      /* 0 : only enabled interrupts or events can wakeup the processor
                                                     disabled interrupts are excluded                                   */
#define APM32_SCB_SCR_SEVONPEND_1                1U      /* 1 : enabled events and all interrupts  including disabled interrupts
                                                     can wakeup the processor                                           */


/* ==========================================================  CCR  ========================================================== */
/* ===========================================  APM32_SCB CCR NONBASETHRDENA [0..0]  =========================================== */
                                 /* APM32_SCB_CCR_NONBASETHRDENA                                         */
#define APM32_SCB_CCR_NONBASETHRDENA_0           0U      /* 0 : processor can enter Thread mode only when no exception is
                                                     active                                                             */
#define APM32_SCB_CCR_NONBASETHRDENA_1           1U      /* 1 : processor can enter Thread mode from any level under the
                                                     control of an EXC_RETURN value                                     */


/* ============================================  APM32_SCB CCR USERSETMPEND [1..1]  ============================================ */
                                  /* APM32_SCB_CCR_USERSETMPEND                                           */
#define APM32_SCB_CCR_USERSETMPEND_0             0U      /* 0 : disable                                                        */
#define APM32_SCB_CCR_USERSETMPEND_1             1U      /* 1 : enable                                                         */


/* ============================================  APM32_SCB CCR UNALIGN_TRP [3..3]  ============================================= */
                                   /* APM32_SCB_CCR_UNALIGN_TRP                                            */
#define APM32_SCB_CCR_UNALIGN_TRP_0              0U      /* 0 : do not trap unaligned halfword and word accesses               */
#define APM32_SCB_CCR_UNALIGN_TRP_1              1U      /* 1 : trap unaligned halfword and word accesses                      */

/* =============================================  APM32_SCB CCR DIV_0_TRP [4..4]  ============================================== */
                                  /* APM32_SCB_CCR_DIV_0_TRP                                              */
#define APM32_SCB_CCR_DIV_0_TRP_0                0U      /* 0 : do not trap divide by 0                                        */
#define APM32_SCB_CCR_DIV_0_TRP_1                1U      /* 1 : trap divide by 0                                               */


/* =============================================  APM32_SCB CCR BFHFNMIGN [8..8]  ============================================== */
                                  /* APM32_SCB_CCR_BFHFNMIGN                                              */
#define APM32_SCB_CCR_BFHFNMIGN_0                0U      /* 0 : data bus faults caused by load and store instructions cause
                                                     a lock-up                                                          */
#define APM32_SCB_CCR_BFHFNMIGN_1                1U      /* 1 : handlers running at priority -1 and -2 ignore data bus faults
                                                     caused by load and store instructions                              */


/* ==============================================  APM32_SCB CCR STKALIGN [9..9]  ============================================== */
                                  /* APM32_SCB_CCR_STKALIGN                                               */
#define APM32_SCB_CCR_STKALIGN_0                 0U      /* 0 : 4-byte aligned                                                 */
#define APM32_SCB_CCR_STKALIGN_1                 1U      /* 1 : 8-byte aligned                                                 */


/* =========================================================  SHPR1  ========================================================= */
/* =========================================================  SHPR2  ========================================================= */
/* =========================================================  SHPR3  ========================================================= */
/* =========================================================  SHCSR  ========================================================= */
/* ===========================================  APM32_SCB SHCSR MEMFAULTACT [0..0]  ============================================ */
                                   /* APM32_SCB_SHCSR_MEMFAULTACT                                          */
#define APM32_SCB_SHCSR_MEMFAULTACT_0            0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_MEMFAULTACT_1            1U      /* 1 : exception is active                                            */


/* ===========================================  APM32_SCB SHCSR BUSFAULTACT [1..1]  ============================================ */
                                  /* APM32_SCB_SHCSR_BUSFAULTACT                                          */
#define APM32_SCB_SHCSR_BUSFAULTACT_0            0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_BUSFAULTACT_1            1U      /* 1 : exception is active                                            */


/* ===========================================  APM32_SCB SHCSR USGFAULTACT [3..3]  ============================================ */
                                  /* APM32_SCB_SHCSR_USGFAULTACT                                          */
#define APM32_SCB_SHCSR_USGFAULTACT_0            0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_USGFAULTACT_1            1U      /* 1 : exception is active                                            */


/* ============================================  APM32_SCB SHCSR SVCALLACT [7..7]  ============================================= */
                                  /* APM32_SCB_SHCSR_SVCALLACT                                            */
#define APM32_SCB_SHCSR_SVCALLACT_0              0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_SVCALLACT_1              1U      /* 1 : exception is active                                            */


/* ============================================  APM32_SCB SHCSR MONITORACT [8..8]  ============================================ */
                                 /* APM32_SCB_SHCSR_MONITORACT                                           */
#define APM32_SCB_SHCSR_MONITORACT_0             0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_MONITORACT_1             1U      /* 1 : exception is active                                            */


/* ===========================================  APM32_SCB SHCSR PENDSVACT [10..10]  ============================================ */
                                  /* APM32_SCB_SHCSR_PENDSVACT                                            */
#define APM32_SCB_SHCSR_PENDSVACT_0              0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_PENDSVACT_1              1U      /* 1 : exception is active                                            */


/* ===========================================  APM32_SCB SHCSR SYSTICKACT [11..11]  =========================================== */
                                  /* APM32_SCB_SHCSR_SYSTICKACT                                           */
#define APM32_SCB_SHCSR_SYSTICKACT_0             0U      /* 0 : exception is not active                                        */
#define APM32_SCB_SHCSR_SYSTICKACT_1             1U      /* 1 : exception is active                                            */


/* =========================================  APM32_SCB SHCSR USGFAULTPENDED [12..12]  ========================================= */
                                  /* APM32_SCB_SHCSR_USGFAULTPENDED                                       */
#define APM32_SCB_SHCSR_USGFAULTPENDED_0         0U      /* 0 : exception is not pending                                       */
#define APM32_SCB_SHCSR_USGFAULTPENDED_1         1U      /* 1 : exception is pending                                           */


/* =========================================  APM32_SCB SHCSR MEMFAULTPENDED [13..13]  ========================================= */
                                  /* APM32_SCB_SHCSR_MEMFAULTPENDED                                       */
#define APM32_SCB_SHCSR_MEMFAULTPENDED_0         0U      /* 0 : exception is not pending                                       */
#define APM32_SCB_SHCSR_MEMFAULTPENDED_1         1U      /* 1 : exception is pending                                           */


/* =========================================  APM32_SCB SHCSR BUSFAULTPENDED [14..14]  ========================================= */
                                 /* APM32_SCB_SHCSR_BUSFAULTPENDED                                       */
#define APM32_SCB_SHCSR_BUSFAULTPENDED_0         0U      /* 0 : exception is not pending                                       */
#define APM32_SCB_SHCSR_BUSFAULTPENDED_1         1U      /* 1 : exception is pending                                           */


/* ==========================================  APM32_SCB SHCSR SVCALLPENDED [15..15]  ========================================== */
                                  /* APM32_SCB_SHCSR_SVCALLPENDED                                         */
#define APM32_SCB_SHCSR_SVCALLPENDED_0           0U      /* 0 : exception is not pending                                       */
#define APM32_SCB_SHCSR_SVCALLPENDED_1           1U      /* 1 : exception is pending                                           */


/* ==========================================  APM32_SCB SHCSR MEMFAULTENA [16..16]  =========================================== */
                                   /* APM32_SCB_SHCSR_MEMFAULTENA                                          */
#define APM32_SCB_SHCSR_MEMFAULTENA_0            0U      /* 0 : disable the exception                                          */
#define APM32_SCB_SHCSR_MEMFAULTENA_1            1U      /* 1 : enable the exception                                           */


/* ==========================================  APM32_SCB SHCSR BUSFAULTENA [17..17]  =========================================== */
                                   /* APM32_SCB_SHCSR_BUSFAULTENA                                          */
#define APM32_SCB_SHCSR_BUSFAULTENA_0            0U      /* 0 : disable the exception                                          */
#define APM32_SCB_SHCSR_BUSFAULTENA_1            1U      /* 1 : enable the exception                                           */


/* ==========================================  APM32_SCB SHCSR USGFAULTENA [18..18]  =========================================== */
                                   /* APM32_SCB_SHCSR_USGFAULTENA                                          */
#define APM32_SCB_SHCSR_USGFAULTENA_0            0U      /* 0 : disable the exception                                          */
#define APM32_SCB_SHCSR_USGFAULTENA_1            1U      /* 1 : enable the exception                                           */


/* =========================================================  CFSR  ========================================================== */
/* =============================================  APM32_SCB CFSR IACCVIOL [0..0]  ============================================== */
                                  /* APM32_SCB_CFSR_IACCVIOL                                              */
#define APM32_SCB_CFSR_IACCVIOL_0                0U      /* 0 : no instruction access violation fault                          */
#define APM32_SCB_CFSR_IACCVIOL_1                1U      /* 1 : the processor attempted an instruction fetch from a location
                                                     that does not permit execution                                     */


/* =============================================  APM32_SCB CFSR DACCVIOL [1..1]  ============================================== */
                                  /* APM32_SCB_CFSR_DACCVIOL                                              */
#define APM32_SCB_CFSR_DACCVIOL_0                0U      /* 0 : no data access violation fault                                 */
#define APM32_SCB_CFSR_DACCVIOL_1                1U      /* 1 : the processor attempted a load or store at a location that
                                                     does not permit the operation                                      */


/* =============================================  APM32_SCB CFSR MUNSTKERR [3..3]  ============================================= */
                                  /* APM32_SCB_CFSR_MUNSTKERR                                             */
#define APM32_SCB_CFSR_MUNSTKERR_0               0U      /* 0 : no unstacking fault                                            */
#define APM32_SCB_CFSR_MUNSTKERR_1               1U      /* 1 : unstack for an exception return has caused one or more access
                                                     violations                                                         */


/* ==============================================  APM32_SCB CFSR MSTKERR [4..4]  ============================================== */
                                   /* APM32_SCB_CFSR_MSTKERR                                               */
#define APM32_SCB_CFSR_MSTKERR_0                 0U      /* 0 : no stacking fault                                              */
#define APM32_SCB_CFSR_MSTKERR_1                 1U      /* 1 : stacking for an exception entry has caused one or more access
                                                     violations                                                         */


/* ==============================================  APM32_SCB CFSR MLSPERR [5..5]  ============================================== */
                                 /* APM32_SCB_CFSR_MLSPERR                                               */
#define APM32_SCB_CFSR_MLSPERR_0                 0U      /* 0 : No MemManage fault occurred during floating-point lazy state
                                                     preservation                                                       */
#define APM32_SCB_CFSR_MLSPERR_1                 1U      /* 1 : A MemManage fault occurred during floating-point lazy state
                                                     preservation                                                       */


/* =============================================  APM32_SCB CFSR MMARVALID [7..7]  ============================================= */
                                  /* APM32_SCB_CFSR_MMARVALID                                             */
#define APM32_SCB_CFSR_MMARVALID_0               0U      /* 0 : value in MMAR is not a valid fault address                     */
#define APM32_SCB_CFSR_MMARVALID_1               1U      /* 1 : MMAR holds a valid fault address                               */


/* ==============================================  APM32_SCB CFSR IBUSERR [8..8]  ============================================== */
                                  /* APM32_SCB_CFSR_IBUSERR                                               */
#define APM32_SCB_CFSR_IBUSERR_0                 0U      /* 0 : no instruction bus error                                       */
#define APM32_SCB_CFSR_IBUSERR_1                 1U      /* 1 : instruction bus error                                          */


/* =============================================  APM32_SCB CFSR PRECISERR [9..9]  ============================================= */
                                   /* APM32_SCB_CFSR_PRECISERR                                             */
#define APM32_SCB_CFSR_PRECISERR_0               0U      /* 0 : no precise data bus error                                      */
#define APM32_SCB_CFSR_PRECISERR_1               1U      /* 1 : a data bus error has occurred  and the PC value stacked
                                                     for the exception return points to the instruction that
                                                     caused the fault                                                   */


/* ===========================================  APM32_SCB CFSR IMPRECISERR [10..10]  =========================================== */
                                  /* APM32_SCB_CFSR_IMPRECISERR                                           */
#define APM32_SCB_CFSR_IMPRECISERR_0             0U      /* 0 : no imprecise data bus error                                    */
#define APM32_SCB_CFSR_IMPRECISERR_1             1U      /* 1 : a data bus error has occurred  but the return address in
                                                     the stack frame is not related to the instruction that
                                                     caused the error                                                   */


/* ============================================  APM32_SCB CFSR UNSTKERR [11..11]  ============================================= */
                                  /* APM32_SCB_CFSR_UNSTKERR                                              */
#define APM32_SCB_CFSR_UNSTKERR_0                0U      /* 0 : no unstacking fault                                            */
#define APM32_SCB_CFSR_UNSTKERR_1                1U     /* 1 : unstack for an exception return has caused one or more BusFaults*/


/* =============================================  APM32_SCB CFSR STKERR [12..12]  ============================================== */
                                   /* APM32_SCB_CFSR_STKERR                                                */
#define APM32_SCB_CFSR_STKERR_0                  0U      /* 0 : no stacking fault                                              */
#define APM32_SCB_CFSR_STKERR_1                  1U     /* 1 : stacking for an exception entry has caused one or more BusFaults*/


/* =============================================  APM32_SCB CFSR LSPERR [13..13]  ============================================== */
                                   /* APM32_SCB_CFSR_LSPERR                                                */
#define APM32_SCB_CFSR_LSPERR_0                  0U  /* 0 : No bus fault occurred during floating-point lazy state preservation*/
#define APM32_SCB_CFSR_LSPERR_1                  1U  /* 1 : A bus fault occurred during floating-point lazy state preservation */


/* ============================================  APM32_SCB CFSR BFARVALID [15..15]  ============================================ */
                                  /* APM32_SCB_CFSR_BFARVALID                                             */
#define APM32_SCB_CFSR_BFARVALID_0               0      /* 0 : value in BFAR is not a valid fault address                      */
#define APM32_SCB_CFSR_BFARVALID_1               1      /* 1 : BFAR holds a valid fault address                                */


/* ===========================================  APM32_SCB CFSR UNDEFINSTR [16..16]  ============================================ */
                                   /* APM32_SCB_CFSR_UNDEFINSTR                                            */
#define APM32_SCB_CFSR_UNDEFINSTR_0               0U     /* 0 : no undefined instruction UsageFault                            */
#define APM32_SCB_CFSR_UNDEFINSTR_1               1U     /* 1 : the processor has attempted to execute an undefined instruction*/


/* ============================================  APM32_SCB CFSR INVSTATE [17..17]  ============================================= */
                                  /* APM32_SCB_CFSR_INVSTATE                                              */
#define APM32_SCB_CFSR_INVSTATE_0                 0U     /* 0 : no invalid state UsageFault                                    */
#define APM32_SCB_CFSR_INVSTATE_1                 1U     /* 1 : the processor has attempted to execute an instruction that
                                                     makes illegal use of the EPSR                                      */


/* ==============================================  APM32_SCB CFSR INVPC [18..18]  ============================================== */
                                  /* APM32_SCB_CFSR_INVPC                                                 */
#define APM32_SCB_CFSR_INVPC_0                    0U     /* 0 : no invalid PC load UsageFault                                  */
#define APM32_SCB_CFSR_INVPC_1                    1U      /* 1 : the processor has attempted an illegal load of EXC_RETURN
                                                     to the PC                                                          */


/* ==============================================  APM32_SCB CFSR NOCP [19..19]  =============================================== */
                                   /* APM32_SCB_CFSR_NOCP                                                  */
#define APM32_SCB_CFSR_NOCP_0                     0U     /* 0 : no UsageFault caused by attempting to access a coprocessor     */
#define APM32_SCB_CFSR_NOCP_1                     1U     /* 1 : the processor has attempted to access a coprocessor            */


/* ============================================  APM32_SCB CFSR UNALIGNED [24..24]  ============================================ */
                                  /* APM32_SCB_CFSR_UNALIGNED                                             */
#define APM32_SCB_CFSR_UNALIGNED_0                0U      /* 0 : no unaligned access fault  or unaligned access trapping
                                                     not enabled                                                        */
#define APM32_SCB_CFSR_UNALIGNED_1                1U     /* 1 : the processor has made an unaligned memory access              */


/* ============================================  APM32_SCB CFSR DIVBYZERO [25..25]  ============================================ */
                                   /* APM32_SCB_CFSR_DIVBYZERO                                             */
#define APM32_SCB_CFSR_DIVBYZERO_0                0U      /* 0 : no divide by zero fault  or divide by zero trapping not
                                                     enabled                                                            */
#define APM32_SCB_CFSR_DIVBYZERO_1                1U      /* 1 : the processor has executed an SDIV or UDIV instruction with
                                                     a divisor of 0                                                     */


/* =========================================================  HFSR  ========================================================== */
/* ==============================================  APM32_SCB HFSR VECTTBL [1..1]  ============================================== */
                                   /* APM32_SCB_HFSR_VECTTBL                                               */
#define APM32_SCB_HFSR_VECTTBL_0                  0U     /* 0 : no BusFault on vector table read                               */
#define APM32_SCB_HFSR_VECTTBL_1                  1U     /* 1 : BusFault on vector table read                                  */


/* =============================================  APM32_SCB HFSR FORCED [30..30]  ============================================== */
                                  /* APM32_SCB_HFSR_FORCED                                                */
#define APM32_SCB_HFSR_FORCED_0                   0U     /* 0 : no forced HardFault                                            */
#define APM32_SCB_HFSR_FORCED_1                   1U     /* 1 : forced HardFault                                               */


/* =========================================================  DFSR  ========================================================== */
/* ==============================================  APM32_SCB DFSR HALTED [0..0]  =============================================== */
                                  /* APM32_SCB_DFSR_HALTED                                                */
#define APM32_SCB_DFSR_HALTED_0                   0U     /* 0 : No active halt request debug event                             */
#define APM32_SCB_DFSR_HALTED_1                   1U     /* 1 : Halt request debug event active                                */


/* ===============================================  APM32_SCB DFSR BKPT [1..1]  ================================================ */
                                  /* APM32_SCB_DFSR_BKPT                                                  */
#define APM32_SCB_DFSR_BKPT_0                     0U     /* 0 : No current breakpoint debug event                              */
#define APM32_SCB_DFSR_BKPT_1                     1U     /* 1 : At least one current breakpoint debug event                    */


/* ==============================================  APM32_SCB DFSR DWTTRAP [2..2]  ============================================== */
                                   /* APM32_SCB_DFSR_DWTTRAP                                               */
#define APM32_SCB_DFSR_DWTTRAP_0                  0U      /* 0 : No current debug events generated by the DWT                  */
#define APM32_SCB_DFSR_DWTTRAP_1                  1U      /* 1 : At least one current debug event generated by the DWT         */


/* ==============================================  APM32_SCB DFSR VCATCH [3..3]  =============================================== */
                                  /* APM32_SCB_DFSR_VCATCH                                                       */
#define APM32_SCB_DFSR_VCATCH_0                   0U      /* 0 : No Vector catch triggered                                     */
#define APM32_SCB_DFSR_VCATCH_1                   1U      /* 1 : Vector catch triggered                                         */


/* =============================================  APM32_SCB DFSR EXTERNAL [4..4]  ============================================== */
                                   /* APM32_SCB_DFSR_EXTERNAL                                              */
#define APM32_SCB_DFSR_EXTERNAL_0                 0U      /* 0 : No EDBGRQ debug event                                          */
#define APM32_SCB_DFSR_EXTERNAL_1                 1U      /* 1 : EDBGRQ debug event                                             */


/* =========================================================  MMFAR  ========================================================= */
/* =========================================================  BFAR  ========================================================== */
/* =========================================================  AFSR  ========================================================== */
/* =========================================================  CPACR  ========================================================= */
/* ==============================================  APM32_SCB CPACR CP10 [20..21]  ============================================== */
                                   /* APM32_SCB_CPACR_CP10                                                 */
#define APM32_SCB_CPACR_CP10_00                   0U    /* 00 : Access denied. Any attempted access generates a NOCP UsageFault*/
#define APM32_SCB_CPACR_CP10_01                   1U      /* 01 : Privileged access only. An unprivileged access generates
                                                     a NOCP fault.                                                      */
#define APM32_SCB_CPACR_CP10_10                   2U      /* 10 : Reserved. The result of any access is UNPREDICTABLE.          */
#define APM32_SCB_CPACR_CP10_11                   3U      /* 11 : Full access.                                                  */
 /* ==============================================  APM32_SCB CPACR CP11 [22..23]  ============================================== */
                                  /* APM32_SCB_CPACR_CP11                                                 */
#define APM32_SCB_CPACR_CP11_00                   0U   /* 00 : Access denied. Any attempted access generates a NOCP UsageFault  */
#define APM32_SCB_CPACR_CP11_01                   1U      /* 01 : Privileged access only. An unprivileged access generates
                                                     a NOCP fault.                                                      */
#define APM32_SCB_CPACR_CP11_10                   2U      /* 10 : Reserved. The result of any access is UNPREDICTABLE.          */
#define APM32_SCB_CPACR_CP11_11                   3U      /* 11 : Full access.                                                  */


/* =========================================================  FPCCR  ========================================================= */
/* ==============================================  APM32_SCB FPCCR LSPACT [0..0]  ============================================== */
                                 /* APM32_SCB_FPCCR_LSPACT                                               */
#define APM32_SCB_FPCCR_LSPACT_0                  0U      /* 0 : Lazy state preservation is not active.                         */
#define APM32_SCB_FPCCR_LSPACT_1                  1U      /* 1 : Lazy state preservation is active. floating-point stack
                                                     frame has been allocated but saving state to it has been
                                                     deferred.                                                                 */


/* ===============================================  APM32_SCB FPCCR USER [1..1]  =============================================== */
                                  /* APM32_SCB_FPCCR_USER                                                        */
#define APM32_SCB_FPCCR_USER_0                    0U      /* 0 : Privilege level was not user when the floating-point stack
                                                     frame was allocated.                                                      */
#define APM32_SCB_FPCCR_USER_1                    1U      /* 1 : Privilege level was user when the floating-point stack frame
                                                     was allocated.                                                            */


/* ==============================================  APM32_SCB FPCCR THREAD [3..3]  ============================================== */
                                  /* APM32_SCB_FPCCR_THREAD                                                      */
#define APM32_SCB_FPCCR_THREAD_0                  0U      /* 0 : Mode was not Thread Mode when the floating-point stack frame
                                                     was allocated.                                                            */
#define APM32_SCB_FPCCR_THREAD_1                  1U      /* 1 : Mode was Thread Mode when the floating-point stack frame
                                                     was allocated.                                                            */


/* ==============================================  APM32_SCB FPCCR HFRDY [4..4]  =============================================== */
                                  /* APM32_SCB_FPCCR_HFRDY                                                       */
#define APM32_SCB_FPCCR_HFRDY_0                   0U      /* 0 : Priority did not permit setting the HardFault handler to
                                                     the pending state when the floating-point stack frame was
                                                     allocated.                                                                */
#define APM32_SCB_FPCCR_HFRDY_1                   1U      /* 1 : Priority permitted setting the HardFault handler to the
                                                     pending state when the floating-point stack frame was allocated.          */


/* ==============================================  APM32_SCB FPCCR MMRDY [5..5]  =============================================== */
                                /* APM32_SCB_FPCCR_MMRDY                                                       */
#define APM32_SCB_FPCCR_MMRDY_0                   0U      /* 0 : MemManage is disabled or priority did not permit setting
                                                     the MemManage handler to the pending state when the floating-point
                                                     stack frame was allocated.                                                */
#define APM32_SCB_FPCCR_MMRDY_1                   1U      /* 1 : MemManage is enabled and priority permitted setting the
                                                     MemManage handler to the pending state when the floating-point
                                                     stack frame was allocated.                                                */


/* ==============================================  APM32_SCB FPCCR BFRDY [6..6]  =============================================== */
                                  /* APM32_SCB_FPCCR_BFRDY                                                       */
#define APM32_SCB_FPCCR_BFRDY_0                   0U      /* 0 : BusFault is disabled or priority did not permit setting
                                                     the BusFault handler to the pending state when the floating-point
                                                     stack frame was allocated.                                                */
#define APM32_SCB_FPCCR_BFRDY_1                   1U      /* 1 : BusFault is disabled or priority did not permit setting
                                                     the BusFault handler to the pending state when the floating-point
                                                     stack frame was allocated.                                                */


/* ==============================================  APM32_SCB FPCCR MONRDY [8..8]  ============================================== */
                                   /* APM32_SCB_FPCCR_MONRDY                                                      */
#define APM32_SCB_FPCCR_MONRDY_0                  0U      /* 0 : DebugMonitor is disabled or priority did not permit setting
                                                     MON_PEND when the floating-point stack frame was allocated.               */
#define APM32_SCB_FPCCR_MONRDY_1                  1U      /* 1 : DebugMonitor is enabled and priority permits setting MON_PEND
                                                     when the floating-point stack frame was allocated.                        */


/* =============================================  APM32_SCB FPCCR LSPEN [30..30]  ============================================== */
                                  /* APM32_SCB_FPCCR_LSPEN                                                       */
#define APM32_SCB_FPCCR_LSPEN_0                   0U      /* 0 : Disable automatic lazy state preservation for floating-point
                                                     context.                                                                  */
#define APM32_SCB_FPCCR_LSPEN_1                   1U      /* 1 : Enable automatic lazy state preservation for floating-point
                                                     context.                                                                  */


/* =============================================  APM32_SCB FPCCR ASPEN [31..31]  ============================================== */
                                  /* APM32_SCB_FPCCR_ASPEN                                                       */
#define APM32_SCB_FPCCR_ASPEN_0                   0U      /* 0 : Disable CONTROL2 setting on execution of a floating-point
                                                     instruction.                                                              */
#define APM32_SCB_FPCCR_ASPEN_1                   1U      /* 1 : Enable CONTROL2 setting on execution of a floating-point
                                                     instruction.                                                              */


/* =========================================================  FPCAR  ========================================================= */
/* ========================================================  FPDSCR  ========================================================= */
/* =============================================  APM32_SCB FPDSCR RMode [22..23]  ============================================= */
                                 /* APM32_SCB_FPDSCR_RMode                                                      */
#define APM32_SCB_FPDSCR_RMode_00                 0U      /* 00 : Round to Nearest (RN) mode                                    */
#define APM32_SCB_FPDSCR_RMode_01                 1U      /* 01 : Round towards Plus Infinity (RP) mode.                        */
#define APM32_SCB_FPDSCR_RMode_10                 2U      /* 10 : Round towards Minus Infinity (RM) mode.                       */
#define APM32_SCB_FPDSCR_RMode_11                 3U      /* 11 : Round towards Zero (RZ) mode.                                 */


/* ==============================================  APM32_SCB FPDSCR FZ [24..24]  =============================================== */
                                  /* APM32_SCB_FPDSCR_FZ                                                  */
#define APM32_SCB_FPDSCR_FZ_0                    0U      /* 0 : Flush-to-zero mode disabled. Behavior of the floating-point
                                                     system is fully compliant with the IEEE 754 standard.              */
#define APM32_SCB_FPDSCR_FZ_1                    1U      /* 1 : Flush-to-zero mode enabled.                                    */


/* ==============================================  APM32_SCB FPDSCR DN [25..25]  =============================================== */
                                   /* APM32_SCB_FPDSCR_DN                                                  */
#define APM32_SCB_FPDSCR_DN_0                    0U      /* 0 : NaN operands propagate through to the output of a floating-point
                                                     operation.                                                         */
#define APM32_SCB_FPDSCR_DN_1                    1U      /* 1 : Any operation involving one or more NaNs returns the Default
                                                     NaN.                                                               */


/* ==============================================  APM32_SCB FPDSCR AHP [26..26]  ============================================== */
                                 /* APM32_SCB_FPDSCR_AHP                                                 */
#define APM32_SCB_FPDSCR_AHP_0                   0U      /* 0 : IEEE half-precision format selected.                           */
#define APM32_SCB_FPDSCR_AHP_1                   1U      /* 1 : Alternative half-precision format selected.                    */




/* =========================================================================================================================== */
/* ================                                        APM32_SysTick                                        ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
/* =============================================  APM32_SysTick CSR ENABLE [0..0]  ============================================= */
                                   /* APM32_SysTick_CSR_ENABLE                                             */
#define APM32_SysTick_CSR_ENABLE_0               0U      /* 0 : counter disabled                                               */
#define APM32_SysTick_CSR_ENABLE_1               1U      /* 1 : counter enabled                                                */

/* ============================================  APM32_SysTick CSR TICKINT [1..1]  ============================================= */
                               /* APM32_SysTick_CSR_TICKINT                                            */
#define APM32_SysTick_CSR_TICKINT_0              0U      /* 0 : counting down to 0 does not assert the SysTick exception
                                                     request                                                            */
#define APM32_SysTick_CSR_TICKINT_1              1U      /* 1 : counting down to 0 asserts the SysTick exception request       */

/* ===========================================  APM32_SysTick CSR CLKSOURCE [2..2]  ============================================ */
                                  /* APM32_SysTick_CSR_CLKSOURCE                                          */
#define APM32_SysTick_CSR_CLKSOURCE_0            0U      /* 0 : external clock                                                 */
#define APM32_SysTick_CSR_CLKSOURCE_1            1U      /* 1 : processor clock                                                */


/* ==========================================================  RVR  ========================================================== */
/* ==========================================================  CVR  ========================================================== */
/* =========================================================  CALIB  ========================================================= */
/* ============================================  APM32_SysTick CALIB SKEW [30..30]  ============================================ */
                                  /* APM32_SysTick_CALIB_SKEW                                             */
#define APM32_SysTick_CALIB_SKEW_0               0U      /* 0 : TENMS value is exact                                           */
#define APM32_SysTick_CALIB_SKEW_1               1U      /* 1 : TENMS value is inexact  or not given                           */


/* ===========================================  APM32_SysTick CALIB NOREF [31..31]  ============================================ */
                                   /* APM32_SysTick_CALIB_NOREF                                            */
#define APM32_SysTick_CALIB_NOREF_0              0U      /* 0 : The reference clock is provided                                */
#define APM32_SysTick_CALIB_NOREF_1              1U      /* 1 : The reference clock is not provided                            */



/* =========================================================================================================================== */
/* ================                                           APM32_NVIC                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  NVICISER0  ======================================================= */
/* =======================================================  NVICISER1  ======================================================= */
/* =======================================================  NVICISER2  ======================================================= */
/* =======================================================  NVICISER3  ======================================================= */
/* =======================================================  NVICISER4  ======================================================= */
/* =======================================================  NVICISER5  ======================================================= */
/* =======================================================  NVICISER6  ======================================================= */
/* =======================================================  NVICISER7  ======================================================= */
/* =======================================================  NVICICER0  ======================================================= */
/* =======================================================  NVICICER1  ======================================================= */
/* =======================================================  NVICICER2  ======================================================= */
/* =======================================================  NVICICER3  ======================================================= */
/* =======================================================  NVICICER4  ======================================================= */
/* =======================================================  NVICICER5  ======================================================= */
/* =======================================================  NVICICER6  ======================================================= */
/* =======================================================  NVICICER7  ======================================================= */
/* =======================================================  NVICISPR0  ======================================================= */
/* =======================================================  NVICISPR1  ======================================================= */
/* =======================================================  NVICISPR2  ======================================================= */
/* =======================================================  NVICISPR3  ======================================================= */
/* =======================================================  NVICISPR4  ======================================================= */
/* =======================================================  NVICISPR5  ======================================================= */
/* =======================================================  NVICISPR6  ======================================================= */
/* =======================================================  NVICISPR7  ======================================================= */
/* =======================================================  NVICICPR0  ======================================================= */
/* =======================================================  NVICICPR1  ======================================================= */
/* =======================================================  NVICICPR2  ======================================================= */
/* =======================================================  NVICICPR3  ======================================================= */
/* =======================================================  NVICICPR4  ======================================================= */
/* =======================================================  NVICICPR5  ======================================================= */
/* =======================================================  NVICICPR6  ======================================================= */
/* =======================================================  NVICICPR7  ======================================================= */
/* =======================================================  NVICIABR0  ======================================================= */
/* =======================================================  NVICIABR1  ======================================================= */
/* =======================================================  NVICIABR2  ======================================================= */
/* =======================================================  NVICIABR3  ======================================================= */
/* =======================================================  NVICIABR4  ======================================================= */
/* =======================================================  NVICIABR5  ======================================================= */
/* =======================================================  NVICIABR6  ======================================================= */
/* =======================================================  NVICIABR7  ======================================================= */
/* ========================================================  NVICIP0  ======================================================== */
/* ========================================================  NVICIP1  ======================================================== */
/* ========================================================  NVICIP2  ======================================================== */
/* ========================================================  NVICIP3  ======================================================== */
/* ========================================================  NVICIP4  ======================================================== */
/* ========================================================  NVICIP5  ======================================================== */
/* ========================================================  NVICIP6  ======================================================== */
/* ========================================================  NVICIP7  ======================================================== */
/* ========================================================  NVICIP8  ======================================================== */
/* ========================================================  NVICIP9  ======================================================== */
/* =======================================================  NVICIP10  ======================================================== */
/* =======================================================  NVICIP11  ======================================================== */
/* =======================================================  NVICIP12  ======================================================== */
/* =======================================================  NVICIP13  ======================================================== */
/* =======================================================  NVICIP14  ======================================================== */
/* =======================================================  NVICIP15  ======================================================== */
/* =======================================================  NVICIP16  ======================================================== */
/* =======================================================  NVICIP17  ======================================================== */
/* =======================================================  NVICIP18  ======================================================== */
/* =======================================================  NVICIP19  ======================================================== */
/* =======================================================  NVICIP20  ======================================================== */
/* =======================================================  NVICIP21  ======================================================== */
/* =======================================================  NVICIP22  ======================================================== */
/* =======================================================  NVICIP23  ======================================================== */
/* =======================================================  NVICIP24  ======================================================== */
/* =======================================================  NVICIP25  ======================================================== */
/* =======================================================  NVICIP26  ======================================================== */
/* =======================================================  NVICIP27  ======================================================== */
/* =======================================================  NVICIP28  ======================================================== */
/* =======================================================  NVICIP29  ======================================================== */
/* =======================================================  NVICIP30  ======================================================== */
/* =======================================================  NVICIP31  ======================================================== */
/* =======================================================  NVICIP32  ======================================================== */
/* =======================================================  NVICIP33  ======================================================== */
/* =======================================================  NVICIP34  ======================================================== */
/* =======================================================  NVICIP35  ======================================================== */
/* =======================================================  NVICIP36  ======================================================== */
/* =======================================================  NVICIP37  ======================================================== */
/* =======================================================  NVICIP38  ======================================================== */
/* =======================================================  NVICIP39  ======================================================== */
/* =======================================================  NVICIP40  ======================================================== */
/* =======================================================  NVICIP41  ======================================================== */
/* =======================================================  NVICIP42  ======================================================== */
/* =======================================================  NVICIP43  ======================================================== */
/* =======================================================  NVICIP44  ======================================================== */
/* =======================================================  NVICIP45  ======================================================== */
/* =======================================================  NVICIP46  ======================================================== */
/* =======================================================  NVICIP47  ======================================================== */
/* =======================================================  NVICIP48  ======================================================== */
/* =======================================================  NVICIP49  ======================================================== */
/* =======================================================  NVICIP50  ======================================================== */
/* =======================================================  NVICIP51  ======================================================== */
/* =======================================================  NVICIP52  ======================================================== */
/* =======================================================  NVICIP53  ======================================================== */
/* =======================================================  NVICIP54  ======================================================== */
/* =======================================================  NVICIP55  ======================================================== */
/* =======================================================  NVICIP56  ======================================================== */
/* =======================================================  NVICIP57  ======================================================== */
/* =======================================================  NVICIP58  ======================================================== */
/* =======================================================  NVICIP59  ======================================================== */
/* =======================================================  NVICIP60  ======================================================== */
/* =======================================================  NVICIP61  ======================================================== */
/* =======================================================  NVICIP62  ======================================================== */
/* =======================================================  NVICIP63  ======================================================== */
/* =======================================================  NVICIP64  ======================================================== */
/* =======================================================  NVICIP65  ======================================================== */
/* =======================================================  NVICIP66  ======================================================== */
/* =======================================================  NVICIP67  ======================================================== */
/* =======================================================  NVICIP68  ======================================================== */
/* =======================================================  NVICIP69  ======================================================== */
/* =======================================================  NVICIP70  ======================================================== */
/* =======================================================  NVICIP71  ======================================================== */
/* =======================================================  NVICIP72  ======================================================== */
/* =======================================================  NVICIP73  ======================================================== */
/* =======================================================  NVICIP74  ======================================================== */
/* =======================================================  NVICIP75  ======================================================== */
/* =======================================================  NVICIP76  ======================================================== */
/* =======================================================  NVICIP77  ======================================================== */
/* =======================================================  NVICIP78  ======================================================== */
/* =======================================================  NVICIP79  ======================================================== */
/* =======================================================  NVICIP80  ======================================================== */
/* =======================================================  NVICIP81  ======================================================== */
/* =======================================================  NVICIP82  ======================================================== */
/* =======================================================  NVICIP83  ======================================================== */
/* =======================================================  NVICIP84  ======================================================== */
/* =======================================================  NVICIP85  ======================================================== */
/* =======================================================  NVICIP86  ======================================================== */
/* =======================================================  NVICIP87  ======================================================== */
/* =======================================================  NVICIP88  ======================================================== */
/* =======================================================  NVICIP89  ======================================================== */
/* =======================================================  NVICIP90  ======================================================== */
/* =======================================================  NVICIP91  ======================================================== */
/* =======================================================  NVICIP92  ======================================================== */
/* =======================================================  NVICIP93  ======================================================== */
/* =======================================================  NVICIP94  ======================================================== */
/* =======================================================  NVICIP95  ======================================================== */
/* =======================================================  NVICIP96  ======================================================== */
/* =======================================================  NVICIP97  ======================================================== */
/* =======================================================  NVICIP98  ======================================================== */
/* =======================================================  NVICIP99  ======================================================== */
/* =======================================================  NVICIP100  ======================================================= */
/* =======================================================  NVICIP101  ======================================================= */
/* =======================================================  NVICIP102  ======================================================= */
/* =======================================================  NVICIP103  ======================================================= */
/* =======================================================  NVICIP104  ======================================================= */
/* =======================================================  NVICIP105  ======================================================= */
/* =======================================================  NVICIP106  ======================================================= */
/* =======================================================  NVICIP107  ======================================================= */
/* =======================================================  NVICIP108  ======================================================= */
/* =======================================================  NVICIP109  ======================================================= */
/* =======================================================  NVICIP110  ======================================================= */
/* =======================================================  NVICIP111  ======================================================= */
/* =======================================================  NVICIP112  ======================================================= */
/* =======================================================  NVICIP113  ======================================================= */
/* =======================================================  NVICIP114  ======================================================= */
/* =======================================================  NVICIP115  ======================================================= */
/* =======================================================  NVICIP116  ======================================================= */
/* =======================================================  NVICIP117  ======================================================= */
/* =======================================================  NVICIP118  ======================================================= */
/* =======================================================  NVICIP119  ======================================================= */
/* =======================================================  NVICIP120  ======================================================= */
/* =======================================================  NVICIP121  ======================================================= */
/* =======================================================  NVICIP122  ======================================================= */
/* =======================================================  NVICIP123  ======================================================= */
/* =======================================================  NVICIP124  ======================================================= */
/* =======================================================  NVICIP125  ======================================================= */
/* =======================================================  NVICIP126  ======================================================= */
/* =======================================================  NVICIP127  ======================================================= */
/* =======================================================  NVICIP128  ======================================================= */
/* =======================================================  NVICIP129  ======================================================= */
/* =======================================================  NVICIP130  ======================================================= */
/* =======================================================  NVICIP131  ======================================================= */
/* =======================================================  NVICIP132  ======================================================= */
/* =======================================================  NVICIP133  ======================================================= */
/* =======================================================  NVICIP134  ======================================================= */
/* =======================================================  NVICIP135  ======================================================= */
/* =======================================================  NVICIP136  ======================================================= */
/* =======================================================  NVICIP137  ======================================================= */
/* =======================================================  NVICIP138  ======================================================= */
/* =======================================================  NVICIP139  ======================================================= */
/* =======================================================  NVICIP140  ======================================================= */
/* =======================================================  NVICIP141  ======================================================= */
/* =======================================================  NVICIP142  ======================================================= */
/* =======================================================  NVICIP143  ======================================================= */
/* =======================================================  NVICIP144  ======================================================= */
/* =======================================================  NVICIP145  ======================================================= */
/* =======================================================  NVICIP146  ======================================================= */
/* =======================================================  NVICIP147  ======================================================= */
/* =======================================================  NVICIP148  ======================================================= */
/* =======================================================  NVICIP149  ======================================================= */
/* =======================================================  NVICIP150  ======================================================= */
/* =======================================================  NVICIP151  ======================================================= */
/* =======================================================  NVICIP152  ======================================================= */
/* =======================================================  NVICIP153  ======================================================= */
/* =======================================================  NVICIP154  ======================================================= */
/* =======================================================  NVICIP155  ======================================================= */
/* =======================================================  NVICIP156  ======================================================= */
/* =======================================================  NVICIP157  ======================================================= */
/* =======================================================  NVICIP158  ======================================================= */
/* =======================================================  NVICIP159  ======================================================= */
/* =======================================================  NVICIP160  ======================================================= */
/* =======================================================  NVICIP161  ======================================================= */
/* =======================================================  NVICIP162  ======================================================= */
/* =======================================================  NVICIP163  ======================================================= */
/* =======================================================  NVICIP164  ======================================================= */
/* =======================================================  NVICIP165  ======================================================= */
/* =======================================================  NVICIP166  ======================================================= */
/* =======================================================  NVICIP167  ======================================================= */
/* =======================================================  NVICIP168  ======================================================= */
/* =======================================================  NVICIP169  ======================================================= */
/* =======================================================  NVICIP170  ======================================================= */
/* =======================================================  NVICIP171  ======================================================= */
/* =======================================================  NVICIP172  ======================================================= */
/* =======================================================  NVICIP173  ======================================================= */
/* =======================================================  NVICIP174  ======================================================= */
/* =======================================================  NVICIP175  ======================================================= */
/* =======================================================  NVICIP176  ======================================================= */
/* =======================================================  NVICIP177  ======================================================= */
/* =======================================================  NVICIP178  ======================================================= */
/* =======================================================  NVICIP179  ======================================================= */
/* =======================================================  NVICIP180  ======================================================= */
/* =======================================================  NVICIP181  ======================================================= */
/* =======================================================  NVICIP182  ======================================================= */
/* =======================================================  NVICIP183  ======================================================= */
/* =======================================================  NVICIP184  ======================================================= */
/* =======================================================  NVICIP185  ======================================================= */
/* =======================================================  NVICIP186  ======================================================= */
/* =======================================================  NVICIP187  ======================================================= */
/* =======================================================  NVICIP188  ======================================================= */
/* =======================================================  NVICIP189  ======================================================= */
/* =======================================================  NVICIP190  ======================================================= */
/* =======================================================  NVICIP191  ======================================================= */
/* =======================================================  NVICIP192  ======================================================= */
/* =======================================================  NVICIP193  ======================================================= */
/* =======================================================  NVICIP194  ======================================================= */
/* =======================================================  NVICIP195  ======================================================= */
/* =======================================================  NVICIP196  ======================================================= */
/* =======================================================  NVICIP197  ======================================================= */
/* =======================================================  NVICIP198  ======================================================= */
/* =======================================================  NVICIP199  ======================================================= */
/* =======================================================  NVICIP200  ======================================================= */
/* =======================================================  NVICIP201  ======================================================= */
/* =======================================================  NVICIP202  ======================================================= */
/* =======================================================  NVICIP203  ======================================================= */
/* =======================================================  NVICIP204  ======================================================= */
/* =======================================================  NVICIP205  ======================================================= */
/* =======================================================  NVICIP206  ======================================================= */
/* =======================================================  NVICIP207  ======================================================= */
/* =======================================================  NVICIP208  ======================================================= */
/* =======================================================  NVICIP209  ======================================================= */
/* =======================================================  NVICIP210  ======================================================= */
/* =======================================================  NVICIP211  ======================================================= */
/* =======================================================  NVICIP212  ======================================================= */
/* =======================================================  NVICIP213  ======================================================= */
/* =======================================================  NVICIP214  ======================================================= */
/* =======================================================  NVICIP215  ======================================================= */
/* =======================================================  NVICIP216  ======================================================= */
/* =======================================================  NVICIP217  ======================================================= */
/* =======================================================  NVICIP218  ======================================================= */
/* =======================================================  NVICIP219  ======================================================= */
/* =======================================================  NVICIP220  ======================================================= */
/* =======================================================  NVICIP221  ======================================================= */
/* =======================================================  NVICIP222  ======================================================= */
/* =======================================================  NVICIP223  ======================================================= */
/* =======================================================  NVICIP224  ======================================================= */
/* =======================================================  NVICIP225  ======================================================= */
/* =======================================================  NVICIP226  ======================================================= */
/* =======================================================  NVICIP227  ======================================================= */
/* =======================================================  NVICIP228  ======================================================= */
/* =======================================================  NVICIP229  ======================================================= */
/* =======================================================  NVICIP230  ======================================================= */
/* =======================================================  NVICIP231  ======================================================= */
/* =======================================================  NVICIP232  ======================================================= */
/* =======================================================  NVICIP233  ======================================================= */
/* =======================================================  NVICIP234  ======================================================= */
/* =======================================================  NVICIP235  ======================================================= */
/* =======================================================  NVICIP236  ======================================================= */
/* =======================================================  NVICIP237  ======================================================= */
/* =======================================================  NVICIP238  ======================================================= */
/* =======================================================  NVICIP239  ======================================================= */
/* =======================================================  NVICSTIR  ======================================================== */


/* =========================================================================================================================== */
/* ================                                            MC                                             ================ */
/* =========================================================================================================================== */

/* ========================================================  SINCSTS  ======================================================== */
/* ===============================================  MC SINCSTS SINCFLG [0..7]  =============================================== */
                                  /* MC_SINCSTS_SINCFLG                                                 */
#define MC_SINCSTS_SINCFLG_0                    0U      /* 0 : A bus slave connection to AXBS input port n is absent          */
#define MC_SINCSTS_SINCFLG_1                    1U      /* 1 : A bus slave connection to AXBS input port n is present         */


/* ========================================================  MINCSTS  ======================================================== */
/* ===============================================  MC MINCSTS MINCFLG [0..7]  =============================================== */
                                  /* MC_MINCSTS_MINCFLG                                                 */
#define MC_MINCSTS_MINCFLG_0                    0U      /* 0 : A bus master connection to AXBS input port n is absent         */
#define MC_MINCSTS_MINCFLG_1                    1U      /* 1 : A bus master connection to AXBS input port n is present        */


/* ========================================================  CPCTRL  ========================================================= */
/* ================================================  MC CPCTRL HMSTS [0..1]  ================================================= */
                                 /* MC_CPCTRL_HMSTS                                                    */
#define MC_CPCTRL_HMSTS_00                     0U      /* 00 : Waiting for request                                           */
#define MC_CPCTRL_HMSTS_01                     1U      /* 01 : Waiting for platform idle                                     */
#define MC_CPCTRL_HMSTS_11                     3U      /* 11 : Platform stalled                                              */
#define MC_CPCTRL_HMSTS_10                     2U      /* 10 : Unused state                                                  */


/* ==============================================  MC CPCTRL RXHREQFLG [2..2]  =============================================== */
                                  /* MC_CPCTRL_RXHREQFLG                                                */
#define MC_CPCTRL_RXHREQFLG_0                  0U      /* 0 : AXBS is not receiving halt request                             */
#define MC_CPCTRL_RXHREQFLG_1                  1U      /* 1 : AXBS is receiving halt request                                 */

/* =================================================  MC CPCTRL HSTS [3..3]  ================================================= */
                                  /* MC_CPCTRL_HSTS                                                     */
#define MC_CPCTRL_HSTS_0                       0U      /* 0 : AXBS is not currently halted                                   */
#define MC_CPCTRL_HSTS_1                       1U      /* 1 : AXBS is currently halted                                       */


/* ==============================================  MC CPCTRL FMCPGISTS [4..4]  =============================================== */
                                  /* MC_CPCTRL_FMCPGISTS                                                */
#define MC_CPCTRL_FMCPGISTS_0                  0U      /* 0 : FMC program flash is not idle                                  */
#define MC_CPCTRL_FMCPGISTS_1                  1U      /* 1 : FMC program flash is currently idle                            */


/* ===============================================  MC CPCTRL ACISTS [6..6]  =============================================== */
                                  /* MC_CPCTRL_ACISTS                                                 */
#define MC_CPCTRL_ACISTS_0                   0U      /* 0 : PBRIDGE is not idle                                            */
#define MC_CPCTRL_ACISTS_1                   1U      /* 1 : PBRIDGE is currently idle                                      */


/* ================================================  MC CPCTRL CASEL [9..9]  ================================================= */
                                  /* MC_CPCTRL_CASEL                                                    */
#define MC_CPCTRL_CASEL_0                      0U      /* 0 : Fixed-priority arbitration                                     */
#define MC_CPCTRL_CASEL_1                      1U      /* 1 : Round-robin arbitration                                        */


/* ==============================================  MC CPCTRL SHAPCFG [24..25]  =============================================== */
                                 /* MC_CPCTRL_SHAPCFG                                                  */
#define MC_CPCTRL_SHAPCFG_00                   0U      /* 00 : Round robin                                                   */
#define MC_CPCTRL_SHAPCFG_01                   1U      /* 01 : Special round robin (favors SRAM backdoor accesses over
                                                     the processor)                                                     */
#define MC_CPCTRL_SHAPCFG_10                   2U      /* 10 : Fixed priority. Processor has highest  backdoor has lowest    */
#define MC_CPCTRL_SHAPCFG_11                   3U      /* 11 : Fixed priority. Backdoor has highest  processor has lowest    */


/* ==============================================  MC CPCTRL SLAPCFG [28..29]  =============================================== */
                                  /* MC_CPCTRL_SLAPCFG                                                  */
#define MC_CPCTRL_SLAPCFG_00                   0U      /* 00 : Round robin                                                   */
#define MC_CPCTRL_SLAPCFG_01                   1U      /* 01 : Special round robin (favors SRAM backdoor accesses over
                                                     the processor)                                                     */
#define MC_CPCTRL_SLAPCFG_10                   2U      /* 10 : Fixed priority. Processor has highest  backdoor has lowest    */
#define MC_CPCTRL_SLAPCFG_11                   3U      /* 11 : Fixed priority. Backdoor has highest  processor has lowest    */


/* ======================================================  FPU_INTCSTS  ====================================================== */
/* ===========================================  MC FPU_INTCSTS INVALIDIFLG [8..8]  =========================================== */
                                  /* MC_FPU_INTCSTS_INVALIDIFLG                                         */
#define MC_FPU_INTCSTS_INVALIDIFLG_0           0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_INVALIDIFLG_1           1U      /* 1 : Interrupt occurred                                             */


/* ============================================  MC FPU_INTCSTS ZEROIFLG [9..9]  ============================================= */
                                 /* MC_FPU_INTCSTS_ZEROIFLG                                            */
#define MC_FPU_INTCSTS_ZEROIFLG_0              0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_ZEROIFLG_1              1U      /* 1 : Interrupt occurred                                             */


/* ============================================  MC FPU_INTCSTS OVRIFLG [10..10]  ============================================ */
                                  /* MC_FPU_INTCSTS_OVRIFLG                                             */
#define MC_FPU_INTCSTS_OVRIFLG_0                0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_OVRIFLG_1                1U      /* 1 : Interrupt occurred                                             */


/* ============================================  MC FPU_INTCSTS UDRIFLG [11..11]  ============================================ */
                                 /* MC_FPU_INTCSTS_UDRIFLG                                             */
#define MC_FPU_INTCSTS_UDRIFLG_0                0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_UDRIFLG_1                1U      /* 1 : Interrupt occurred                                             */


/* ==========================================  MC FPU_INTCSTS INEXACTIFLG [12..12]  ========================================== */
                                  /* MC_FPU_INTCSTS_INEXACTIFLG                                         */
#define MC_FPU_INTCSTS_INEXACTIFLG_0            0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_INEXACTIFLG_1            1U      /* 1 : Interrupt occurred                                             */


/* ============================================  MC FPU_INTCSTS INDIFLG [15..15]  ============================================ */
                                 /* MC_FPU_INTCSTS_INDIFLG                                             */
#define MC_FPU_INTCSTS_INDIFLG_0                0U      /* 0 : No interrupt                                                   */
#define MC_FPU_INTCSTS_INDIFLG_1                1U      /* 1 : Interrupt occurred                                             */


/* ===========================================  MC FPU_INTCSTS INVALIDEN [24..24]  =========================================== */
                                  /* MC_FPU_INTCSTS_INVALIDEN                                           */
#define MC_FPU_INTCSTS_INVALIDEN_0              0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_INVALIDEN_1              1U      /* 1 : Enable interrupt                                               */


/* ============================================  MC FPU_INTCSTS ZEROEN [25..25]  ============================================= */
                                  /* MC_FPU_INTCSTS_ZEROEN                                              */
#define MC_FPU_INTCSTS_ZEROEN_0                 0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_ZEROEN_1                 1U      /* 1 : Enable interrupt                                               */


/* ============================================  MC FPU_INTCSTS OVRIEN [26..26]  ============================================= */
                                  /* MC_FPU_INTCSTS_OVRIEN                                              */
#define MC_FPU_INTCSTS_OVRIEN_0                 0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_OVRIEN_1                 1U      /* 1 : Enable interrupt                                               */


/* ============================================  MC FPU_INTCSTS UDRIEN [27..27]  ============================================= */
                                /* MC_FPU_INTCSTS_UDRIEN                                              */
#define MC_FPU_INTCSTS_UDRIEN_0                 0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_UDRIEN_1                 1U      /* 1 : Enable interrupt                                               */


/* ==========================================  MC FPU_INTCSTS INEXACTIEN [28..28]  =========================================== */
                                   /* MC_FPU_INTCSTS_INEXACTIEN                                          */
#define MC_FPU_INTCSTS_INEXACTIEN_0             0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_INEXACTIEN_1             1U      /* 1 : Enable interrupt                                               */


/* ============================================  MC FPU_INTCSTS INDIEN [31..31]  ============================================= */
                                  /* MC_FPU_INTCSTS_INDIEN                                              */
#define MC_FPU_INTCSTS_INDIEN_0                0U      /* 0 : Disable interrupt                                              */
#define MC_FPU_INTCSTS_INDIEN_1                1U      /* 1 : Enable interrupt                                               */


/* ==========================================================  PID  ========================================================== */
/* ========================================================  COCTRL  ========================================================= */
/* ================================================  MC COCTRL COREQ [0..0]  ================================================= */
                                  /* MC_COCTRL_COREQ                                                    */
#define MC_COCTRL_COREQ_0                      0U      /* 0 : Request is cleared.                                            */
#define MC_COCTRL_COREQ_1                      1U      /* 1 : Request Compute Operation.                                     */


/* ================================================  MC COCTRL COACK [1..1]  ================================================= */
                                   /* MC_COCTRL_COACK                                                    */
#define MC_COCTRL_COACK_0                      0U      /* 0 : Compute operation entry has not completed or compute operation
                                                     exit has completed.                                                */
#define MC_COCTRL_COACK_1                      1U      /* 1 : Compute operation entry has completed or compute operation
                                                     exit has not completed.                                            */


/* ================================================  MC COCTRL COWBI [2..2]  ================================================= */
                                  /* MC_COCTRL_COWBI                                                    */
#define MC_COCTRL_COWBI_0                      0U      /* 0 : No effect.                                                     */
#define MC_COCTRL_COWBI_1                      1U      /* 1 : When set  the CPOREQ is cleared on any interrupt or exception
                                                     vector fetch.                                                      */


/* ========================================================  LMDES0  ========================================================= */
/* ================================================  MC LMDES0 TSEL [13..15]  ================================================ */
                                  /* MC_LMDES0_TSEL                                                     */
#define MC_LMDES0_TSEL_000                     0U      /* 000 : SRAM_L                                                       */
#define MC_LMDES0_TSEL_001                     1U      /* 001 : SRAM_U                                                       */


/* ================================================  MC LMDES0 LOCK [16..16]  ================================================ */
                                  /* MC_LMDES0_LOCK                                                     */
#define MC_LMDES0_LOCK_0                       0U      /* 0 : Writes to the LMDRn[7:0] are allowed.                          */
#define MC_LMDES0_LOCK_1                       1U      /* 1 : Writes to the LMDRn[7:0] are ignored.                          */


/* ===============================================  MC LMDES0 DPWSEL [17..19]  =============================================== */
                                  /* MC_LMDES0_DPWSEL                                                   */
#define MC_LMDES0_DPWSEL_010                   2U      /* 010 : LMEMn 32-bits wide                                           */
#define MC_LMDES0_DPWSEL_011                   3U      /* 011 : LMEMn 64-bits wide                                           */


/* ===============================================  MC LMDES0 CWCFG [20..23]  ================================================ */
                                  /* MC_LMDES0_CWCFG                                                    */
#define MC_LMDES0_CWCFG_0000                   0U      /* 0000 : No Cache                                                    */
#define MC_LMDES0_CWCFG_0010                   2U      /* 0010 : 2-Way Set Associative                                       */
#define MC_LMDES0_CWCFG_0100                   4U      /* 0100 : 4-Way Set Associative                                       */


/* ================================================  MC LMDES0 SIZE [24..27]  ================================================ */
                                  /* MC_LMDES0_SIZE                                                     */
#define MC_LMDES0_SIZE_0000                     0U      /* 0000 : no LMEMn (0 KB)                                             */
#define MC_LMDES0_SIZE_0001                     1U      /* 0001 : 1 KB LMEMn                                                  */
#define MC_LMDES0_SIZE_0010                     2U      /* 0010 : 2 KB LMEMn                                                  */
#define MC_LMDES0_SIZE_0011                     3U      /* 0011 : 4 KB LMEMn                                                  */
#define MC_LMDES0_SIZE_0100                     4U      /* 0100 : 8 KB LMEMn                                                  */
#define MC_LMDES0_SIZE_0101                     5U      /* 0101 : 16 KB LMEMn                                                 */
#define MC_LMDES0_SIZE_0110                     6U      /* 0110 : 32 KB LMEMn                                                 */
#define MC_LMDES0_SIZE_0111                     7U      /* 0111 : 64 KB LMEMn                                                 */
#define MC_LMDES0_SIZE_1000                     8U      /* 1000 : 128 KB LMEMn                                                */
#define MC_LMDES0_SIZE_1001                     9U      /* 1001 : 256 KB LMEMn                                                */
#define MC_LMDES0_SIZE_1010                     10U     /* 1010 : 512 KB LMEMn                                                */
#define MC_LMDES0_SIZE_1011                     11U     /* 1011 : 1024 KB LMEMn                                               */
#define MC_LMDES0_SIZE_1100                     12U     /* 1100 : 2048 KB LMEMn                                               */
#define MC_LMDES0_SIZE_1101                     13U     /* 1101 : 4096 KB LMEMn                                               */
#define MC_LMDES0_SIZE_1110                     14U     /* 1110 : 8192 KB LMEMn                                               */
#define MC_LMDES0_SIZE_1111                     15U     /* 1111 : 16384 KB LMEMn                                              */


/* ===============================================  MC LMDES0 SIZEH [28..28]  ================================================ */
                                  /* MC_LMDES0_SIZEH                                                    */
#define MC_LMDES0_SIZEH_0                      0U      /* 0 : LMEMn is a power-of-2 capacity.                                */
#define MC_LMDES0_SIZEH_1                      1U      /* 1 : LMEMn is not a power-of-2  with a capacity is 0.75 * LMSZ.     */


/* ===============================================  MC LMDES0 VALID [31..31]  ================================================ */
                                   /* MC_LMDES0_VALID                                                    */
#define MC_LMDES0_VALID_0                      0U      /* 0 : LMEMn is not present.                                          */
#define MC_LMDES0_VALID_1                      1U      /* 1 : LMEMn is present.                                              */


/* ========================================================  LMDES1  ========================================================= */
/* ================================================  MC LMDES1 TSEL [13..15]  ================================================ */
                                  /* MC_LMDES1_TSEL                                                     */
#define MC_LMDES1_TSEL_000                     0U      /* 000 : SRAM_L                                                       */
#define MC_LMDES1_TSEL_001                     1U      /* 001 : SRAM_U                                                       */


/* ================================================  MC LMDES1 LOCK [16..16]  ================================================ */
                                  /* MC_LMDES1_LOCK                                                     */
#define MC_LMDES1_LOCK_0                       0U      /* 0 : Writes to the LMDRn[7:0] are allowed.                          */
#define MC_LMDES1_LOCK_1                       1U      /* 1 : Writes to the LMDRn[7:0] are ignored.                          */


/* ===============================================  MC LMDES1 DPWSEL [17..19]  =============================================== */
                                 /* MC_LMDES1_DPWSEL                                                   */
#define MC_LMDES1_DPWSEL_010                  2U      /* 010 : LMEMn 32-bits wide                                           */
#define MC_LMDES1_DPWSEL_011                  3U      /* 011 : LMEMn 64-bits wide                                           */


/* ===============================================  MC LMDES1 CWCFG [20..23]  ================================================ */
                                   /* MC_LMDES1_CWCFG                                                    */
#define MC_LMDES1_CWCFG_0000                   0U      /* 0000 : No Cache                                                    */
#define MC_LMDES1_CWCFG_0010                   2U      /* 0010 : 2-Way Set Associative                                       */
#define MC_LMDES1_CWCFG_0100                   4U      /* 0100 : 4-Way Set Associative                                       */


/* ================================================  MC LMDES1 SIZE [24..27]  ================================================ */
                                   /* MC_LMDES1_SIZE                                                     */
#define MC_LMDES1_SIZE_0000                     0U      /* 0000 : no LMEMn (0 KB)                                             */
#define MC_LMDES1_SIZE_0001                     1U      /* 0001 : 1 KB LMEMn                                                  */
#define MC_LMDES1_SIZE_0010                     2U      /* 0010 : 2 KB LMEMn                                                  */
#define MC_LMDES1_SIZE_0011                     3U      /* 0011 : 4 KB LMEMn                                                  */
#define MC_LMDES1_SIZE_0100                     4U      /* 0100 : 8 KB LMEMn                                                  */
#define MC_LMDES1_SIZE_0101                     5U      /* 0101 : 16 KB LMEMn                                                 */
#define MC_LMDES1_SIZE_0110                     6U      /* 0110 : 32 KB LMEMn                                                 */
#define MC_LMDES1_SIZE_0111                     7U      /* 0111 : 64 KB LMEMn                                                 */
#define MC_LMDES1_SIZE_1000                     8U      /* 1000 : 128 KB LMEMn                                                */
#define MC_LMDES1_SIZE_1001                     9U      /* 1001 : 256 KB LMEMn                                                */
#define MC_LMDES1_SIZE_1010                     10U     /* 1010 : 512 KB LMEMn                                                */
#define MC_LMDES1_SIZE_1011                     11U     /* 1011 : 1024 KB LMEMn                                               */
#define MC_LMDES1_SIZE_1100                     12U     /* 1100 : 2048 KB LMEMn                                               */
#define MC_LMDES1_SIZE_1101                     13U     /* 1101 : 4096 KB LMEMn                                               */
#define MC_LMDES1_SIZE_1110                     14U     /* 1110 : 8192 KB LMEMn                                               */
#define MC_LMDES1_SIZE_1111                     15U     /* 1111 : 16384 KB LMEMn                                              */


/* ===============================================  MC LMDES1 SIZEH [28..28]  ================================================ */
                                   /* MC_LMDES1_SIZEH                                                    */
#define MC_LMDES1_SIZEH_0                      0U      /* 0 : LMEMn is a power-of-2 capacity.                                */
#define MC_LMDES1_SIZEH_1                      1U      /* 1 : LMEMn is not a power-of-2  with a capacity is 0.75 * LMSZ.     */


/* ===============================================  MC LMDES1 VALID [31..31]  ================================================ */
                                  /* MC_LMDES1_VALID                                                    */
#define MC_LMDES1_VALID_0                      0U      /* 0 : LMEMn is not present.                                          */
#define MC_LMDES1_VALID_1                      1U      /* 1 : LMEMn is present.                                              */


/* ========================================================  LMDES2  ========================================================= */
/* ================================================  MC LMDES2 TSEL [13..15]  ================================================ */
                                  /* MC_LMDES2_TSEL                                                     */
#define MC_LMDES2_TSEL_010                     2U      /* 010 : PC Cache                                                     */


/* ================================================  MC LMDES2 LOCK [16..16]  ================================================ */
                                  /* MC_LMDES2_LOCK                                                     */
#define MC_LMDES2_LOCK_0                       0U      /* 0 : Writes to the LMDRn[7:0] are allowed.                          */
#define MC_LMDES2_LOCK_1                       1U      /* 1 : Writes to the LMDRn[7:0] are ignored.                          */


/* ===============================================  MC LMDES2 DPWSEL [17..19]  =============================================== */
                                   /* MC_LMDES2_DPWSEL                                                   */
#define MC_LMDES2_DPWSEL_010                   2U      /* 010 : LMEMn 32-bits wide                                           */
#define MC_LMDES2_DPWSEL_011                   3U      /* 011 : LMEMn 64-bits wide                                           */


/* ===============================================  MC LMDES2 CWCFG [20..23]  ================================================ */
                                   /* MC_LMDES2_CWCFG                                                    */
#define MC_LMDES2_CWCFG_0000                   0U      /* 0000 : No Cache                                                    */
#define MC_LMDES2_CWCFG_0010                   2U      /* 0010 : 2-Way Set Associative                                       */
#define MC_LMDES2_CWCFG_0100                   4U      /* 0100 : 4-Way Set Associative                                       */


/* ================================================  MC LMDES2 SIZE [24..27]  ================================================ */
                                   /* MC_LMDES2_SIZE                                                     */
#define MC_LMDES2_SIZE_0100                    4U      /* 0100 : 4 KB LMEMn                                                  */


/* ===============================================  MC LMDES2 SIZEH [28..28]  ================================================ */
                                  /* MC_LMDES2_SIZEH                                                    */
#define MC_LMDES2_SIZEH_0                      0U      /* 0 : LMEMn is a power-of-2 capacity.                                */
#define MC_LMDES2_SIZEH_1                      1U      /* 1 : LMEMn is not a power-of-2  with a capacity is 0.75 * LMSZ.     */


/* ===============================================  MC LMDES2 VALID [31..31]  ================================================ */
                                   /* MC_LMDES2_VALID                                                    */
#define MC_LMDES2_VALID_0                      0U      /* 0 : LMEMn is not present.                                          */
#define MC_LMDES2_VALID_1                      1U      /* 1 : LMEMn is present.                                              */


/* =======================================================  LMPECTRL  ======================================================== */
/* ===============================================  MC LMPECTRL NCREN [0..0]  ================================================ */
                                   /* MC_LMPECTRL_NCREN                                                  */
#define MC_LMPECTRL_NCREN_0                  = 0U      /* 0 : Reporting disabled                                             */
#define MC_LMPECTRL_NCREN_1                  = 1U      /* 1 : Reporting enabled                                              */


/* ===============================================  MC LMPECTRL R1BREN [8..8]  =============================================== */
                                   /* MC_LMPECTRL_R1BREN                                                 */
#define MC_LMPECTRL_R1BREN_0                 = 0U      /* 0 : Reporting disabled                                             */
#define MC_LMPECTRL_R1BREN_1                 = 1U      /* 1 : Reporting enabled                                              */


/* ==============================================  MC LMPECTRL CPREN [20..20]  =============================================== */
                                  /* MC_LMPECTRL_CPREN                                                  */
#define MC_LMPECTRL_CPREN_0                    0U      /* 0 : Reporting disabled                                             */
#define MC_LMPECTRL_CPREN_1                    1U      /* 1 : Reporting enabled                                              */


/* ========================================================  LMPEINT  ======================================================== */
/* ==============================================  MC LMPEINT PEERRL [24..28]  =============================================== */
                                   /* MC_LMPEINT_PEERRL                                                  */
#define MC_LMPEINT_PEERRL_00                   0U      /* 00 : Non-correctable ECC event from SRAM_L                         */
#define MC_LMPEINT_PEERRL_01                   1U      /* 01 : Non-correctable ECC event from SRAM_U                         */


/* ========================================================  LMFADDR  ======================================================== */
/* =========================================================  LMFAT  ========================================================= */
/* ===============================================  MC LMFAT PEFMSIZE [4..6]  ================================================ */
                                /* MC_LMFAT_PEFMSIZE                                                  */
#define MC_LMFAT_PEFMSIZE_000                   0U      /* 000 : 8-bit access                                                 */
#define MC_LMFAT_PEFMSIZE_001                   1U      /* 001 : 16-bit access                                                */
#define MC_LMFAT_PEFMSIZE_010                   2U      /* 010 : 32-bit access                                                */
#define MC_LMFAT_PEFMSIZE_011                   3U      /* 011 : 64-bit access                                                */


/* =======================================================  LMFDATAH  ======================================================== */
/* =======================================================  LMFDATAL  ======================================================== */


/* =========================================================================================================================== */
/* ================                                            LMC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CCTRL  ========================================================= */
/* =================================================  LMC CCTRL CEN [0..0]  ================================================= */
                                 /* LMC_CCTRL_CEN                                                     */
#define LMC_CCTRL_CEN_0                        0U      /* 0 : Cache disabled                                                 */
#define LMC_CCTRL_CEN_1                        1U      /* 1 : Cache enabled                                                  */


/* ================================================  LMC CCTRL IW0 [24..24]  ================================================ */
                                  /* LMC_CCTRL_IW0                                                     */
#define LMC_CCTRL_IW0_0                        0U      /* 0 : No operation                                                   */
#define LMC_CCTRL_IW0_1                        1U      /* 1 : When setting the GO bit  invalidate all lines in way 0.        */


/* ================================================  LMC CCTRL PW0 [25..25]  ================================================ */
                                 /* LMC_CCTRL_PW0                                                     */
#define LMC_CCTRL_PW0_0                        0U      /* 0 : No operation                                                   */
#define LMC_CCTRL_PW0_1                        1U      /* 1 : When setting the GO bit  push all modified lines in way
                                                     0                                                                  */


/* ================================================  LMC CCTRL IW1 [26..26]  ================================================ */
                                  /* LMC_CCTRL_IW1                                                     */
#define LMC_CCTRL_IW1_0                        0U      /* 0 : No operation                                                   */
#define LMC_CCTRL_IW1_1                        1U      /* 1 : When setting the GO bit  invalidate all lines in way 1         */


/* ================================================  LMC CCTRL PW1 [27..27]  ================================================ */
                                  /* LMC_CCTRL_PW1                                                     */
#define LMC_CCTRL_PW1_0                        0U      /* 0 : No operation                                                   */
#define LMC_CCTRL_PW1_1                        1U      /* 1 : When setting the GO bit  push all modified lines in way
                                                     1                                                                  */


/* ===============================================  LMC CCTRL ICCMD [31..31]  =============================================== */
                                  /* LMC_CCTRL_ICCMD                                                   */
#define LMC_CCTRL_ICCMD_0                      0U      /* 0 : Write: no effect. Read: no cache command active.               */
#define LMC_CCTRL_ICCMD_1                      1U      /* 1 : Write: initiate command indicated by bits 27-24. Read: cache
                                                     command active.                                                    */


/* ========================================================  CLCTRL  ======================================================== */
/* ===============================================  LMC CLCTRL ICLCMD [0..0]  =============================================== */
                                  /* LMC_CLCTRL_ICLCMD                                                 */
#define LMC_CLCTRL_ICLCMD_0                    0U      /* 0 : Write: no effect. Read: no line command active.                */
#define LMC_CLCTRL_ICLCMD_1                    1U      /* 1 : Write: initiate line command indicated by bits 27-24. Read:
                                                     line command active.                                               */


/* =============================================  LMC CLCTRL LCMDWSEL [14..14]  ============================================= */
                                  /* LMC_CLCTRL_LCMDWSEL                                               */
#define LMC_CLCTRL_LCMDWSEL_0                  0U      /* 0 : Way 0                                                          */
#define LMC_CLCTRL_LCMDWSEL_1                  1U      /* 1 : Way 1                                                          */


/* ===========================================  LMC CLCTRL TAG_DATASEL [16..16]  ============================================ */
                                  /* LMC_CLCTRL_TAG_DATASEL                                            */
#define LMC_CLCTRL_TAG_DATASEL_0               0U      /* 0 : Data                                                           */
#define LMC_CLCTRL_TAG_DATASEL_1               1U      /* 1 : Tag                                                            */


/* =============================================  LMC CLCTRL LCMDCFG [24..25]  ============================================== */
                                  /* LMC_CLCTRL_LCMDCFG                                                */
#define LMC_CLCTRL_LCMDCFG_00                  0U      /* 00 : Search and read or write                                      */
#define LMC_CLCTRL_LCMDCFG_01                  1U      /* 01 : Invalidate                                                    */
#define LMC_CLCTRL_LCMDCFG_10                  2U      /* 10 : Push                                                          */
#define LMC_CLCTRL_LCMDCFG_11                  3U      /* 11 : Clear                                                         */


/* =============================================  LMC CLCTRL LADDRSEL [26..26]  ============================================= */
                                  /* LMC_CLCTRL_LADDRSEL                                               */
#define LMC_CLCTRL_LADDRSEL_0                 0U      /* 0 : Cache address                                                  */
#define LMC_CLCTRL_LADDRSEL_1                 1U      /* 1 : Physical address                                               */


/* =============================================  LMC CLCTRL LACCTSEL [27..27]  ============================================= */
                                 /* LMC_CLCTRL_LACCTSEL                                               */
#define LMC_CLCTRL_LACCTSEL_0                  0U      /* 0 : Read                                                           */
#define LMC_CLCTRL_LACCTSEL_1                  1U      /* 1 : Write                                                          */


/* ========================================================  CSADDR  ======================================================== */
/* ===============================================  LMC CSADDR CLCMDI [0..0]  =============================================== */
                                  /* LMC_CSADDR_CLCMDI                                                 */
#define LMC_CSADDR_CLCMDI_0                    0U      /* 0 : Write: no effect. Read: no line command active.                */
#define LMC_CSADDR_CLCMDI_1                    1U      /* 1 : Write: initiate line command indicated by bits CLCR[27:24].
                                                     Read: line command active.                                         */


/* =========================================================  CDATA  ========================================================= */
/* ========================================================  RCMCFG  ========================================================= */
/* ===============================================  LMC RCMCFG CMCFGR [0..1]  ================================================ */
                                  /* LMC_RCMCFG_CMCFGR                                                  */
#define LMC_RCMCFG_CMCFGR_00                    0U      /* 00 : Non-cacheable                                                 */
#define LMC_RCMCFG_CMCFGR_01                    1U      /* 01 : Non-cacheable                                                 */
#define LMC_RCMCFG_CMCFGR_10                    2U      /* 10 : Write-through                                                 */
#define LMC_RCMCFG_CMCFGR_11                    3U      /* 11 : Write-back                                                    */



/** @} */ /* End of group Macros_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* APM32F445_446_H */


/** @} */ /* End of group APM32F445_446 */

/** @} */ /* End of group  */
