/*!
 * @file        bmp561_tmr.h
 *
 * @brief       This file contains all the functions prototypes for the TMR firmware library
 *
 * @version     V1.0.0
 *
 * @date        2025-01-01
 *
 * @attention
 *
 *  Copyright (C) 2025 Geehy Semiconductor
 *
 *  You may not use this file except in compliance with the
 *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 *
 *  The program is only for reference, which is distributed in the hope
 *  that it will be useful and instructional for customers to develop
 *  their software. Unless required by applicable law or agreed to in
 *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
 *  and limitations under the License.
 */

/* Define to prevent recursive inclusion */
#ifndef __BMP561_TMR_H
#define __BMP561_TMR_H

/* Includes */
#include "bmp561.h"

#ifdef __cplusplus
  extern "C" {
#endif

/** @addtogroup Peripherals_Library Standard Peripheral Library
  @{
*/

/** @addtogroup TMR_Driver TMR Driver
  @{
*/

/** @addtogroup TMR_Enumerations Enumerations
  @{
*/

/**
 * @brief TMR mode
 */
typedef enum
{
    TMR_MODE_TMR = 0,    /*!< TIMER mode */
    TMR_MODE_PWM = 1     /*!< PWM mode */
} TMR_MODE_T;

/**
 * @brief TMR PWM polarity
 */
typedef enum
{
    TMR_PWM_POL_HIGH = 0,    /*!< Output high level */
    TMR_PWM_POL_LOW  = 1     /*!< Output low level */
} TMR_PWM_POL_T;

/**
 * @brief TMR clock divisor
 */
typedef enum
{
    TMR_DIV_1     = ((uint8_t)0x00),    /*!< TMR clock = Fsys/2^0 */
    TMR_DIV_2     = ((uint8_t)0x01),    /*!< TMR clock = Fsys/2^1 */
    TMR_DIV_4     = ((uint8_t)0x02),    /*!< TMR clock = Fsys/2^2 */
    TMR_DIV_8     = ((uint8_t)0x03),    /*!< TMR clock = Fsys/2^3 */
    TMR_DIV_16    = ((uint8_t)0x04),    /*!< TMR clock = Fsys/2^4 */
    TMR_DIV_32    = ((uint8_t)0x05),    /*!< TMR clock = Fsys/2^5 */
    TMR_DIV_64    = ((uint8_t)0x06),    /*!< TMR clock = Fsys/2^6 */
    TMR_DIV_128   = ((uint8_t)0x07),    /*!< TMR clock = Fsys/2^7 */
    TMR_DIV_256   = ((uint8_t)0x08),    /*!< TMR clock = Fsys/2^8 */
    TMR_DIV_512   = ((uint8_t)0x09),    /*!< TMR clock = Fsys/2^9 */
    TMR_DIV_1024  = ((uint8_t)0x0A),    /*!< TMR clock = Fsys/2^10 */
    TMR_DIV_OTHER = ((uint8_t)0x0A)     /*!< TMR clock = Fsys/2^10 */
} TMR_DIV_T;

/**
 * @brief TMR interrupt
 */
typedef enum
{
    TMR_INT_OV  = ((uint8_t)0x01),    /*!< Overflow interrupt */
    TMR_INT_PWM = ((uint8_t)0x02),    /*!< PWM mode counter arrived register PWMXD's value occurs interrupt */
} TMR_INT_T;

/**@} end of group TMR_Enumerations */

/** @addtogroup  TMR_Functions Functions
  @{
*/

/* TMR configuration */
void TMR_Reset(TMR_T* tmr);
void TMR_Enable(TMR_T* tmr);
void TMR_Disable(TMR_T* tmr);
void TMR_ConfigMode(TMR_T* tmr, TMR_MODE_T mode);
void TMR_EnableOverflowReload(TMR_T* tmr);
void TMR_DisableOverflowReload(TMR_T* tmr);
void TMR_ConfigClockDiv(TMR_T* tmr, TMR_DIV_T div);
void TMR_SetCounter(TMR_T* tmr, uint16_t counter);
uint16_t TMR_GetCounter(TMR_T* tmr);

/* TMR PWM configuration */
void TMR_PWM_ConfigPolarity(TMR_T* tmr, TMR_PWM_POL_T levelType);
void TMR_PWM_ConfigDutyRatio(TMR_T* tmr, uint16_t ratio);

/* TMR interrupt */
void TMR_EnableInterrupt(TMR_T* tmr, TMR_INT_T interrupt);
void TMR_DisableInterrupt(TMR_T* tmr, TMR_INT_T interrupt);
uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
void TMR_ClearIntFlag(TMR_T* tmr, TMR_INT_T flag);

/**@} end of group TMR_Functions*/
/**@} end of group TMR_Driver*/
/**@} end of group Peripherals_Library*/

#ifdef __cplusplus
}
#endif

#endif /* __BMP561_TMR_H */
