//#############################################################################
//
// FILE:    dccomp_ex4_clock_fail_detect.c
//
// TITLE:   DCCOMP Clock Fail Detection
//
// VERSION: 1.0.0
//
// DATE:    2025-01-15
//
//! \addtogroup driver_example_list
//! <h1>DCCOMP Detection of clock failure</h1>
//!
//! This program demonstrates clock failure detection on continuous
//! monitoring of the PLL Clock in the system using XTAL as the osc
//! clock source. Once the oscillator clock fails, it would trigger
//! a DCCOMP error interrupt, causing the decrement/ reload of counters
//! to stop. In this examples, the clock failure is simulated by
//! turning off the XTAL oscillator. Once the ISR is serviced, the
//! osc source is changed to INTOSC1 and the PLL is turned off.
//!
//! The Dual-Clock Comparator Module 0 is used for the clock monitoring.
//! The clocksource0 is the reference clock (Fclk0 = 20Mhz) and the
//! clocksource1 is the clock that needs to be monitored (Fclk1 = 200Mhz).
//! Seed is the value that gets loaded into the Counter.
//!
//! \note In the current example, the XTAL is expected to be a Resonator
//! running in Crystal mode which is later switched off to simulate the clock
//! failure. If an SE Crystal is used, you will need to physically disconnect
//! the clock on the board.
//!
//! Please refer to the TRM for details on counter seed values to be set.
//! Note : When running in flash configuration it is good to do a reset
//! & restart after loading the example to remove any stale flags/states.
//!
//! \b External \b Connections \n
//!  - None
//!
//! \b Watch \b Variables \n
//!  - \b status/result - Status of the clock failure detection
//!
//
//###########################################################################
// $Copyright:
// Copyright (C) 2024 Geehy Semiconductor - http://www.geehy.com/
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
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//
// Modifications:
// - 2024-09-13:
// 1. Modify some comments, macros, function names, and function contents.
//
//###########################################################################

//
// Included Files
//
#include "driverlib.h"
#include "device.h"

//
// Defines
//
#define PASS 0
#define FAIL 1

//
// Globals
//
volatile uint32_t result = FAIL, isr_enter = 0;
uint16_t pass= 0;

//
// Function Prototypes
//
void DCCOMP_ISR();

void example_main(void)
{
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    //Initialize NVIC and clears NVIC registers. Disables CPU interrupts
    //
    Interrupt_initModule();

    //
    //Initialize the NVIC vector table with pointers to the shell Interrupt
    //Service Routines (ISR)
    //
    Interrupt_initVectorTable();

    //
    // Clear Error & Done Flag
    //
    DCCOMP_clearErrorFlag(DCCOMP0_BASE);
    DCCOMP_clearDoneFlag(DCCOMP0_BASE);

    //
    // Set the priority group to indicate the PREEMPT and SUB priority bits.
    //
    Interrupt_setPriorityGroup(INTERRUPT_PRIGROUP_PREEMPT_7_6_SUB_5_0);

    //
    // Set the global and group interrupt priority to allow CPU interrupts
    // with higher priority
    Interrupt_setPriority(INT_DCCOMP, 0, 0);

    //
    // Interrupts that are used in this example are re-mapped to ISR functions
    // found within this file.
    //
    Interrupt_register(INT_DCCOMP, &DCCOMP_ISR);

    //
    // Enable interrupts required for this example
    //
    Interrupt_enable(INT_DCCOMP);

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

    //
    // Continuous monitor of PLL clock using XTAL as reference clock
    // CLk1 = PLLRAW (Frequency = 250MHz)
    // CLk0 = XTAL   (Frequency = 20MHz)
    // Tolerance = 1%
    // Allowable Frequency Tolerance = 0% (update as per the error in the XTAL frequency)
    // SysClk Freq = 100MHz
    //
    // Note: Update the parameters in case you re using different PLL or XTAL
    // frequencies,
    //
    DCCOMP_continuousMonitor(DCCOMP0_BASE,
                             DCCOMP_COUNT1SRC_PLL, 200.0F,
                             DCCOMP_COUNT0SRC_XTAL, 20.0F,
                             1.0F, 0.0F, 200.0F);

    //
    // Disable MCD to prevent NMI generation due to missing clock
    // MCD to be handled by the DCCOMP
    //
    SysCtl_disableMCD();

    //
    // Turn off XTAL to simulate a missing clock
    //
    WRPRT_DISABLE;
    HWREGH(CLKCFG_BASE + SYSCTL_O_XTALCR) |= SYSCTL_XTALCR_OSCOFF;
    WRPRT_ENABLE;

    //
    // Wait till the ISR is hit on clock failure
    //
    while(isr_enter != 0x1U);

    //
    // Configure oscillator source to INTOSC1
    //
    SysCtl_selectOscSource(SYSCTL_OSCSRC_OSC1);

    //
    // Delay of at least 60 OSCCLK cycles
    //
    SysCtl_delay(11U);


    //
    // Turn off PLL
    //
    WRPRT_DISABLE;
    HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
        ~SYSCTL_SYSPLLCTL1_PLLEN;
    WRPRT_ENABLE;

    //
    // Delay of at least 66 OSCCLK cycles required post
    // powerdown of PLL
    //
    SysCtl_delay(12U);

    //
    // Status of the clock failure detection
    //
    if (pass == 0)
    {
        result = FAIL;
    }
    else
    {
        result = PASS;
    }

    ESTOP0;
    
    while(1);
}

//
// DCCOMP ISR triggered on an error
//
void DCCOMP_ISR()
{
    //
    // Shows that the ISR was called
    //
    isr_enter = 1;

    //
    // A clock failure was detected
    //
    pass++;

    if (DCCOMP_getErrorStatus(DCCOMP0_BASE) == 1U)
    {
        //
        // Clear the Error flag
        //
        DCCOMP_clearErrorFlag(DCCOMP0_BASE);
    }
}

