//#############################################################################
//
// FILE:    boot_ex1_errorstatuspin.c
//
// TITLE:   Boot Error Status Pin Example with DCS OTP
//
// VERSION: 1.0.0
//
// DATE:    2025-01-15
//
//! \addtogroup driver_example_list
//! <h1> Boot Error Status Pin Example with DCS OTP</h1>
//!
//! This example demonstrates how to configure the boot modes, boot mode select
//! pins, and error status pin.
//!
//! NOTE: DCS OTP (one time programmable) memory is used to configure the boot
//! modes, boot mode select pins, and error status pin. Once the DCS OTP
//! sections are programmed, they cannot be erased and programmed again.
//!
//! This example is designed to show how to configure boot control as well as
//! the function of the error status pin. Once the error status pin is enabled,
//! an NMI will be triggered by software and the error status pin will go high.
//! Then the NMI ISR will clear error status and drive the error status pin
//! low and return to the main loop where the NMI will be triggered again. More
//! details are available in the "ROM Code and Peripheral Booting" chapter of
//! the User Manual.
//!
//! \b External \b Connections \n
//!  - Scope the error status pin used according to what is programmed into
//!    GPREG2. The error status pin may be either GPIO 24, GPIO 28, or GPIO 29.
//!
//! \b Watch \b Variables \n
//!  - None.
//!
//
//###########################################################################
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//
// Modifications:
// - 2024-09-13:
// 1. Modify some comments, macros, function names, and function contents.
//
//###########################################################################


//
// Included Files
//
#include "driverlib.h"
#include "device.h"

//
// Globals
//
volatile uint32_t counter = 0;

//
// Function Prototypes
//
__interrupt void NMI_Handler(void);

//
// Main
//
void example_main(void)
{
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Initialize GPIO and configure the GPIO pin as a push-pull output
    //
    Device_initGPIO();

    //
    // Disable global interrupts.
    //
    DINT;

    //
    // Initialize NVIC and clear NVIC registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the NVIC vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Map the ISR to the NMI interrupt.
    //
    Interrupt_register(INT_NMI, NMI_Handler);

    //
    // Set the priority group to indicate the PREEMPT and SUB priortiy bits.
    //
    Interrupt_setPriorityGroup(INTERRUPT_PRIGROUP_PREEMPT_7_6_SUB_5_0);

    //
    // Set the global and group priority to allow CPU interrupts
    // with higher priority
    //
    Interrupt_setPriority(INT_NMI, 2, 0);

    //
    // Clear all NMI flags and enable the nmi interrupt.
    //
    SysCtl_clearAllNMIFlags();
    Interrupt_enable(INT_NMI);

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

    //
    // Loop Forever
    //
    for (;;)
    {
        //
        // Force the NMI by software which causes the error status
        // pin low.
        //
        SysCtl_forceNMIFlags(SYSCTL_NMI_SWERR);

        //
        // Delay for a 500000 microseconds.
        //
        DEVICE_DELAY_US(500000);
    }
}

//
// nmiISR - Non-Maskable Interrupt which should have been triggered by software
//          in the main loop.
//
__interrupt void NMI_Handler(void)
{
    //
    // Increment the counter each time the ISR is entered.
    //
    counter++;

    //
    // Delay for a 50 microseconds.
    //
    DEVICE_DELAY_US(50);

    //
    // Clear the NMI flag and NMIINT to cause the error status
    // pin to go high.
    //
    SysCtl_clearNMIStatus(SYSCTL_NMI_SWERR);
}

//
// End of File
//
