#ifndef _GW3323_H
#define _GW3323_H

#include "include.h"

typedef enum {
    DISABLE         = 0,
    ENABLE          = 1,
} FUNCTIONAL_STATE;

typedef enum {
    RESET           = 0,
    SET             = 1,
} FLAG_STATE;

//------------- Interrupt Number DECLARATION -------------//
typedef enum {
    ICACHE_DCACHE_MISS_IRQn,
    BT_BLE_BTDM_IRQn,
    SOFT_IRQn,
    TMR0_IRQn,
    TMR1_IRQn,
    TMR2_IRQn,
    IR_REVEIVER_IRQn,
    USB_CONTROL_IRQn,
    SD_IRQn,
    AUDIO_BUF0_BUF1_IRQn,
    SDADC_DMA_PBF_DMA_IRQn,
    AUDIO_CODEC_SBC_ENCODE_AEC_FFT_IRQn,
    PLC_CVSD_IRQn,
    PIANO_SDADC_IRQn,
    UARTx_IRQn,
    HSUART_DVP_IRQn,
    TMR3_IRQn,
    TMR4_IRQn,
    TMR5_IRQn,
    GPDMA_IRQn,
    SPIx_IRQn,
    UARTx_KEY_IRQn,
    BT_TX_RX_IRQn,
    FREQUENCY_DET_TOUCH_KEY_IQRn,
    DAC_DMA_RNN_RDFT_HWMATH_IRQn,
    SRC_IRQn,
    PORT_IRQn,
    IIS_IRQn,
    SARADC_IRQn,
    RTC_LVD_WDT_IRQn,
    IIC_BSP_IRQn,
    TICKx_IRQn,
} IRQ_TYPEDEF;

//----------------- SFR BASE DECLARATION -----------------//
#define SFR_BASE     0x00000000
#define SFR0_BASE   (0x00000000 + 0x000)
#define SFR1_BASE   (0x00000000 + 0x100)
#define SFR2_BASE   (0x00000000 + 0x200)
#define SFR3_BASE   (0x00000000 + 0x300)
#define SFR4_BASE   (0x00000000 + 0x400)
#define SFR5_BASE   (0x00000000 + 0x500)
#define SFR6_BASE   (0x00000000 + 0x600)
#define SFR7_BASE   (0x00000000 + 0x700)
#define SFR8_BASE   (0x00000000 + 0x800)
#define SFR9_BASE   (0x00000000 + 0x900)
#define SFR10_BASE  (0x00000000 + 0xa00)
#define SFR11_BASE  (0x00000000 + 0xb00)
#define SFR12_BASE  (0x00000000 + 0xc00)
#define SFR13_BASE  (0x00000000 + 0xd00)
#define SFR14_BASE  (0x00000000 + 0xe00)
#define SFR15_BASE  (0x00000000 + 0xf00)

//---------------------- SFR Group0 ----------------------//
#define UART0_BASE  (SFR0_BASE + 0x40)
#define TMR0_BASE   (SFR0_BASE + 0x50)
#define WDT_BASE    (SFR0_BASE + 0x68)
#define SD0_BASE    (SFR0_BASE + 0x80)
#define SPI0_BASE   (SFR0_BASE + 0xa8)
#define UART1_BASE  (SFR0_BASE + 0xc0)
#define TMR1_BASE   (SFR0_BASE + 0xd4)
#define TMR2_BASE   (SFR0_BASE + 0xe8)
//---------------------- SFR Group1 ----------------------//

//---------------------- SFR Group3 ----------------------//
#define HSUART_BASE (SFR3_BASE + 0xc0)

//---------------------- SFR Group4 ----------------------//

//---------------------- SFR Group5 ----------------------//
#define IIC_BASE    (SFR5_BASE + 0x1c)
#define SADC_BASE   (SFR5_BASE + 0x80)

//---------------------- SFR Group6 ----------------------//
#define GPIOA_BASE  (SFR6_BASE + 0x00)
#define GPIOB_BASE  (SFR6_BASE + 0x40)
#define GPIOE_BASE  (SFR6_BASE + 0x80)
#define GPIOF_BASE  (SFR6_BASE + 0xc0)

//---------------------- SFR Group7 ----------------------//
#define GPIOG_BASE  (SFR7_BASE + 0x00)

//---------------------- SFR Group8 ----------------------//

//---------------------- SFR Group9 ----------------------//
#define TMR3_BASE   (SFR9_BASE + 0x00)
#define TMR4_BASE   (SFR9_BASE + 0x20)
#define TMR5_BASE   (SFR9_BASE + 0x40)
#define UART2_BASE  (SFR9_BASE + 0x60)
#define SPI1_BASE   (SFR9_BASE + 0x80)

//---------------- PERIPHERAL DECLARATION ----------------//
#define GPIOA_REG   ((gpio_typedef *) GPIOA_BASE)
#define GPIOB_REG   ((gpio_typedef *) GPIOB_BASE)
#define GPIOE_REG   ((gpio_typedef *) GPIOE_BASE)
#define GPIOF_REG   ((gpio_typedef *) GPIOF_BASE)
#define GPIOG_REG   ((gpio_typedef *) GPIOG_BASE)
#define UART0       ((uart_typedef *) UART0_BASE)
#define UART1       ((uart_typedef *) UART1_BASE)
#define UART2       ((uart_typedef *) UART2_BASE)
#define TMR0        ((tmr_typedef *) TMR0_BASE)
#define TMR1        ((tmr_typedef *) TMR1_BASE)
#define TMR2        ((tmr_typedef *) TMR2_BASE)
#define TMR3        ((tmr_typedef *) TMR3_BASE)
#define TMR4        ((tmr_typedef *) TMR4_BASE)
#define TMR5        ((tmr_typedef *) TMR5_BASE)
#define HSUART      ((hsuart_typedef*) HSUART_BASE)
#define IIC         ((iic_typedef *) IIC_BASE)
#define SADC        ((sadc_typedef *) SADC_BASE)
#define SPI0        ((spi_typedef *) SPI0_BASE)
#define SPI1        ((spi_typedef *) SPI1_BASE)
#define SDIO        ((sdio_typedef *) SD0_BASE)
#define WDT         ((wdt_typedef *) WDT_BASE)


//-------------- Bit definition for uart_con --------------//
#define UART_CON_RXPND          0x00000200
#define UART_CON_TXPND          0x00000100
#define UART_CON_RXEN           0x00000080
#define UART_CON_ONELINE        0x00000040
#define UART_CON_CLKSRC         0x00000020
#define UART_CON_SB2EN          0x00000010
#define UART_CON_TXIE           0x00000008
#define UART_CON_RXIE           0x00000004
#define UART_CON_BIT9EN         0x00000002
#define UART_CON_UTEN           0x00000001

//-------------- Bit definition for uart_cpnd --------------//
#define UART_CPND_CRSTKEYPND    0x00020000
#define UART_CPND_CKEYPND       0x00010000
#define UART_CPND_CRXPND        0x00000200
#define UART_CPND_CTXPND        0x00000100

//-------------- Bit definition for tmr[0..2]_con --------------//
#define TMR_CON1_TPND           0x00000200
#define TMR_CON1_TIE            0x00000080
#define TMR_CON1_INCSRC         0x00000040
#define TMR_CON1_INCSEL         0x0000000c
#define TMR_CON1_TMREN          0x00000001

//-------------- Bit definition for tmr[3..5]_con --------------//
#define TMR_CON2_CPND           0x00020000
#define TMR_CON2_TPND           0x00010000
#define TMR_CON2_PWM2EN         0x00000800
#define TMR_CON2_PWM1EN         0x00000400
#define TMR_CON2_PWM0EN         0x00000200
#define TMR_CON2_CIE            0x00000100
#define TMR_CON2_TIE            0x00000080
#define TMR_CON2_INCSRC         0x00000040
#define TMR_CON2_CPTEDSEL       0x00000030
#define TMR_CON2_INCSEL         0x0000000c
#define TMR_CON2_CPTEN          0x00000002
#define TMR_CON2_TMREN          0x00000001

//------------------ Bit definition for RTCCON ------------------//
#define RTC_CON_WKSLPPND        0x00040000
#define RTC_CON_ALMPND          0x00020000
#define RTC_CON_ALMIE           0x00000010
#define RTC_CON_1SIE            0x00000008

//----------------- Bit definition for RTCCPND ------------------//
#define RTC_CPND_CWKSLPPND      0x00040000
#define RTC_CPND_CALMPND        0x00020000

//----------------- Bit definition for RTCCON0 -----------------//
#define RTC_CON0_RCSEL          0x00004000
#define RTC_CON0_CLK2MRTCSSEL   0x00000100
#define RTC_CON0_EXT32KS        0x00000040
#define RTC_CON0_CLK2MEN        0x00000004
#define RTC_CON0_RCEN           0x00000001

//----------------- Bit definition for RTCCON2 -----------------//
#define RTC_CON2_32KSEL         0x00000040

//----------------- Bit definition for RTCCON11 -----------------//
#define RTC_CON11_WKSLPEN       0x00000400
#define RTC_CON11_WKSLPS        0x00000300

//----------------- Bit definition for HSUT0CON -----------------//
#define HSUT0_CON_UPTXCFG       0x00020000
#define HSUT0_CON_UPRXCFG       0x00010000
#define HSUT0_CON_TMROV         0x00008000
#define HSUT0_CON_RXFAIL        0x00004000
#define HSUT0_CON_TXPND         0x00002000
#define HSUT0_CON_RXPND         0x00001000
#define HSUT0_CON_RXOVPND       0x00000800
#define HSUT0_CON_HSUTTMREN_NS  0x00000400
#define HSUT0_CON_SPBITSEL_NS   0x00000200
#define HSUT0_CON_TXBITSEL_NS   0x00000100
#define HSUT0_CON_TXTRSMODE     0x00000080
#define HSUT0_CON_RXLPBUFEN     0x00000040
#define HSUT0_CON_RXBITSEL_NS   0x00000020
#define HSUT0_CON_RXTRSMODE     0x00000010
#define HSUT0_CON_TXIE          0x00000008
#define HSUT0_CON_RXIE          0x00000004
#define HSUT0_CON_UTXEN_NS      0x00000002
#define HSUT0_CON_URXEN_NS      0x00000001

//-------------- Bit definition for saradc con --------------//
#define SADC_CON_ADCAEN         0x00080000
#define SADC_CON_ADCANGIOEN     0x00040000
#define SADC_CON_ADCIEN         0x00020000
#define SADC_CON_ADCEN          0x00010000
#define SADC_CON_CH15PUEN       0x00008000
#define SADC_CON_CH14PUEN       0x00004000
#define SADC_CON_CH13PUEN       0x00002000
#define SADC_CON_CH12PUEN       0x00001000
#define SADC_CON_CH11PUEN       0x00000800
#define SADC_CON_CH10PUEN       0x00000400
#define SADC_CON_CH9PUEN        0x00000200
#define SADC_CON_CH8PUEN        0x00000100
#define SADC_CON_CH7PUEN        0x00000080
#define SADC_CON_CH6PUEN        0x00000040
#define SADC_CON_CH5PUEN        0x00000020
#define SADC_CON_CH4PUEN        0x00000010
#define SADC_CON_CH3PUEN        0x00000008
#define SADC_CON_CH2PUEN        0x00000004
#define SADC_CON_CH1PUEN        0x00000002
#define SADC_CON_CH0PUEN        0x00000001

//-------------- Bit definition for spi[0..1]_con --------------//
#define SPI_CON_SPIPND          0x00010000
#define SPI_CON_HOLDENSW        0x00002000
#define SPI_CON_HOLDENTX        0x00001000
#define SPI_CON_HOLDENRX        0x00000800
#define SPI_CON_SPIOSS          0x00000400
#define SPI_CON_SPIMBEN         0x00000200
#define SPI_CON_SPILF_EN        0x00000100
#define SPI_CON_SPIIE           0x00000080
#define SPI_CON_SMPS            0x00000040
#define SPI_CON_CLKIDS          0x00000020
#define SPI_CON_SPISEL          0x00000010
#define SPI_CON_SPISM           0x00000002
#define SPI_CON_SPIEN           0x00000001

//-------------- Bit definition for IICCON0 --------------//
#define IIC_CON0_DONE           0x80000000
#define IIC_CON0_ACKSTATUS      0x40000000
#define IIC_CON0_CLR_DONE       0x20000000
#define IIC_CON0_KS             0x10000000
#define IIC_CON0_CLR_ALL        0x08000000
#define IIC_CON0_POSDIV         0x000003f0
#define IIC_CON0_HOLDCNT        0x0000000c
#define IIC_CON0_INTEN          0x00000002
#define IIC_CON0_IICEN          0x00000001

//-------------- Bit definition for IICCON1 --------------//
#define IIC_CON1_TXNAK_EN       0x00001000
#define IIC_CON1_STOP_EN        0x00000800
#define IIC_CON1_WDAT_EN        0x00000400
#define IIC_CON1_RDAT_EN        0x00000200
#define IIC_CON1_CTL1_EN        0x00000100
#define IIC_CON1_START1_EN      0x00000080
#define IIC_CON1_ADR1_EN        0x00000040
#define IIC_CON1_ADR0_EN        0x00000020
#define IIC_CON1_CTL0_EN        0x00000010
#define IIC_CON1_START0_EN      0x00000008
#define IIC_CON1_DATA_CNT       0x00000007

//-------------- Bit definition for sdio con --------------//
#define SDIO_CON_CLKIDIE        0x00000040
#define IIC_CON0_ACKSTATUS      0x40000000
#define SDIO_CON_DATIE          0x00000020
#define SDIO_CON_CMDIE          0x00000010
#define SDIO_CON_CKEN           0x00000008
#define SDIO_CON_OUTEDGE        0x00000004
#define SDIO_CON_DWTH           0x00000002
#define SDIO_CON_SDEN           0x00000001

//-------------- Bit definition for wdt con --------------//
#define WDT_CON_WDTEN           0x00000010
#define WDT_CON_RSTEN           0x00000100
#define WDT_CON_WDTIE           0x00001000
#define WDT_CON_WDTSEL          0x00010000


//gpio register structure
typedef struct {
  volatile u32 io_set;
  volatile u32 io_clr;
  volatile u32 dr;
  volatile u32 dir;
  volatile u32 de;
  volatile u32 fen;
  volatile u32 drv;
  volatile u32 pupd[6];
} gpio_typedef;

//uart register structure
typedef struct {
    volatile u32 con;
    volatile u32 cpnd;
    volatile u32 baud;
    volatile u32 data;
} uart_typedef;

//timer register structure
typedef struct {
    volatile u32 con;
    volatile u32 cpnd;
    volatile u32 cnt;
    volatile u32 pr;
    // only tmr3/4/5 can configure the following regisgter
    volatile u32 cpt_val;
    volatile u32 duty0;
    volatile u32 duty1;
    volatile u32 duty2;
} tmr_typedef;

//high speed uart register structure
typedef struct {
    volatile u32 con;
    volatile u32 cpnd;
    volatile u32 baud;
    volatile u32 data;
    volatile u32 tx_cnt;
    volatile u32 tx_adr;
    volatile u32 rx_cnt;
    volatile u32 const reserved0;
    volatile u32 const reserved1;
    volatile u32 rx_adr;
    volatile u32 fifo_cnt;
    volatile u32 fifo;
    volatile u32 fifo_adr;
    volatile u32 tmr_cnt;
} hsuart_typedef;

//iic register structure
typedef struct {
    volatile u32 con0;
    volatile u32 con1;
    volatile u32 cmda;
    volatile u32 data;
} iic_typedef;

//saradc register structure
typedef struct {
    volatile u32 dat[16];
    volatile u32 con;
    volatile u32 ch;
    volatile u32 cst;
    volatile u32 baud;
} sadc_typedef;

//spi register structure
typedef struct {
    volatile u32 con;
    volatile u32 buf;
    volatile u32 baud;
    volatile u32 cpnd;
    volatile u32 dma_cnt;
    volatile u32 dma_adr;
} spi_typedef;

//sdio register structure
typedef struct {
    volatile u32 con;
    volatile u32 cpnd;
    volatile u32 baud;
    volatile u32 cmd;
    volatile u32 arg3;
    volatile u32 arg2;
    volatile u32 arg1;
    volatile u32 arg0;
    volatile u32 dma_adr;
    volatile u32 dma_cnt;
} sdio_typedef;

//wdt register structure
typedef struct {
    volatile u32 con;
} wdt_typedef;

extern const u32 SYS_CLOCK_DEFINITION[8];

#endif // _GW3323_H
